1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/ADT/DenseMap.h"
23 class X86RegisterInfo
;
24 class X86TargetMachine
;
27 // Enums for memory operand decoding. Each memory operand is represented with
28 // a 5 operand sequence in the form:
29 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
30 // These enums help decode this.
37 /// AddrSegmentReg - The operand # of the segment in the memory operand.
40 /// AddrNumOperands - Total number of operands in a memory reference.
45 // X86 specific condition code. These correspond to X86_*_COND in
46 // X86InstrInfo.td. They must be kept in synch.
65 // Artificial condition codes. These are used by AnalyzeBranch
66 // to indicate a block terminated with two conditional branches to
67 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
68 // which can't be represented on x86 with a single condition. These
69 // are never used in MachineInstrs.
76 // Turn condition code into conditional branch opcode.
77 unsigned GetCondBranchFromCond(CondCode CC
);
79 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
80 /// e.g. turning COND_E to COND_NE.
81 CondCode
GetOppositeBranchCondition(X86::CondCode CC
);
85 /// X86II - This namespace holds all of the target specific flags that
86 /// instruction info tracks.
89 /// Target Operand Flag enum.
91 //===------------------------------------------------------------------===//
92 // X86 Specific MachineOperand flags.
96 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
98 /// SYMBOL_LABEL + [. - PICBASELABEL]
99 MO_GOT_ABSOLUTE_ADDRESS
,
101 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
102 /// immediate should get the value of the symbol minus the PIC base label:
103 /// SYMBOL_LABEL - PICBASELABEL
106 /// MO_GOT - On a symbol operand this indicates that the immediate is the
107 /// offset to the GOT entry for the symbol name from the base of the GOT.
109 /// See the X86-64 ELF ABI supplement for more details.
110 /// SYMBOL_LABEL @GOT
113 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
114 /// the offset to the location of the symbol name from the base of the GOT.
116 /// See the X86-64 ELF ABI supplement for more details.
117 /// SYMBOL_LABEL @GOTOFF
120 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
121 /// offset to the GOT entry for the symbol name from the current code
124 /// See the X86-64 ELF ABI supplement for more details.
125 /// SYMBOL_LABEL @GOTPCREL
128 /// MO_PLT - On a symbol operand this indicates that the immediate is
129 /// offset to the PLT entry of symbol name from the current code location.
131 /// See the X86-64 ELF ABI supplement for more details.
132 /// SYMBOL_LABEL @PLT
135 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
138 /// See 'ELF Handling for Thread-Local Storage' for more details.
139 /// SYMBOL_LABEL @TLSGD
142 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
145 /// See 'ELF Handling for Thread-Local Storage' for more details.
146 /// SYMBOL_LABEL @GOTTPOFF
149 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
152 /// See 'ELF Handling for Thread-Local Storage' for more details.
153 /// SYMBOL_LABEL @INDNTPOFF
156 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
159 /// See 'ELF Handling for Thread-Local Storage' for more details.
160 /// SYMBOL_LABEL @TPOFF
163 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
166 /// See 'ELF Handling for Thread-Local Storage' for more details.
167 /// SYMBOL_LABEL @NTPOFF
170 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
171 /// reference is actually to the "__imp_FOO" symbol. This is used for
172 /// dllimport linkage on windows.
175 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
176 /// reference is actually to the "FOO$stub" symbol. This is used for calls
177 /// and jumps to external functions on Tiger and before.
180 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
181 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
182 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
185 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
186 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
187 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
188 MO_DARWIN_NONLAZY_PIC_BASE
,
190 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
191 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
192 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer
194 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE
,
196 /// MO_TLVP - On a symbol operand this indicates that the immediate is
199 /// This is the TLS offset for the Darwin TLS mechanism.
202 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
203 /// is some TLS offset from the picbase.
205 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
210 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
211 /// a reference to a stub for a global, not the global itself.
212 inline static bool isGlobalStubReference(unsigned char TargetFlag
) {
213 switch (TargetFlag
) {
214 case X86II::MO_DLLIMPORT
: // dllimport stub.
215 case X86II::MO_GOTPCREL
: // rip-relative GOT reference.
216 case X86II::MO_GOT
: // normal GOT reference.
217 case X86II::MO_DARWIN_NONLAZY_PIC_BASE
: // Normal $non_lazy_ptr ref.
218 case X86II::MO_DARWIN_NONLAZY
: // Normal $non_lazy_ptr ref.
219 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE
: // Hidden $non_lazy_ptr ref.
226 /// isGlobalRelativeToPICBase - Return true if the specified global value
227 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
228 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
229 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag
) {
230 switch (TargetFlag
) {
231 case X86II::MO_GOTOFF
: // isPICStyleGOT: local global.
232 case X86II::MO_GOT
: // isPICStyleGOT: other global.
233 case X86II::MO_PIC_BASE_OFFSET
: // Darwin local global.
234 case X86II::MO_DARWIN_NONLAZY_PIC_BASE
: // Darwin/32 external global.
235 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE
: // Darwin/32 hidden global.
236 case X86II::MO_TLVP
: // ??? Pretty sure..
243 /// X86II - This namespace holds all of the target specific flags that
244 /// instruction info tracks.
248 //===------------------------------------------------------------------===//
249 // Instruction encodings. These are the standard/most common forms for X86
253 // PseudoFrm - This represents an instruction that is a pseudo instruction
254 // or one that has not been implemented yet. It is illegal to code generate
255 // it, but tolerated for intermediate implementation stages.
258 /// Raw - This form is for instructions that don't have any operands, so
259 /// they are just a fixed opcode value, like 'leave'.
262 /// AddRegFrm - This form is used for instructions like 'push r32' that have
263 /// their one register operand added to their opcode.
266 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
267 /// to specify a destination, which in this case is a register.
271 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
272 /// to specify a destination, which in this case is memory.
276 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
277 /// to specify a source, which in this case is a register.
281 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
282 /// to specify a source, which in this case is memory.
286 /// MRM[0-7][rm] - These forms are used to represent instructions that use
287 /// a Mod/RM byte, and use the middle field to hold extended opcode
288 /// information. In the intel manual these are represented as /0, /1, ...
291 // First, instructions that operate on a register r/m operand...
292 MRM0r
= 16, MRM1r
= 17, MRM2r
= 18, MRM3r
= 19, // Format /0 /1 /2 /3
293 MRM4r
= 20, MRM5r
= 21, MRM6r
= 22, MRM7r
= 23, // Format /4 /5 /6 /7
295 // Next, instructions that operate on a memory r/m operand...
296 MRM0m
= 24, MRM1m
= 25, MRM2m
= 26, MRM3m
= 27, // Format /0 /1 /2 /3
297 MRM4m
= 28, MRM5m
= 29, MRM6m
= 30, MRM7m
= 31, // Format /4 /5 /6 /7
299 // MRMInitReg - This form is used for instructions whose source and
300 // destinations are the same register.
303 //// MRM_C1 - A mod/rm byte of exactly 0xC1.
317 //===------------------------------------------------------------------===//
320 // OpSize - Set if this instruction requires an operand size prefix (0x66),
321 // which most often indicates that the instruction operates on 16 bit data
322 // instead of 32 bit data.
325 // AsSize - Set if this instruction requires an operand size prefix (0x67),
326 // which most often indicates that the instruction address 16 bit address
327 // instead of 32 bit address (or 32 bit address in 64 bit mode).
330 //===------------------------------------------------------------------===//
331 // Op0Mask - There are several prefix bytes that are used to form two byte
332 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
333 // used to obtain the setting of this field. If no bits in this field is
334 // set, there is no prefix byte for obtaining a multibyte opcode.
337 Op0Mask
= 0xF << Op0Shift
,
339 // TB - TwoByte - Set if this instruction has a two byte opcode, which
340 // starts with a 0x0F byte before the real opcode.
343 // REP - The 0xF3 prefix byte indicating repetition of the following
347 // D8-DF - These escape opcodes are used by the floating point unit. These
348 // values must remain sequential.
349 D8
= 3 << Op0Shift
, D9
= 4 << Op0Shift
,
350 DA
= 5 << Op0Shift
, DB
= 6 << Op0Shift
,
351 DC
= 7 << Op0Shift
, DD
= 8 << Op0Shift
,
352 DE
= 9 << Op0Shift
, DF
= 10 << Op0Shift
,
354 // XS, XD - These prefix codes are for single and double precision scalar
355 // floating point operations performed in the SSE registers.
356 XD
= 11 << Op0Shift
, XS
= 12 << Op0Shift
,
358 // T8, TA - Prefix after the 0x0F prefix.
359 T8
= 13 << Op0Shift
, TA
= 14 << Op0Shift
,
361 // TF - Prefix before and after 0x0F
364 //===------------------------------------------------------------------===//
365 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
366 // They are used to specify GPRs and SSE registers, 64-bit operand size,
367 // etc. We only cares about REX.W and REX.R bits and only the former is
368 // statically determined.
371 REX_W
= 1 << REXShift
,
373 //===------------------------------------------------------------------===//
374 // This three-bit field describes the size of an immediate operand. Zero is
375 // unused so that we can tell if we forgot to set a value.
377 ImmMask
= 7 << ImmShift
,
378 Imm8
= 1 << ImmShift
,
379 Imm8PCRel
= 2 << ImmShift
,
380 Imm16
= 3 << ImmShift
,
381 Imm16PCRel
= 4 << ImmShift
,
382 Imm32
= 5 << ImmShift
,
383 Imm32PCRel
= 6 << ImmShift
,
384 Imm64
= 7 << ImmShift
,
386 //===------------------------------------------------------------------===//
387 // FP Instruction Classification... Zero is non-fp instruction.
389 // FPTypeMask - Mask for all of the FP types...
391 FPTypeMask
= 7 << FPTypeShift
,
393 // NotFP - The default, set for instructions that do not use FP registers.
394 NotFP
= 0 << FPTypeShift
,
396 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
397 ZeroArgFP
= 1 << FPTypeShift
,
399 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
400 OneArgFP
= 2 << FPTypeShift
,
402 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
403 // result back to ST(0). For example, fcos, fsqrt, etc.
405 OneArgFPRW
= 3 << FPTypeShift
,
407 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
408 // explicit argument, storing the result to either ST(0) or the implicit
409 // argument. For example: fadd, fsub, fmul, etc...
410 TwoArgFP
= 4 << FPTypeShift
,
412 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
413 // explicit argument, but have no destination. Example: fucom, fucomi, ...
414 CompareFP
= 5 << FPTypeShift
,
416 // CondMovFP - "2 operand" floating point conditional move instructions.
417 CondMovFP
= 6 << FPTypeShift
,
419 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
420 SpecialFP
= 7 << FPTypeShift
,
424 LOCK
= 1 << LOCKShift
,
426 // Segment override prefixes. Currently we just need ability to address
427 // stuff in gs and fs segments.
429 SegOvrMask
= 3 << SegOvrShift
,
430 FS
= 1 << SegOvrShift
,
431 GS
= 2 << SegOvrShift
,
433 // Execution domain for SSE instructions in bits 22, 23.
434 // 0 in bits 22-23 means normal, non-SSE instruction.
438 OpcodeMask
= 0xFF << OpcodeShift
,
440 //===------------------------------------------------------------------===//
441 // VEX - The opcode prefix used by AVX instructions
444 // VEX_W - Has a opcode specific functionality, but is used in the same
445 // way as REX_W is for regular SSE instructions.
448 // VEX_4V - Used to specify an additional AVX/SSE register. Several 2
449 // address instructions in SSE are represented as 3 address ones in AVX
450 // and the additional register is encoded in VEX_VVVV prefix.
453 // VEX_I8IMM - Specifies that the last register used in a AVX instruction,
454 // must be encoded in the i8 immediate field. This usually happens in
455 // instructions with 4 operands.
456 VEX_I8IMM
= 1ULL << 35
459 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
460 // specified machine instruction.
462 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags
) {
463 return TSFlags
>> X86II::OpcodeShift
;
466 static inline bool hasImm(uint64_t TSFlags
) {
467 return (TSFlags
& X86II::ImmMask
) != 0;
470 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
471 /// of the specified instruction.
472 static inline unsigned getSizeOfImm(uint64_t TSFlags
) {
473 switch (TSFlags
& X86II::ImmMask
) {
474 default: assert(0 && "Unknown immediate size");
476 case X86II::Imm8PCRel
: return 1;
478 case X86II::Imm16PCRel
: return 2;
480 case X86II::Imm32PCRel
: return 4;
481 case X86II::Imm64
: return 8;
485 /// isImmPCRel - Return true if the immediate of the specified instruction's
486 /// TSFlags indicates that it is pc relative.
487 static inline unsigned isImmPCRel(uint64_t TSFlags
) {
488 switch (TSFlags
& X86II::ImmMask
) {
489 default: assert(0 && "Unknown immediate size");
490 case X86II::Imm8PCRel
:
491 case X86II::Imm16PCRel
:
492 case X86II::Imm32PCRel
:
502 /// getMemoryOperandNo - The function returns the MCInst operand # for the
503 /// first field of the memory operand. If the instruction doesn't have a
504 /// memory operand, this returns -1.
506 /// Note that this ignores tied operands. If there is a tied register which
507 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
508 /// counted as one operand.
510 static inline int getMemoryOperandNo(uint64_t TSFlags
) {
511 switch (TSFlags
& X86II::FormMask
) {
512 case X86II::MRMInitReg
: assert(0 && "FIXME: Remove this form");
513 default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!");
516 case X86II::AddRegFrm
:
517 case X86II::MRMDestReg
:
518 case X86II::MRMSrcReg
:
520 case X86II::MRMDestMem
:
522 case X86II::MRMSrcMem
: {
523 bool HasVEX_4V
= TSFlags
& X86II::VEX_4V
;
524 unsigned FirstMemOp
= 1;
526 ++FirstMemOp
;// Skip the register source (which is encoded in VEX_VVVV).
528 // FIXME: Maybe lea should have its own form? This is a horrible hack.
529 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
530 // Opcode == X86::LEA16r || Opcode == X86::LEA32r)
533 case X86II::MRM0r
: case X86II::MRM1r
:
534 case X86II::MRM2r
: case X86II::MRM3r
:
535 case X86II::MRM4r
: case X86II::MRM5r
:
536 case X86II::MRM6r
: case X86II::MRM7r
:
538 case X86II::MRM0m
: case X86II::MRM1m
:
539 case X86II::MRM2m
: case X86II::MRM3m
:
540 case X86II::MRM4m
: case X86II::MRM5m
:
541 case X86II::MRM6m
: case X86II::MRM7m
:
558 inline static bool isScale(const MachineOperand
&MO
) {
560 (MO
.getImm() == 1 || MO
.getImm() == 2 ||
561 MO
.getImm() == 4 || MO
.getImm() == 8);
564 inline static bool isLeaMem(const MachineInstr
*MI
, unsigned Op
) {
565 if (MI
->getOperand(Op
).isFI()) return true;
566 return Op
+4 <= MI
->getNumOperands() &&
567 MI
->getOperand(Op
).isReg() && isScale(MI
->getOperand(Op
+1)) &&
568 MI
->getOperand(Op
+2).isReg() &&
569 (MI
->getOperand(Op
+3).isImm() ||
570 MI
->getOperand(Op
+3).isGlobal() ||
571 MI
->getOperand(Op
+3).isCPI() ||
572 MI
->getOperand(Op
+3).isJTI());
575 inline static bool isMem(const MachineInstr
*MI
, unsigned Op
) {
576 if (MI
->getOperand(Op
).isFI()) return true;
577 return Op
+5 <= MI
->getNumOperands() &&
578 MI
->getOperand(Op
+4).isReg() &&
582 class X86InstrInfo
: public TargetInstrInfoImpl
{
583 X86TargetMachine
&TM
;
584 const X86RegisterInfo RI
;
586 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
587 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
589 DenseMap
<unsigned*, std::pair
<unsigned,unsigned> > RegOp2MemOpTable2Addr
;
590 DenseMap
<unsigned*, std::pair
<unsigned,unsigned> > RegOp2MemOpTable0
;
591 DenseMap
<unsigned*, std::pair
<unsigned,unsigned> > RegOp2MemOpTable1
;
592 DenseMap
<unsigned*, std::pair
<unsigned,unsigned> > RegOp2MemOpTable2
;
594 /// MemOp2RegOpTable - Load / store unfolding opcode map.
596 DenseMap
<unsigned*, std::pair
<unsigned, unsigned> > MemOp2RegOpTable
;
599 explicit X86InstrInfo(X86TargetMachine
&tm
);
601 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
602 /// such, whenever a client has an instance of instruction info, it should
603 /// always be able to get register info as well (through this method).
605 virtual const X86RegisterInfo
&getRegisterInfo() const { return RI
; }
607 /// Return true if the instruction is a register to register move and return
608 /// the source and dest operands and their sub-register indices by reference.
609 virtual bool isMoveInstr(const MachineInstr
&MI
,
610 unsigned &SrcReg
, unsigned &DstReg
,
611 unsigned &SrcSubIdx
, unsigned &DstSubIdx
) const;
613 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
614 /// extension instruction. That is, it's like a copy where it's legal for the
615 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
616 /// true, then it's expected the pre-extension value is available as a subreg
617 /// of the result register. This also returns the sub-register index in
619 virtual bool isCoalescableExtInstr(const MachineInstr
&MI
,
620 unsigned &SrcReg
, unsigned &DstReg
,
621 unsigned &SubIdx
) const;
623 unsigned isLoadFromStackSlot(const MachineInstr
*MI
, int &FrameIndex
) const;
624 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
625 /// stack locations as well. This uses a heuristic so it isn't
626 /// reliable for correctness.
627 unsigned isLoadFromStackSlotPostFE(const MachineInstr
*MI
,
628 int &FrameIndex
) const;
630 /// hasLoadFromStackSlot - If the specified machine instruction has
631 /// a load from a stack slot, return true along with the FrameIndex
632 /// of the loaded stack slot and the machine mem operand containing
633 /// the reference. If not, return false. Unlike
634 /// isLoadFromStackSlot, this returns true for any instructions that
635 /// loads from the stack. This is a hint only and may not catch all
637 bool hasLoadFromStackSlot(const MachineInstr
*MI
,
638 const MachineMemOperand
*&MMO
,
639 int &FrameIndex
) const;
641 unsigned isStoreToStackSlot(const MachineInstr
*MI
, int &FrameIndex
) const;
642 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
643 /// stack locations as well. This uses a heuristic so it isn't
644 /// reliable for correctness.
645 unsigned isStoreToStackSlotPostFE(const MachineInstr
*MI
,
646 int &FrameIndex
) const;
648 /// hasStoreToStackSlot - If the specified machine instruction has a
649 /// store to a stack slot, return true along with the FrameIndex of
650 /// the loaded stack slot and the machine mem operand containing the
651 /// reference. If not, return false. Unlike isStoreToStackSlot,
652 /// this returns true for any instructions that loads from the
653 /// stack. This is a hint only and may not catch all cases.
654 bool hasStoreToStackSlot(const MachineInstr
*MI
,
655 const MachineMemOperand
*&MMO
,
656 int &FrameIndex
) const;
658 bool isReallyTriviallyReMaterializable(const MachineInstr
*MI
,
659 AliasAnalysis
*AA
) const;
660 void reMaterialize(MachineBasicBlock
&MBB
, MachineBasicBlock::iterator MI
,
661 unsigned DestReg
, unsigned SubIdx
,
662 const MachineInstr
*Orig
,
663 const TargetRegisterInfo
&TRI
) const;
665 /// convertToThreeAddress - This method must be implemented by targets that
666 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
667 /// may be able to convert a two-address instruction into a true
668 /// three-address instruction on demand. This allows the X86 target (for
669 /// example) to convert ADD and SHL instructions into LEA instructions if they
670 /// would require register copies due to two-addressness.
672 /// This method returns a null pointer if the transformation cannot be
673 /// performed, otherwise it returns the new instruction.
675 virtual MachineInstr
*convertToThreeAddress(MachineFunction::iterator
&MFI
,
676 MachineBasicBlock::iterator
&MBBI
,
677 LiveVariables
*LV
) const;
679 /// commuteInstruction - We have a few instructions that must be hacked on to
682 virtual MachineInstr
*commuteInstruction(MachineInstr
*MI
, bool NewMI
) const;
685 virtual bool isUnpredicatedTerminator(const MachineInstr
* MI
) const;
686 virtual bool AnalyzeBranch(MachineBasicBlock
&MBB
, MachineBasicBlock
*&TBB
,
687 MachineBasicBlock
*&FBB
,
688 SmallVectorImpl
<MachineOperand
> &Cond
,
689 bool AllowModify
) const;
690 virtual unsigned RemoveBranch(MachineBasicBlock
&MBB
) const;
691 virtual unsigned InsertBranch(MachineBasicBlock
&MBB
, MachineBasicBlock
*TBB
,
692 MachineBasicBlock
*FBB
,
693 const SmallVectorImpl
<MachineOperand
> &Cond
,
695 virtual bool copyRegToReg(MachineBasicBlock
&MBB
,
696 MachineBasicBlock::iterator MI
,
697 unsigned DestReg
, unsigned SrcReg
,
698 const TargetRegisterClass
*DestRC
,
699 const TargetRegisterClass
*SrcRC
,
701 virtual void copyPhysReg(MachineBasicBlock
&MBB
,
702 MachineBasicBlock::iterator MI
, DebugLoc DL
,
703 unsigned DestReg
, unsigned SrcReg
,
705 virtual void storeRegToStackSlot(MachineBasicBlock
&MBB
,
706 MachineBasicBlock::iterator MI
,
707 unsigned SrcReg
, bool isKill
, int FrameIndex
,
708 const TargetRegisterClass
*RC
,
709 const TargetRegisterInfo
*TRI
) const;
711 virtual void storeRegToAddr(MachineFunction
&MF
, unsigned SrcReg
, bool isKill
,
712 SmallVectorImpl
<MachineOperand
> &Addr
,
713 const TargetRegisterClass
*RC
,
714 MachineInstr::mmo_iterator MMOBegin
,
715 MachineInstr::mmo_iterator MMOEnd
,
716 SmallVectorImpl
<MachineInstr
*> &NewMIs
) const;
718 virtual void loadRegFromStackSlot(MachineBasicBlock
&MBB
,
719 MachineBasicBlock::iterator MI
,
720 unsigned DestReg
, int FrameIndex
,
721 const TargetRegisterClass
*RC
,
722 const TargetRegisterInfo
*TRI
) const;
724 virtual void loadRegFromAddr(MachineFunction
&MF
, unsigned DestReg
,
725 SmallVectorImpl
<MachineOperand
> &Addr
,
726 const TargetRegisterClass
*RC
,
727 MachineInstr::mmo_iterator MMOBegin
,
728 MachineInstr::mmo_iterator MMOEnd
,
729 SmallVectorImpl
<MachineInstr
*> &NewMIs
) const;
731 virtual bool spillCalleeSavedRegisters(MachineBasicBlock
&MBB
,
732 MachineBasicBlock::iterator MI
,
733 const std::vector
<CalleeSavedInfo
> &CSI
,
734 const TargetRegisterInfo
*TRI
) const;
736 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock
&MBB
,
737 MachineBasicBlock::iterator MI
,
738 const std::vector
<CalleeSavedInfo
> &CSI
,
739 const TargetRegisterInfo
*TRI
) const;
742 MachineInstr
*emitFrameIndexDebugValue(MachineFunction
&MF
,
743 int FrameIx
, uint64_t Offset
,
747 /// foldMemoryOperand - If this target supports it, fold a load or store of
748 /// the specified stack slot into the specified machine instruction for the
749 /// specified operand(s). If this is possible, the target should perform the
750 /// folding and return true, otherwise it should return false. If it folds
751 /// the instruction, it is likely that the MachineInstruction the iterator
752 /// references has been changed.
753 virtual MachineInstr
* foldMemoryOperandImpl(MachineFunction
&MF
,
755 const SmallVectorImpl
<unsigned> &Ops
,
756 int FrameIndex
) const;
758 /// foldMemoryOperand - Same as the previous version except it allows folding
759 /// of any load and store from / to any address, not just from a specific
761 virtual MachineInstr
* foldMemoryOperandImpl(MachineFunction
&MF
,
763 const SmallVectorImpl
<unsigned> &Ops
,
764 MachineInstr
* LoadMI
) const;
766 /// canFoldMemoryOperand - Returns true if the specified load / store is
767 /// folding is possible.
768 virtual bool canFoldMemoryOperand(const MachineInstr
*,
769 const SmallVectorImpl
<unsigned> &) const;
771 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
772 /// a store or a load and a store into two or more instruction. If this is
773 /// possible, returns true as well as the new instructions by reference.
774 virtual bool unfoldMemoryOperand(MachineFunction
&MF
, MachineInstr
*MI
,
775 unsigned Reg
, bool UnfoldLoad
, bool UnfoldStore
,
776 SmallVectorImpl
<MachineInstr
*> &NewMIs
) const;
778 virtual bool unfoldMemoryOperand(SelectionDAG
&DAG
, SDNode
*N
,
779 SmallVectorImpl
<SDNode
*> &NewNodes
) const;
781 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
782 /// instruction after load / store are unfolded from an instruction of the
783 /// specified opcode. It returns zero if the specified unfolding is not
784 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
785 /// index of the operand which will hold the register holding the loaded
787 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc
,
788 bool UnfoldLoad
, bool UnfoldStore
,
789 unsigned *LoadRegIndex
= 0) const;
791 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
792 /// to determine if two loads are loading from the same base address. It
793 /// should only return true if the base pointers are the same and the
794 /// only differences between the two addresses are the offset. It also returns
795 /// the offsets by reference.
796 virtual bool areLoadsFromSameBasePtr(SDNode
*Load1
, SDNode
*Load2
,
797 int64_t &Offset1
, int64_t &Offset2
) const;
799 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
800 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
801 /// be scheduled togther. On some targets if two loads are loading from
802 /// addresses in the same cache line, it's better if they are scheduled
803 /// together. This function takes two integers that represent the load offsets
804 /// from the common base address. It returns true if it decides it's desirable
805 /// to schedule the two loads together. "NumLoads" is the number of loads that
806 /// have already been scheduled after Load1.
807 virtual bool shouldScheduleLoadsNear(SDNode
*Load1
, SDNode
*Load2
,
808 int64_t Offset1
, int64_t Offset2
,
809 unsigned NumLoads
) const;
811 virtual void getNoopForMachoTarget(MCInst
&NopInst
) const;
814 bool ReverseBranchCondition(SmallVectorImpl
<MachineOperand
> &Cond
) const;
816 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
817 /// instruction that defines the specified register class.
818 bool isSafeToMoveRegClassDefs(const TargetRegisterClass
*RC
) const;
820 static bool isX86_64NonExtLowByteReg(unsigned reg
) {
821 return (reg
== X86::SPL
|| reg
== X86::BPL
||
822 reg
== X86::SIL
|| reg
== X86::DIL
);
825 static bool isX86_64ExtendedReg(const MachineOperand
&MO
) {
826 if (!MO
.isReg()) return false;
827 return isX86_64ExtendedReg(MO
.getReg());
829 static unsigned determineREX(const MachineInstr
&MI
);
831 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
832 /// higher) register? e.g. r8, xmm8, xmm13, etc.
833 static bool isX86_64ExtendedReg(unsigned RegNo
);
835 /// GetInstSize - Returns the size of the specified MachineInstr.
837 virtual unsigned GetInstSizeInBytes(const MachineInstr
*MI
) const;
839 /// getGlobalBaseReg - Return a virtual register initialized with the
840 /// the global base register value. Output instructions required to
841 /// initialize the register in the function entry block, if necessary.
843 unsigned getGlobalBaseReg(MachineFunction
*MF
) const;
845 /// GetSSEDomain - Return the SSE execution domain of MI as the first element,
846 /// and a bitmask of possible arguments to SetSSEDomain ase the second.
847 std::pair
<uint16_t, uint16_t> GetSSEDomain(const MachineInstr
*MI
) const;
849 /// SetSSEDomain - Set the SSEDomain of MI.
850 void SetSSEDomain(MachineInstr
*MI
, unsigned Domain
) const;
853 MachineInstr
* convertToThreeAddressWithLEA(unsigned MIOpc
,
854 MachineFunction::iterator
&MFI
,
855 MachineBasicBlock::iterator
&MBBI
,
856 LiveVariables
*LV
) const;
858 MachineInstr
* foldMemoryOperandImpl(MachineFunction
&MF
,
861 const SmallVectorImpl
<MachineOperand
> &MOs
,
862 unsigned Size
, unsigned Alignment
) const;
864 /// isFrameOperand - Return true and the FrameIndex if the specified
865 /// operand and follow operands form a reference to the stack frame.
866 bool isFrameOperand(const MachineInstr
*MI
, unsigned int Op
,
867 int &FrameIndex
) const;
870 } // End llvm namespace