1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetFrameLowering.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Type.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo
&tii
)
39 : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN
, XCore::ADJCALLSTACKUP
),
44 static inline bool isImmUs(unsigned val
) {
48 static inline bool isImmU6(unsigned val
) {
49 return val
< (1 << 6);
52 static inline bool isImmU16(unsigned val
) {
53 return val
< (1 << 16);
56 static const unsigned XCore_ArgRegs
[] = {
57 XCore::R0
, XCore::R1
, XCore::R2
, XCore::R3
60 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction
*MF
)
65 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction
*MF
)
67 return array_lengthof(XCore_ArgRegs
);
70 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction
&MF
) {
71 return MF
.getMMI().hasDebugInfo() || !MF
.getFunction()->doesNotThrow() ||
72 UnwindTablesMandatory
;
75 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction
*MF
)
77 static const unsigned CalleeSavedRegs
[] = {
78 XCore::R4
, XCore::R5
, XCore::R6
, XCore::R7
,
79 XCore::R8
, XCore::R9
, XCore::R10
, XCore::LR
,
82 return CalleeSavedRegs
;
85 BitVector
XCoreRegisterInfo::getReservedRegs(const MachineFunction
&MF
) const {
86 BitVector
Reserved(getNumRegs());
87 const TargetFrameLowering
*TFI
= MF
.getTarget().getFrameLowering();
89 Reserved
.set(XCore::CP
);
90 Reserved
.set(XCore::DP
);
91 Reserved
.set(XCore::SP
);
92 Reserved
.set(XCore::LR
);
94 Reserved
.set(XCore::R10
);
100 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction
&MF
) const {
101 const TargetFrameLowering
*TFI
= MF
.getTarget().getFrameLowering();
103 // TODO can we estimate stack size?
104 return TFI
->hasFP(MF
);
107 // This function eliminates ADJCALLSTACKDOWN,
108 // ADJCALLSTACKUP pseudo instructions
109 void XCoreRegisterInfo::
110 eliminateCallFramePseudoInstr(MachineFunction
&MF
, MachineBasicBlock
&MBB
,
111 MachineBasicBlock::iterator I
) const {
112 const TargetFrameLowering
*TFI
= MF
.getTarget().getFrameLowering();
114 if (!TFI
->hasReservedCallFrame(MF
)) {
115 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
116 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
117 MachineInstr
*Old
= I
;
118 uint64_t Amount
= Old
->getOperand(0).getImm();
120 // We need to keep the stack aligned properly. To do this, we round the
121 // amount of space needed for the outgoing arguments up to the next
122 // alignment boundary.
123 unsigned Align
= TFI
->getStackAlignment();
124 Amount
= (Amount
+Align
-1)/Align
*Align
;
126 assert(Amount
%4 == 0);
129 bool isU6
= isImmU6(Amount
);
130 if (!isU6
&& !isImmU16(Amount
)) {
131 // FIX could emit multiple instructions in this case.
133 errs() << "eliminateCallFramePseudoInstr size too big: "
140 if (Old
->getOpcode() == XCore::ADJCALLSTACKDOWN
) {
141 int Opcode
= isU6
? XCore::EXTSP_u6
: XCore::EXTSP_lu6
;
142 New
=BuildMI(MF
, Old
->getDebugLoc(), TII
.get(Opcode
))
145 assert(Old
->getOpcode() == XCore::ADJCALLSTACKUP
);
146 int Opcode
= isU6
? XCore::LDAWSP_ru6_RRegs
: XCore::LDAWSP_lru6_RRegs
;
147 New
=BuildMI(MF
, Old
->getDebugLoc(), TII
.get(Opcode
), XCore::SP
)
151 // Replace the pseudo instruction with a new instruction...
160 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II
,
161 int SPAdj
, RegScavenger
*RS
) const {
162 assert(SPAdj
== 0 && "Unexpected");
163 MachineInstr
&MI
= *II
;
164 DebugLoc dl
= MI
.getDebugLoc();
167 while (!MI
.getOperand(i
).isFI()) {
169 assert(i
< MI
.getNumOperands() && "Instr doesn't have FrameIndex operand!");
172 MachineOperand
&FrameOp
= MI
.getOperand(i
);
173 int FrameIndex
= FrameOp
.getIndex();
175 MachineFunction
&MF
= *MI
.getParent()->getParent();
176 const TargetFrameLowering
*TFI
= MF
.getTarget().getFrameLowering();
177 int Offset
= MF
.getFrameInfo()->getObjectOffset(FrameIndex
);
178 int StackSize
= MF
.getFrameInfo()->getStackSize();
181 DEBUG(errs() << "\nFunction : "
182 << MF
.getFunction()->getName() << "\n");
183 DEBUG(errs() << "<--------->\n");
184 DEBUG(MI
.print(errs()));
185 DEBUG(errs() << "FrameIndex : " << FrameIndex
<< "\n");
186 DEBUG(errs() << "FrameOffset : " << Offset
<< "\n");
187 DEBUG(errs() << "StackSize : " << StackSize
<< "\n");
192 // fold constant into offset.
193 Offset
+= MI
.getOperand(i
+ 1).getImm();
194 MI
.getOperand(i
+ 1).ChangeToImmediate(0);
196 assert(Offset
%4 == 0 && "Misaligned stack offset");
198 DEBUG(errs() << "Offset : " << Offset
<< "\n" << "<--------->\n");
202 bool FP
= TFI
->hasFP(MF
);
204 unsigned Reg
= MI
.getOperand(0).getReg();
205 bool isKill
= MI
.getOpcode() == XCore::STWFI
&& MI
.getOperand(0).isKill();
207 assert(XCore::GRRegsRegisterClass
->contains(Reg
) &&
208 "Unexpected register operand");
210 MachineBasicBlock
&MBB
= *MI
.getParent();
213 bool isUs
= isImmUs(Offset
);
214 unsigned FramePtr
= XCore::R10
;
218 report_fatal_error("eliminateFrameIndex Frame size too big: " +
220 unsigned ScratchReg
= RS
->scavengeRegister(XCore::GRRegsRegisterClass
, II
,
222 loadConstant(MBB
, II
, ScratchReg
, Offset
, dl
);
223 switch (MI
.getOpcode()) {
225 BuildMI(MBB
, II
, dl
, TII
.get(XCore::LDW_3r
), Reg
)
227 .addReg(ScratchReg
, RegState::Kill
);
230 BuildMI(MBB
, II
, dl
, TII
.get(XCore::STW_3r
))
231 .addReg(Reg
, getKillRegState(isKill
))
233 .addReg(ScratchReg
, RegState::Kill
);
236 BuildMI(MBB
, II
, dl
, TII
.get(XCore::LDAWF_l3r
), Reg
)
238 .addReg(ScratchReg
, RegState::Kill
);
241 llvm_unreachable("Unexpected Opcode");
244 switch (MI
.getOpcode()) {
246 BuildMI(MBB
, II
, dl
, TII
.get(XCore::LDW_2rus
), Reg
)
251 BuildMI(MBB
, II
, dl
, TII
.get(XCore::STW_2rus
))
252 .addReg(Reg
, getKillRegState(isKill
))
257 BuildMI(MBB
, II
, dl
, TII
.get(XCore::LDAWF_l2rus
), Reg
)
262 llvm_unreachable("Unexpected Opcode");
266 bool isU6
= isImmU6(Offset
);
267 if (!isU6
&& !isImmU16(Offset
))
268 report_fatal_error("eliminateFrameIndex Frame size too big: " +
271 switch (MI
.getOpcode()) {
274 NewOpcode
= (isU6
) ? XCore::LDWSP_ru6
: XCore::LDWSP_lru6
;
275 BuildMI(MBB
, II
, dl
, TII
.get(NewOpcode
), Reg
)
279 NewOpcode
= (isU6
) ? XCore::STWSP_ru6
: XCore::STWSP_lru6
;
280 BuildMI(MBB
, II
, dl
, TII
.get(NewOpcode
))
281 .addReg(Reg
, getKillRegState(isKill
))
285 NewOpcode
= (isU6
) ? XCore::LDAWSP_ru6
: XCore::LDAWSP_lru6
;
286 BuildMI(MBB
, II
, dl
, TII
.get(NewOpcode
), Reg
)
290 llvm_unreachable("Unexpected Opcode");
293 // Erase old instruction.
297 void XCoreRegisterInfo::
298 loadConstant(MachineBasicBlock
&MBB
, MachineBasicBlock::iterator I
,
299 unsigned DstReg
, int64_t Value
, DebugLoc dl
) const {
300 // TODO use mkmsk if possible.
301 if (!isImmU16(Value
)) {
302 // TODO use constant pool.
303 report_fatal_error("loadConstant value too big " + Twine(Value
));
305 int Opcode
= isImmU6(Value
) ? XCore::LDC_ru6
: XCore::LDC_lru6
;
306 BuildMI(MBB
, I
, dl
, TII
.get(Opcode
), DstReg
).addImm(Value
);
309 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum
, bool isEH
) const {
310 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum
, 0);
313 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction
&MF
) const {
314 const TargetFrameLowering
*TFI
= MF
.getTarget().getFrameLowering();
316 return TFI
->hasFP(MF
) ? XCore::R10
: XCore::SP
;
319 unsigned XCoreRegisterInfo::getRARegister() const {
323 #include "XCoreGenRegisterInfo.inc"