lib/CodeGen/MachineRegisterInfo.cpp

   1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Implementation of the MachineRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/CodeGen/MachineRegisterInfo.h"
  15 #include "llvm/CodeGen/MachineInstrBuilder.h"
  16 #include "llvm/Target/TargetInstrInfo.h"
  17 #include "llvm/Support/CommandLine.h"
  18 using namespace llvm;
  19
  20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
  21   VRegInfo.reserve(256);
  22   RegAllocHints.reserve(256);
  23   RegClass2VRegMap = new std::vector<unsigned>[TRI.getNumRegClasses()];
  24   UsedPhysRegs.resize(TRI.getNumRegs());
  25
  26   // Create the physreg use/def lists.
  27   PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
  28   memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
  29 }
  30
  31 MachineRegisterInfo::~MachineRegisterInfo() {
  32 #ifndef NDEBUG
  33   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
  34     assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
  35            "Vreg use list non-empty still?");
  36   for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
  37     assert(!PhysRegUseDefLists[i] &&
  38            "PhysRegUseDefLists has entries after all instructions are deleted");
  39 #endif
  40   delete [] PhysRegUseDefLists;
  41   delete [] RegClass2VRegMap;
  42 }
  43
  44 /// setRegClass - Set the register class of the specified virtual register.
  45 ///
  46 void
  47 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
  48   const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
  49   VRegInfo[Reg].first = RC;
  50
  51   // Remove from old register class's vregs list. This may be slow but
  52   // fortunately this operation is rarely needed.
  53   std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
  54   std::vector<unsigned>::iterator I =
  55     std::find(VRegs.begin(), VRegs.end(), Reg);
  56   VRegs.erase(I);
  57
  58   // Add to new register class's vregs list.
  59   RegClass2VRegMap[RC->getID()].push_back(Reg);
  60 }
  61
  62 const TargetRegisterClass *
  63 MachineRegisterInfo::constrainRegClass(unsigned Reg,
  64                                        const TargetRegisterClass *RC) {
  65   const TargetRegisterClass *OldRC = getRegClass(Reg);
  66   if (OldRC == RC)
  67     return RC;
  68   const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC);
  69   if (!NewRC)
  70     return 0;
  71   if (NewRC != OldRC)
  72     setRegClass(Reg, NewRC);
  73   return NewRC;
  74 }
  75
  76 /// createVirtualRegister - Create and return a new virtual register in the
  77 /// function with the specified register class.
  78 ///
  79 unsigned
  80 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
  81   assert(RegClass && "Cannot create register without RegClass!");
  82
  83   // New virtual register number.
  84   unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
  85
  86   // Add a reg, but keep track of whether the vector reallocated or not.
  87   const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0);
  88   void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg];
  89   VRegInfo.grow(Reg);
  90   VRegInfo[Reg].first = RegClass;
  91   RegAllocHints.grow(Reg);
  92
  93   if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase)
  94     // The vector reallocated, handle this now.
  95     HandleVRegListReallocation();
  96   RegClass2VRegMap[RegClass->getID()].push_back(Reg);
  97   return Reg;
  98 }
  99
 100 /// HandleVRegListReallocation - We just added a virtual register to the
 101 /// VRegInfo info list and it reallocated.  Update the use/def lists info
 102 /// pointers.
 103 void MachineRegisterInfo::HandleVRegListReallocation() {
 104   // The back pointers for the vreg lists point into the previous vector.
 105   // Update them to point to their correct slots.
 106   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
 107     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
 108     MachineOperand *List = VRegInfo[Reg].second;
 109     if (!List) continue;
 110     // Update the back-pointer to be accurate once more.
 111     List->Contents.Reg.Prev = &VRegInfo[Reg].second;
 112   }
 113 }
 114
 115 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
 116 /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
 117 /// except that it also changes any definitions of the register as well.
 118 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
 119   assert(FromReg != ToReg && "Cannot replace a reg with itself");
 120
 121   // TODO: This could be more efficient by bulk changing the operands.
 122   for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
 123     MachineOperand &O = I.getOperand();
 124     ++I;
 125     O.setReg(ToReg);
 126   }
 127 }
 128
 129
 130 /// getVRegDef - Return the machine instr that defines the specified virtual
 131 /// register or null if none is found.  This assumes that the code is in SSA
 132 /// form, so there should only be one definition.
 133 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
 134   // Since we are in SSA form, we can use the first definition.
 135   if (!def_empty(Reg))
 136     return &*def_begin(Reg);
 137   return 0;
 138 }
 139
 140 bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
 141   use_iterator UI = use_begin(RegNo);
 142   if (UI == use_end())
 143     return false;
 144   return ++UI == use_end();
 145 }
 146
 147 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
 148   use_nodbg_iterator UI = use_nodbg_begin(RegNo);
 149   if (UI == use_nodbg_end())
 150     return false;
 151   return ++UI == use_nodbg_end();
 152 }
 153
 154 /// clearKillFlags - Iterate over all the uses of the given register and
 155 /// clear the kill flag from the MachineOperand. This function is used by
 156 /// optimization passes which extend register lifetimes and need only
 157 /// preserve conservative kill flag information.
 158 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
 159   for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
 160     UI.getOperand().setIsKill(false);
 161 }
 162
 163 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
 164   for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
 165     if (I->first == Reg || I->second == Reg)
 166       return true;
 167   return false;
 168 }
 169
 170 bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
 171   for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
 172     if (*I == Reg)
 173       return true;
 174   return false;
 175 }
 176
 177 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
 178 /// corresponding live-in physical register.
 179 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
 180   for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
 181     if (I->second == VReg)
 182       return I->first;
 183   return 0;
 184 }
 185
 186 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
 187 /// corresponding live-in physical register.
 188 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
 189   for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
 190     if (I->first == PReg)
 191       return I->second;
 192   return 0;
 193 }
 194
 195 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
 196 /// into the given entry block.
 197 void
 198 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
 199                                       const TargetRegisterInfo &TRI,
 200                                       const TargetInstrInfo &TII) {
 201   // Emit the copies into the top of the block.
 202   for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
 203     if (LiveIns[i].second) {
 204       if (use_empty(LiveIns[i].second)) {
 205         // The livein has no uses. Drop it.
 206         //
 207         // It would be preferable to have isel avoid creating live-in
 208         // records for unused arguments in the first place, but it's
 209         // complicated by the debug info code for arguments.
 210         LiveIns.erase(LiveIns.begin() + i);
 211         --i; --e;
 212       } else {
 213         DebugLoc DL;
 214         // If there is a location for this live in then use it.
 215         DenseMap<unsigned, DebugLoc>::iterator DLI =
 216           LiveInLocs.find(LiveIns[i].second);
 217         if (DLI != LiveInLocs.end())
 218           DL = DLI->second;
 219
 220         // Emit a copy.
 221         BuildMI(*EntryMBB, EntryMBB->begin(), DL,
 222                 TII.get(TargetOpcode::COPY), LiveIns[i].second)
 223           .addReg(LiveIns[i].first);
 224
 225         // Add the register to the entry block live-in set.
 226         EntryMBB->addLiveIn(LiveIns[i].first);
 227       }
 228     } else {
 229       // Add the register to the entry block live-in set.
 230       EntryMBB->addLiveIn(LiveIns[i].first);
 231     }
 232 }
 233
 234 void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {
 235   for (int i = UsedPhysRegs.find_first(); i >= 0;
 236        i = UsedPhysRegs.find_next(i))
 237          for (const unsigned *SS = TRI.getSubRegisters(i);
 238               unsigned SubReg = *SS; ++SS)
 239            if (SubReg > unsigned(i))
 240              UsedPhysRegs.set(SubReg);
 241 }
 242
 243 #ifndef NDEBUG
 244 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
 245   for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
 246     I.getOperand().getParent()->dump();
 247 }
 248 #endif