When removing a function from the function set and adding it to deferred, we
[llvm.git] / lib / CodeGen / DeadMachineInstructionElim.cpp
blobfdc1d9142140b06a9aab44ff99e89a6effd539bc
1 //===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This is an extremely simple MachineInstr-level dead-code-elimination pass.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "codegen-dce"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Pass.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/ADT/Statistic.h"
24 using namespace llvm;
26 STATISTIC(NumDeletes, "Number of dead instructions deleted");
28 namespace {
29 class DeadMachineInstructionElim : public MachineFunctionPass {
30 virtual bool runOnMachineFunction(MachineFunction &MF);
32 const TargetRegisterInfo *TRI;
33 const MachineRegisterInfo *MRI;
34 const TargetInstrInfo *TII;
35 BitVector LivePhysRegs;
37 public:
38 static char ID; // Pass identification, replacement for typeid
39 DeadMachineInstructionElim() : MachineFunctionPass(ID) {
40 initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry());
43 private:
44 bool isDead(const MachineInstr *MI) const;
47 char DeadMachineInstructionElim::ID = 0;
49 INITIALIZE_PASS(DeadMachineInstructionElim, "dead-mi-elimination",
50 "Remove dead machine instructions", false, false)
52 FunctionPass *llvm::createDeadMachineInstructionElimPass() {
53 return new DeadMachineInstructionElim();
56 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
57 // Technically speaking inline asm without side effects and no defs can still
58 // be deleted. But there is so much bad inline asm code out there, we should
59 // let them be.
60 if (MI->isInlineAsm())
61 return false;
63 // Don't delete instructions with side effects.
64 bool SawStore = false;
65 if (!MI->isSafeToMove(TII, 0, SawStore) && !MI->isPHI())
66 return false;
68 // Examine each operand.
69 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
70 const MachineOperand &MO = MI->getOperand(i);
71 if (MO.isReg() && MO.isDef()) {
72 unsigned Reg = MO.getReg();
73 if (TargetRegisterInfo::isPhysicalRegister(Reg) ?
74 LivePhysRegs[Reg] : !MRI->use_nodbg_empty(Reg)) {
75 // This def has a non-debug use. Don't delete the instruction!
76 return false;
81 // If there are no defs with uses, the instruction is dead.
82 return true;
85 bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
86 bool AnyChanges = false;
87 MRI = &MF.getRegInfo();
88 TRI = MF.getTarget().getRegisterInfo();
89 TII = MF.getTarget().getInstrInfo();
91 // Treat reserved registers as always live.
92 BitVector ReservedRegs = TRI->getReservedRegs(MF);
94 // Loop over all instructions in all blocks, from bottom to top, so that it's
95 // more likely that chains of dependent but ultimately dead instructions will
96 // be cleaned up.
97 for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
98 I != E; ++I) {
99 MachineBasicBlock *MBB = &*I;
101 // Start out assuming that reserved registers are live out of this block.
102 LivePhysRegs = ReservedRegs;
104 // Also add any explicit live-out physregs for this block.
105 if (!MBB->empty() && MBB->back().getDesc().isReturn())
106 for (MachineRegisterInfo::liveout_iterator LOI = MRI->liveout_begin(),
107 LOE = MRI->liveout_end(); LOI != LOE; ++LOI) {
108 unsigned Reg = *LOI;
109 if (TargetRegisterInfo::isPhysicalRegister(Reg))
110 LivePhysRegs.set(Reg);
113 // FIXME: Add live-ins from sucessors to LivePhysRegs. Normally, physregs
114 // are not live across blocks, but some targets (x86) can have flags live
115 // out of a block.
117 // Now scan the instructions and delete dead ones, tracking physreg
118 // liveness as we go.
119 for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
120 MIE = MBB->rend(); MII != MIE; ) {
121 MachineInstr *MI = &*MII;
123 // If the instruction is dead, delete it!
124 if (isDead(MI)) {
125 DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
126 // It is possible that some DBG_VALUE instructions refer to this
127 // instruction. Examine each def operand for such references;
128 // if found, mark the DBG_VALUE as undef (but don't delete it).
129 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
130 const MachineOperand &MO = MI->getOperand(i);
131 if (!MO.isReg() || !MO.isDef())
132 continue;
133 unsigned Reg = MO.getReg();
134 if (!TargetRegisterInfo::isVirtualRegister(Reg))
135 continue;
136 MachineRegisterInfo::use_iterator nextI;
137 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
138 E = MRI->use_end(); I!=E; I=nextI) {
139 nextI = llvm::next(I); // I is invalidated by the setReg
140 MachineOperand& Use = I.getOperand();
141 MachineInstr *UseMI = Use.getParent();
142 if (UseMI==MI)
143 continue;
144 assert(Use.isDebug());
145 UseMI->getOperand(0).setReg(0U);
148 AnyChanges = true;
149 MI->eraseFromParent();
150 ++NumDeletes;
151 MIE = MBB->rend();
152 // MII is now pointing to the next instruction to process,
153 // so don't increment it.
154 continue;
157 // Record the physreg defs.
158 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
159 const MachineOperand &MO = MI->getOperand(i);
160 if (MO.isReg() && MO.isDef()) {
161 unsigned Reg = MO.getReg();
162 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
163 LivePhysRegs.reset(Reg);
164 // Check the subreg set, not the alias set, because a def
165 // of a super-register may still be partially live after
166 // this def.
167 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
168 *SubRegs; ++SubRegs)
169 LivePhysRegs.reset(*SubRegs);
173 // Record the physreg uses, after the defs, in case a physreg is
174 // both defined and used in the same instruction.
175 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
176 const MachineOperand &MO = MI->getOperand(i);
177 if (MO.isReg() && MO.isUse()) {
178 unsigned Reg = MO.getReg();
179 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
180 LivePhysRegs.set(Reg);
181 for (const unsigned *AliasSet = TRI->getAliasSet(Reg);
182 *AliasSet; ++AliasSet)
183 LivePhysRegs.set(*AliasSet);
188 // We didn't delete the current instruction, so increment MII to
189 // the next one.
190 ++MII;
194 LivePhysRegs.clear();
195 return AnyChanges;