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1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
13 //
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
41 SDTCisSameAs<0,2>]>>;
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
73 SDTCisVT<1, v4f32>,
74 SDTCisVT<2, v4f32>]>;
75 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
77 //===----------------------------------------------------------------------===//
78 // SSE Complex Patterns
79 //===----------------------------------------------------------------------===//
81 // These are 'extloads' from a scalar to the low element of a vector, zeroing
82 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
83 // forms.
84 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
85 [SDNPHasChain, SDNPMayLoad]>;
86 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
87 [SDNPHasChain, SDNPMayLoad]>;
89 def ssmem : Operand<v4f32> {
90 let PrintMethod = "printf32mem";
91 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
92 let ParserMatchClass = X86MemAsmOperand;
93 }
94 def sdmem : Operand<v2f64> {
95 let PrintMethod = "printf64mem";
96 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
97 let ParserMatchClass = X86MemAsmOperand;
98 }
100 //===----------------------------------------------------------------------===//
101 // SSE pattern fragments
102 //===----------------------------------------------------------------------===//
104 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
105 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
106 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
107 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
109 // Like 'store', but always requires vector alignment.
110 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
111 (store node:$val, node:$ptr), [{
112 return cast<StoreSDNode>(N)->getAlignment() >= 16;
113 }]>;
115 // Like 'load', but always requires vector alignment.
116 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
117 return cast<LoadSDNode>(N)->getAlignment() >= 16;
118 }]>;
120 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
121 (f32 (alignedload node:$ptr))>;
122 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
123 (f64 (alignedload node:$ptr))>;
124 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
125 (v4f32 (alignedload node:$ptr))>;
126 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
127 (v2f64 (alignedload node:$ptr))>;
128 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
129 (v4i32 (alignedload node:$ptr))>;
130 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
131 (v2i64 (alignedload node:$ptr))>;
133 // Like 'load', but uses special alignment checks suitable for use in
134 // memory operands in most SSE instructions, which are required to
135 // be naturally aligned on some targets but not on others. If the subtarget
136 // allows unaligned accesses, match any load, though this may require
137 // setting a feature bit in the processor (on startup, for example).
138 // Opteron 10h and later implement such a feature.
139 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
140 return Subtarget->hasVectorUAMem()
141 || cast<LoadSDNode>(N)->getAlignment() >= 16;
142 }]>;
144 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
145 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
146 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
147 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
148 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
149 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
150 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
152 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
153 // 16-byte boundary.
154 // FIXME: 8 byte alignment for mmx reads is not required
155 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
156 return cast<LoadSDNode>(N)->getAlignment() >= 8;
157 }]>;
159 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
160 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
161 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
162 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
164 // MOVNT Support
165 // Like 'store', but requires the non-temporal bit to be set
166 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
167 (st node:$val, node:$ptr), [{
168 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
169 return ST->isNonTemporal();
170 return false;
171 }]>;
173 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
174 (st node:$val, node:$ptr), [{
175 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
176 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
177 ST->getAddressingMode() == ISD::UNINDEXED &&
178 ST->getAlignment() >= 16;
179 return false;
180 }]>;
182 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
183 (st node:$val, node:$ptr), [{
184 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
185 return ST->isNonTemporal() &&
186 ST->getAlignment() < 16;
187 return false;
188 }]>;
190 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
191 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
192 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
193 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
194 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
195 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
197 def vzmovl_v2i64 : PatFrag<(ops node:$src),
198 (bitconvert (v2i64 (X86vzmovl
199 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
200 def vzmovl_v4i32 : PatFrag<(ops node:$src),
201 (bitconvert (v4i32 (X86vzmovl
202 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
204 def vzload_v2i64 : PatFrag<(ops node:$src),
205 (bitconvert (v2i64 (X86vzload node:$src)))>;
208 def fp32imm0 : PatLeaf<(f32 fpimm), [{
209 return N->isExactlyValue(+0.0);
210 }]>;
212 // BYTE_imm - Transform bit immediates into byte immediates.
213 def BYTE_imm : SDNodeXForm<imm, [{
214 // Transformation function: imm >> 3
215 return getI32Imm(N->getZExtValue() >> 3);
216 }]>;
218 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
219 // SHUFP* etc. imm.
220 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
221 return getI8Imm(X86::getShuffleSHUFImmediate(N));
222 }]>;
224 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
225 // PSHUFHW imm.
226 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
227 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
228 }]>;
230 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
231 // PSHUFLW imm.
232 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
233 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
234 }]>;
236 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
237 // a PALIGNR imm.
238 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
239 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
240 }]>;
242 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
243 (vector_shuffle node:$lhs, node:$rhs), [{
244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
245 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
246 }]>;
248 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
249 (vector_shuffle node:$lhs, node:$rhs), [{
250 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
251 }]>;
253 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
254 (vector_shuffle node:$lhs, node:$rhs), [{
255 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
256 }]>;
258 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
259 (vector_shuffle node:$lhs, node:$rhs), [{
260 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
261 }]>;
263 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
264 (vector_shuffle node:$lhs, node:$rhs), [{
265 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
266 }]>;
268 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
269 (vector_shuffle node:$lhs, node:$rhs), [{
270 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
271 }]>;
273 def movl : PatFrag<(ops node:$lhs, node:$rhs),
274 (vector_shuffle node:$lhs, node:$rhs), [{
275 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
276 }]>;
278 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
279 (vector_shuffle node:$lhs, node:$rhs), [{
280 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
281 }]>;
283 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
284 (vector_shuffle node:$lhs, node:$rhs), [{
285 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
286 }]>;
288 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
289 (vector_shuffle node:$lhs, node:$rhs), [{
290 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
291 }]>;
293 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
294 (vector_shuffle node:$lhs, node:$rhs), [{
295 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
296 }]>;
298 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
299 (vector_shuffle node:$lhs, node:$rhs), [{
300 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
301 }]>;
303 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
304 (vector_shuffle node:$lhs, node:$rhs), [{
305 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
306 }]>;
308 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
309 (vector_shuffle node:$lhs, node:$rhs), [{
310 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
311 }], SHUFFLE_get_shuf_imm>;
313 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
314 (vector_shuffle node:$lhs, node:$rhs), [{
315 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
316 }], SHUFFLE_get_shuf_imm>;
318 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
319 (vector_shuffle node:$lhs, node:$rhs), [{
320 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
321 }], SHUFFLE_get_pshufhw_imm>;
323 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
324 (vector_shuffle node:$lhs, node:$rhs), [{
325 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
326 }], SHUFFLE_get_pshuflw_imm>;
328 def palign : PatFrag<(ops node:$lhs, node:$rhs),
329 (vector_shuffle node:$lhs, node:$rhs), [{
330 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
331 }], SHUFFLE_get_palign_imm>;
333 //===----------------------------------------------------------------------===//
334 // SSE scalar FP Instructions
335 //===----------------------------------------------------------------------===//
337 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
338 // instruction selection into a branch sequence.
339 let Uses = [EFLAGS], usesCustomInserter = 1 in {
340 def CMOV_FR32 : I<0, Pseudo,
341 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
342 "#CMOV_FR32 PSEUDO!",
343 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
344 EFLAGS))]>;
345 def CMOV_FR64 : I<0, Pseudo,
346 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
347 "#CMOV_FR64 PSEUDO!",
348 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
349 EFLAGS))]>;
350 def CMOV_V4F32 : I<0, Pseudo,
351 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
352 "#CMOV_V4F32 PSEUDO!",
353 [(set VR128:$dst,
354 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
355 EFLAGS)))]>;
356 def CMOV_V2F64 : I<0, Pseudo,
357 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
358 "#CMOV_V2F64 PSEUDO!",
359 [(set VR128:$dst,
360 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
361 EFLAGS)))]>;
362 def CMOV_V2I64 : I<0, Pseudo,
363 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
364 "#CMOV_V2I64 PSEUDO!",
365 [(set VR128:$dst,
366 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
367 EFLAGS)))]>;
368 }
370 //===----------------------------------------------------------------------===//
371 // SSE 1 & 2 Instructions Classes
372 //===----------------------------------------------------------------------===//
374 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
375 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
376 RegisterClass RC, X86MemOperand x86memop> {
377 let isCommutable = 1 in {
378 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
379 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
380 }
381 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
382 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
383 }
385 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
386 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
387 string asm, string SSEVer, string FPSizeStr,
388 Operand memopr, ComplexPattern mem_cpat> {
389 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
390 asm, [(set RC:$dst, (
391 !nameconcat<Intrinsic>("int_x86_sse",
392 !strconcat(SSEVer, !strconcat("_",
393 !strconcat(OpcodeStr, FPSizeStr))))
394 RC:$src1, RC:$src2))]>;
395 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
396 asm, [(set RC:$dst, (
397 !nameconcat<Intrinsic>("int_x86_sse",
398 !strconcat(SSEVer, !strconcat("_",
399 !strconcat(OpcodeStr, FPSizeStr))))
400 RC:$src1, mem_cpat:$src2))]>;
401 }
403 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
404 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
405 RegisterClass RC, ValueType vt,
406 X86MemOperand x86memop, PatFrag mem_frag,
407 Domain d, bit MayLoad = 0> {
408 let isCommutable = 1 in
409 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
410 OpcodeStr, [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))],d>;
411 let mayLoad = MayLoad in
412 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
413 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
414 (mem_frag addr:$src2)))],d>;
415 }
417 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
418 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
419 string OpcodeStr, X86MemOperand x86memop,
420 list<dag> pat_rr, list<dag> pat_rm> {
421 let isCommutable = 1 in
422 def rr : PI<opc, MRMSrcReg, (outs RC:$dst),
423 (ins RC:$src1, RC:$src2), OpcodeStr, pat_rr, d>;
424 def rm : PI<opc, MRMSrcMem, (outs RC:$dst),
425 (ins RC:$src1, x86memop:$src2), OpcodeStr, pat_rm, d>;
426 }
428 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
429 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
430 string asm, string SSEVer, string FPSizeStr,
431 X86MemOperand x86memop, PatFrag mem_frag,
432 Domain d> {
433 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
434 asm, [(set RC:$dst, (
435 !nameconcat<Intrinsic>("int_x86_sse",
436 !strconcat(SSEVer, !strconcat("_",
437 !strconcat(OpcodeStr, FPSizeStr))))
438 RC:$src1, RC:$src2))], d>;
439 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
440 asm, [(set RC:$dst, (
441 !nameconcat<Intrinsic>("int_x86_sse",
442 !strconcat(SSEVer, !strconcat("_",
443 !strconcat(OpcodeStr, FPSizeStr))))
444 RC:$src1, (mem_frag addr:$src2)))], d>;
445 }
447 //===----------------------------------------------------------------------===//
448 // SSE 1 & 2 - Move Instructions
449 //===----------------------------------------------------------------------===//
451 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
452 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
453 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
455 // Loading from memory automatically zeroing upper bits.
456 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
457 PatFrag mem_pat, string OpcodeStr> :
458 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
459 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
460 [(set RC:$dst, (mem_pat addr:$src))]>;
462 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
463 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
464 // is used instead. Register-to-register movss/movsd is not modeled as an
465 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
466 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
467 let isAsmParserOnly = 1 in {
468 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
469 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
470 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
471 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
473 let canFoldAsLoad = 1, isReMaterializable = 1 in {
474 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
476 let AddedComplexity = 20 in
477 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
478 }
479 }
481 let Constraints = "$src1 = $dst" in {
482 def MOVSSrr : sse12_move_rr<FR32, v4f32,
483 "movss\t{$src2, $dst|$dst, $src2}">, XS;
484 def MOVSDrr : sse12_move_rr<FR64, v2f64,
485 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
486 }
488 let canFoldAsLoad = 1, isReMaterializable = 1 in {
489 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
491 let AddedComplexity = 20 in
492 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
493 }
495 let AddedComplexity = 15 in {
496 // Extract the low 32-bit value from one vector and insert it into another.
497 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
498 (MOVSSrr (v4f32 VR128:$src1),
499 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
500 // Extract the low 64-bit value from one vector and insert it into another.
501 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
502 (MOVSDrr (v2f64 VR128:$src1),
503 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
504 }
506 // Implicitly promote a 32-bit scalar to a vector.
507 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
508 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
509 // Implicitly promote a 64-bit scalar to a vector.
510 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
511 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
513 let AddedComplexity = 20 in {
514 // MOVSSrm zeros the high parts of the register; represent this
515 // with SUBREG_TO_REG.
516 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
517 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
518 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
519 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
520 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
521 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
522 // MOVSDrm zeros the high parts of the register; represent this
523 // with SUBREG_TO_REG.
524 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
525 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
526 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
527 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
528 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
529 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
530 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
531 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
532 def : Pat<(v2f64 (X86vzload addr:$src)),
533 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
534 }
536 // Store scalar value to memory.
537 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
538 "movss\t{$src, $dst|$dst, $src}",
539 [(store FR32:$src, addr:$dst)]>;
540 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
541 "movsd\t{$src, $dst|$dst, $src}",
542 [(store FR64:$src, addr:$dst)]>;
544 let isAsmParserOnly = 1 in {
545 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
546 "movss\t{$src, $dst|$dst, $src}",
547 [(store FR32:$src, addr:$dst)]>, XS, VEX_4V;
548 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
549 "movsd\t{$src, $dst|$dst, $src}",
550 [(store FR64:$src, addr:$dst)]>, XD, VEX_4V;
551 }
553 // Extract and store.
554 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
555 addr:$dst),
556 (MOVSSmr addr:$dst,
557 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
558 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
559 addr:$dst),
560 (MOVSDmr addr:$dst,
561 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
563 // Move Aligned/Unaligned floating point values
564 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
565 X86MemOperand x86memop, PatFrag ld_frag,
566 string asm, Domain d,
567 bit IsReMaterializable = 1> {
568 let neverHasSideEffects = 1 in
569 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
570 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
571 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
572 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
573 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
574 [(set RC:$dst, (ld_frag addr:$src))], d>;
575 }
577 let isAsmParserOnly = 1 in {
578 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
579 "movaps", SSEPackedSingle>, VEX;
580 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
581 "movapd", SSEPackedDouble>, OpSize, VEX;
582 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
583 "movups", SSEPackedSingle>, VEX;
584 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
585 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
586 }
587 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
588 "movaps", SSEPackedSingle>, TB;
589 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
590 "movapd", SSEPackedDouble>, TB, OpSize;
591 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
592 "movups", SSEPackedSingle>, TB;
593 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
594 "movupd", SSEPackedDouble, 0>, TB, OpSize;
596 let isAsmParserOnly = 1 in {
597 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
598 "movaps\t{$src, $dst|$dst, $src}",
599 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
600 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
601 "movapd\t{$src, $dst|$dst, $src}",
602 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
603 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
604 "movups\t{$src, $dst|$dst, $src}",
605 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
606 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
607 "movupd\t{$src, $dst|$dst, $src}",
608 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
609 }
610 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
611 "movaps\t{$src, $dst|$dst, $src}",
612 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
613 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
614 "movapd\t{$src, $dst|$dst, $src}",
615 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
616 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
617 "movups\t{$src, $dst|$dst, $src}",
618 [(store (v4f32 VR128:$src), addr:$dst)]>;
619 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
620 "movupd\t{$src, $dst|$dst, $src}",
621 [(store (v2f64 VR128:$src), addr:$dst)]>;
623 // Intrinsic forms of MOVUPS/D load and store
624 let isAsmParserOnly = 1 in {
625 let canFoldAsLoad = 1, isReMaterializable = 1 in
626 def VMOVUPSrm_Int : VPSI<0x10, MRMSrcMem, (outs VR128:$dst),
627 (ins f128mem:$src),
628 "movups\t{$src, $dst|$dst, $src}",
629 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>, VEX;
630 def VMOVUPDrm_Int : VPDI<0x10, MRMSrcMem, (outs VR128:$dst),
631 (ins f128mem:$src),
632 "movupd\t{$src, $dst|$dst, $src}",
633 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>, VEX;
634 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
635 (ins f128mem:$dst, VR128:$src),
636 "movups\t{$src, $dst|$dst, $src}",
637 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
638 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
639 (ins f128mem:$dst, VR128:$src),
640 "movupd\t{$src, $dst|$dst, $src}",
641 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
642 }
643 let canFoldAsLoad = 1, isReMaterializable = 1 in
644 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
645 "movups\t{$src, $dst|$dst, $src}",
646 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
647 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
648 "movupd\t{$src, $dst|$dst, $src}",
649 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
651 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
652 "movups\t{$src, $dst|$dst, $src}",
653 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
654 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
655 "movupd\t{$src, $dst|$dst, $src}",
656 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
658 // Move Low/High packed floating point values
659 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
660 PatFrag mov_frag, string base_opc,
661 string asm_opr> {
662 def PSrm : PI<opc, MRMSrcMem,
663 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
664 !strconcat(!strconcat(base_opc,"s"), asm_opr),
665 [(set RC:$dst,
666 (mov_frag RC:$src1,
667 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
668 SSEPackedSingle>, TB;
670 def PDrm : PI<opc, MRMSrcMem,
671 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
672 !strconcat(!strconcat(base_opc,"d"), asm_opr),
673 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
674 (scalar_to_vector (loadf64 addr:$src2)))))],
675 SSEPackedDouble>, TB, OpSize;
676 }
678 let isAsmParserOnly = 1, AddedComplexity = 20 in {
679 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
680 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
681 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
682 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
683 }
684 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
685 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
686 "\t{$src2, $dst|$dst, $src2}">;
687 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
688 "\t{$src2, $dst|$dst, $src2}">;
689 }
691 let isAsmParserOnly = 1 in {
692 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
693 "movlps\t{$src, $dst|$dst, $src}",
694 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
695 (iPTR 0))), addr:$dst)]>, VEX;
696 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
697 "movlpd\t{$src, $dst|$dst, $src}",
698 [(store (f64 (vector_extract (v2f64 VR128:$src),
699 (iPTR 0))), addr:$dst)]>, VEX;
700 }
701 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
702 "movlps\t{$src, $dst|$dst, $src}",
703 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
704 (iPTR 0))), addr:$dst)]>;
705 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
706 "movlpd\t{$src, $dst|$dst, $src}",
707 [(store (f64 (vector_extract (v2f64 VR128:$src),
708 (iPTR 0))), addr:$dst)]>;
710 // v2f64 extract element 1 is always custom lowered to unpack high to low
711 // and extract element 0 so the non-store version isn't too horrible.
712 let isAsmParserOnly = 1 in {
713 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
714 "movhps\t{$src, $dst|$dst, $src}",
715 [(store (f64 (vector_extract
716 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
717 (undef)), (iPTR 0))), addr:$dst)]>,
718 VEX;
719 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
720 "movhpd\t{$src, $dst|$dst, $src}",
721 [(store (f64 (vector_extract
722 (v2f64 (unpckh VR128:$src, (undef))),
723 (iPTR 0))), addr:$dst)]>,
724 VEX;
725 }
726 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
727 "movhps\t{$src, $dst|$dst, $src}",
728 [(store (f64 (vector_extract
729 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
730 (undef)), (iPTR 0))), addr:$dst)]>;
731 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
732 "movhpd\t{$src, $dst|$dst, $src}",
733 [(store (f64 (vector_extract
734 (v2f64 (unpckh VR128:$src, (undef))),
735 (iPTR 0))), addr:$dst)]>;
737 let isAsmParserOnly = 1, AddedComplexity = 20 in {
738 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
739 (ins VR128:$src1, VR128:$src2),
740 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
741 [(set VR128:$dst,
742 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
743 VEX_4V;
744 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
745 (ins VR128:$src1, VR128:$src2),
746 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
747 [(set VR128:$dst,
748 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
749 VEX_4V;
750 }
751 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
752 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
753 (ins VR128:$src1, VR128:$src2),
754 "movlhps\t{$src2, $dst|$dst, $src2}",
755 [(set VR128:$dst,
756 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
757 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
758 (ins VR128:$src1, VR128:$src2),
759 "movhlps\t{$src2, $dst|$dst, $src2}",
760 [(set VR128:$dst,
761 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
762 }
764 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
765 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
766 let AddedComplexity = 20 in {
767 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
768 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
769 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
770 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
771 }
773 //===----------------------------------------------------------------------===//
774 // SSE 1 & 2 - Conversion Instructions
775 //===----------------------------------------------------------------------===//
777 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
778 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
779 string asm> {
780 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
781 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
782 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
783 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
784 }
786 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
787 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
788 string asm, Domain d> {
789 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
790 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
791 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
792 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
793 }
795 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
796 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
797 string asm> {
798 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
799 asm, []>;
800 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
801 (ins DstRC:$src1, x86memop:$src), asm, []>;
802 }
804 let isAsmParserOnly = 1 in {
805 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
806 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
807 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
808 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
809 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
810 "cvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}">, XS,
811 VEX_4V;
812 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
813 "cvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}">, XD,
814 VEX_4V;
815 }
817 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
818 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
819 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
820 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
821 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
822 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
823 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
824 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
826 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
827 // and/or XMM operand(s).
828 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
829 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
830 string asm, Domain d> {
831 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
832 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
833 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
834 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
835 }
837 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
838 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
839 string asm> {
840 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
841 [(set DstRC:$dst, (Int SrcRC:$src))]>;
842 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
843 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
844 }
846 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
847 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
848 PatFrag ld_frag, string asm, Domain d> {
849 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
850 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
851 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
852 (ins DstRC:$src1, x86memop:$src2), asm,
853 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
854 }
856 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
857 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
858 PatFrag ld_frag, string asm> {
859 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
860 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
861 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
862 (ins DstRC:$src1, x86memop:$src2), asm,
863 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
864 }
866 let isAsmParserOnly = 1 in {
867 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
868 f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS,
869 VEX;
870 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
871 f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD,
872 VEX;
873 }
874 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
875 f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS;
876 defm Int_CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
877 f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD;
880 let Constraints = "$src1 = $dst" in {
881 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
882 int_x86_sse_cvtsi2ss, i32mem, loadi32,
883 "cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XS;
884 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
885 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
886 "cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XD;
887 }
889 // Instructions below don't have an AVX form.
890 defm Int_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
891 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
892 SSEPackedSingle>, TB;
893 defm Int_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
894 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
895 SSEPackedDouble>, TB, OpSize;
896 defm Int_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
897 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
898 SSEPackedSingle>, TB;
899 defm Int_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
900 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
901 SSEPackedDouble>, TB, OpSize;
902 defm Int_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
903 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
904 SSEPackedDouble>, TB, OpSize;
905 let Constraints = "$src1 = $dst" in {
906 defm Int_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
907 int_x86_sse_cvtpi2ps,
908 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
909 SSEPackedSingle>, TB;
910 }
912 /// SSE 1 Only
914 // Aliases for intrinsics
915 let isAsmParserOnly = 1, Pattern = []<dag> in {
916 defm Int_VCVTTSS2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
917 int_x86_sse_cvttss2si, f32mem, load,
918 "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS;
919 defm Int_VCVTTSD2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
920 int_x86_sse2_cvttsd2si, f128mem, load,
921 "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD;
922 }
923 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
924 f32mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
925 XS;
926 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
927 f128mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
928 XD;
930 let isAsmParserOnly = 1, Pattern = []<dag> in {
931 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
932 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
933 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load,
934 "cvtdq2ps\t{$src, $dst|$dst, $src}",
935 SSEPackedSingle>, TB, VEX;
936 }
937 let Pattern = []<dag> in {
938 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
939 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
940 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load /*dummy*/,
941 "cvtdq2ps\t{$src, $dst|$dst, $src}",
942 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
943 }
945 /// SSE 2 Only
947 // Convert scalar double to scalar single
948 let isAsmParserOnly = 1 in {
949 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
950 (ins FR64:$src1, FR64:$src2),
951 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
952 VEX_4V;
953 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
954 (ins FR64:$src1, f64mem:$src2),
955 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
956 []>, XD, Requires<[HasAVX, HasSSE2, OptForSize]>, VEX_4V;
957 }
958 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
959 "cvtsd2ss\t{$src, $dst|$dst, $src}",
960 [(set FR32:$dst, (fround FR64:$src))]>;
961 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
962 "cvtsd2ss\t{$src, $dst|$dst, $src}",
963 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
964 Requires<[HasSSE2, OptForSize]>;
966 let isAsmParserOnly = 1 in
967 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
968 int_x86_sse2_cvtsd2ss, f64mem, load,
969 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
970 XS, VEX_4V;
971 let Constraints = "$src1 = $dst" in
972 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
973 int_x86_sse2_cvtsd2ss, f64mem, load,
974 "cvtsd2ss\t{$src2, $dst|$dst, $src2}">, XS;
976 // Convert scalar single to scalar double
977 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
978 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
979 (ins FR32:$src1, FR32:$src2),
980 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
981 []>, XS, Requires<[HasAVX, HasSSE2]>, VEX_4V;
982 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
983 (ins FR32:$src1, f32mem:$src2),
984 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
985 []>, XS, VEX_4V, Requires<[HasAVX, HasSSE2, OptForSize]>;
986 }
987 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
988 "cvtss2sd\t{$src, $dst|$dst, $src}",
989 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
990 Requires<[HasSSE2]>;
991 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
992 "cvtss2sd\t{$src, $dst|$dst, $src}",
993 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
994 Requires<[HasSSE2, OptForSize]>;
996 let isAsmParserOnly = 1 in {
997 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
998 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
999 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1000 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1001 VR128:$src2))]>, XS, VEX_4V,
1002 Requires<[HasAVX, HasSSE2]>;
1003 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1004 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1005 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1006 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1007 (load addr:$src2)))]>, XS, VEX_4V,
1008 Requires<[HasAVX, HasSSE2]>;
1009 }
1010 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1011 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1012 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1013 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1014 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1015 VR128:$src2))]>, XS,
1016 Requires<[HasSSE2]>;
1017 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1018 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1019 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1020 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1021 (load addr:$src2)))]>, XS,
1022 Requires<[HasSSE2]>;
1023 }
1025 def : Pat<(extloadf32 addr:$src),
1026 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1027 Requires<[HasSSE2, OptForSpeed]>;
1029 // Convert doubleword to packed single/double fp
1030 let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
1031 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1032 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1033 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1034 TB, VEX, Requires<[HasAVX, HasSSE2]>;
1035 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1036 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1037 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1038 (bitconvert (memopv2i64 addr:$src))))]>,
1039 TB, VEX, Requires<[HasAVX, HasSSE2]>;
1040 }
1041 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1042 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1043 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1044 TB, Requires<[HasSSE2]>;
1045 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1046 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1047 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1048 (bitconvert (memopv2i64 addr:$src))))]>,
1049 TB, Requires<[HasSSE2]>;
1051 // FIXME: why the non-intrinsic version is described as SSE3?
1052 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
1053 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1054 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1055 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1056 XS, VEX, Requires<[HasAVX, HasSSE2]>;
1057 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1058 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1059 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1060 (bitconvert (memopv2i64 addr:$src))))]>,
1061 XS, VEX, Requires<[HasAVX, HasSSE2]>;
1062 }
1063 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1064 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1065 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1066 XS, Requires<[HasSSE2]>;
1067 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1068 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1069 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1070 (bitconvert (memopv2i64 addr:$src))))]>,
1071 XS, Requires<[HasSSE2]>;
1073 // Convert packed single/double fp to doubleword
1074 let isAsmParserOnly = 1 in {
1075 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1076 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1077 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1078 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1079 }
1080 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1081 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1082 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1083 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1085 let isAsmParserOnly = 1 in {
1086 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1087 "cvtps2dq\t{$src, $dst|$dst, $src}",
1088 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1089 VEX;
1090 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1091 (ins f128mem:$src),
1092 "cvtps2dq\t{$src, $dst|$dst, $src}",
1093 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1094 (memop addr:$src)))]>, VEX;
1095 }
1096 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1097 "cvtps2dq\t{$src, $dst|$dst, $src}",
1098 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1099 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1100 "cvtps2dq\t{$src, $dst|$dst, $src}",
1101 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1102 (memop addr:$src)))]>;
1104 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XD prefix
1105 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1106 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1107 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1108 XD, VEX, Requires<[HasAVX, HasSSE2]>;
1109 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1110 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1111 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1112 (memop addr:$src)))]>,
1113 XD, VEX, Requires<[HasAVX, HasSSE2]>;
1114 }
1115 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1116 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1117 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1118 XD, Requires<[HasSSE2]>;
1119 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1120 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1121 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1122 (memop addr:$src)))]>,
1123 XD, Requires<[HasSSE2]>;
1126 // Convert with truncation packed single/double fp to doubleword
1127 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XS prefix
1128 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1129 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1130 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1131 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1132 }
1133 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1134 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1135 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1136 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1139 let isAsmParserOnly = 1 in {
1140 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1141 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1142 [(set VR128:$dst,
1143 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1144 XS, VEX, Requires<[HasAVX, HasSSE2]>;
1145 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1146 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1147 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1148 (memop addr:$src)))]>,
1149 XS, VEX, Requires<[HasAVX, HasSSE2]>;
1150 }
1151 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1152 "cvttps2dq\t{$src, $dst|$dst, $src}",
1153 [(set VR128:$dst,
1154 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1155 XS, Requires<[HasSSE2]>;
1156 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1157 "cvttps2dq\t{$src, $dst|$dst, $src}",
1158 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1159 (memop addr:$src)))]>,
1160 XS, Requires<[HasSSE2]>;
1162 let isAsmParserOnly = 1 in {
1163 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
1164 (ins VR128:$src),
1165 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1166 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
1167 VEX;
1168 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
1169 (ins f128mem:$src),
1170 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1171 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1172 (memop addr:$src)))]>, VEX;
1173 }
1174 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1175 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1176 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1177 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1178 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1179 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1180 (memop addr:$src)))]>;
1182 // Convert packed single to packed double
1183 let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
1184 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1185 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX,
1186 Requires<[HasAVX]>;
1187 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1188 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX,
1189 Requires<[HasAVX]>;
1190 }
1191 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1192 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1193 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1194 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1196 let isAsmParserOnly = 1 in {
1197 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1198 "cvtps2pd\t{$src, $dst|$dst, $src}",
1199 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1200 VEX, Requires<[HasAVX, HasSSE2]>;
1201 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1202 "cvtps2pd\t{$src, $dst|$dst, $src}",
1203 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1204 (load addr:$src)))]>,
1205 VEX, Requires<[HasAVX, HasSSE2]>;
1206 }
1207 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1208 "cvtps2pd\t{$src, $dst|$dst, $src}",
1209 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1210 TB, Requires<[HasSSE2]>;
1211 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1212 "cvtps2pd\t{$src, $dst|$dst, $src}",
1213 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1214 (load addr:$src)))]>,
1215 TB, Requires<[HasSSE2]>;
1217 // Convert packed double to packed single
1218 let isAsmParserOnly = 1 in {
1219 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1220 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1221 // FIXME: the memory form of this instruction should described using
1222 // use extra asm syntax
1223 }
1224 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1225 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1226 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1227 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1230 let isAsmParserOnly = 1 in {
1231 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1232 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1233 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1234 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1235 (ins f128mem:$src),
1236 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1237 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1238 (memop addr:$src)))]>;
1239 }
1240 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1241 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1242 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1243 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1244 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1245 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1246 (memop addr:$src)))]>;
1248 //===----------------------------------------------------------------------===//
1249 // SSE 1 & 2 - Compare Instructions
1250 //===----------------------------------------------------------------------===//
1252 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1253 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1254 string asm, string asm_alt> {
1255 def rr : SIi8<0xC2, MRMSrcReg,
1256 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1257 asm, []>;
1258 let mayLoad = 1 in
1259 def rm : SIi8<0xC2, MRMSrcMem,
1260 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1261 asm, []>;
1262 // Accept explicit immediate argument form instead of comparison code.
1263 let isAsmParserOnly = 1 in {
1264 def rr_alt : SIi8<0xC2, MRMSrcReg,
1265 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1266 asm_alt, []>;
1267 let mayLoad = 1 in
1268 def rm_alt : SIi8<0xC2, MRMSrcMem,
1269 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1270 asm_alt, []>;
1271 }
1272 }
1274 let neverHasSideEffects = 1, isAsmParserOnly = 1 in {
1275 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1276 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1277 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1278 XS, VEX_4V;
1279 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1280 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1281 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1282 XD, VEX_4V;
1283 }
1285 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1286 defm CMPSS : sse12_cmp_scalar<FR32, f32mem,
1287 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
1288 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
1289 defm CMPSD : sse12_cmp_scalar<FR64, f64mem,
1290 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1291 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
1292 }
1294 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1295 Intrinsic Int, string asm> {
1296 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1297 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1298 [(set VR128:$dst, (Int VR128:$src1,
1299 VR128:$src, imm:$cc))]>;
1300 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1301 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1302 [(set VR128:$dst, (Int VR128:$src1,
1303 (load addr:$src), imm:$cc))]>;
1304 }
1306 // Aliases to match intrinsics which expect XMM operand(s).
1307 let isAsmParserOnly = 1 in {
1308 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1309 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1310 XS, VEX_4V;
1311 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1312 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1313 XD, VEX_4V;
1314 }
1315 let Constraints = "$src1 = $dst" in {
1316 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1317 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1318 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1319 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1320 }
1323 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1324 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1325 ValueType vt, X86MemOperand x86memop,
1326 PatFrag ld_frag, string OpcodeStr, Domain d> {
1327 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1328 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1329 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1330 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1331 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1332 [(set EFLAGS, (OpNode (vt RC:$src1),
1333 (ld_frag addr:$src2)))], d>;
1334 }
1336 let Defs = [EFLAGS] in {
1337 let isAsmParserOnly = 1 in {
1338 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1339 "ucomiss", SSEPackedSingle>, VEX;
1340 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1341 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1342 let Pattern = []<dag> in {
1343 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1344 "comiss", SSEPackedSingle>, VEX;
1345 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1346 "comisd", SSEPackedDouble>, OpSize, VEX;
1347 }
1349 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1350 load, "ucomiss", SSEPackedSingle>, VEX;
1351 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1352 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1354 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1355 load, "comiss", SSEPackedSingle>, VEX;
1356 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1357 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1358 }
1359 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1360 "ucomiss", SSEPackedSingle>, TB;
1361 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1362 "ucomisd", SSEPackedDouble>, TB, OpSize;
1364 let Pattern = []<dag> in {
1365 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1366 "comiss", SSEPackedSingle>, TB;
1367 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1368 "comisd", SSEPackedDouble>, TB, OpSize;
1369 }
1371 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1372 load, "ucomiss", SSEPackedSingle>, TB;
1373 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1374 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1376 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1377 "comiss", SSEPackedSingle>, TB;
1378 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1379 "comisd", SSEPackedDouble>, TB, OpSize;
1380 } // Defs = [EFLAGS]
1382 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1383 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1384 Intrinsic Int, string asm, string asm_alt,
1385 Domain d> {
1386 def rri : PIi8<0xC2, MRMSrcReg,
1387 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1388 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1389 def rmi : PIi8<0xC2, MRMSrcMem,
1390 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1391 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1392 // Accept explicit immediate argument form instead of comparison code.
1393 let isAsmParserOnly = 1 in {
1394 def rri_alt : PIi8<0xC2, MRMSrcReg,
1395 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1396 asm_alt, [], d>;
1397 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1398 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1399 asm_alt, [], d>;
1400 }
1401 }
1403 let isAsmParserOnly = 1 in {
1404 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1405 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1406 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1407 SSEPackedSingle>, VEX_4V;
1408 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1409 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1410 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1411 SSEPackedDouble>, OpSize, VEX_4V;
1412 }
1413 let Constraints = "$src1 = $dst" in {
1414 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1415 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1416 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1417 SSEPackedSingle>, TB;
1418 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1419 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1420 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1421 SSEPackedDouble>, TB, OpSize;
1422 }
1424 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1425 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1426 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1427 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1428 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1429 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1430 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1431 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1433 //===----------------------------------------------------------------------===//
1434 // SSE 1 & 2 - Shuffle Instructions
1435 //===----------------------------------------------------------------------===//
1437 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1438 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1439 ValueType vt, string asm, PatFrag mem_frag,
1440 Domain d, bit IsConvertibleToThreeAddress = 0> {
1441 def rmi : PIi8<0xC6, MRMSrcMem, (outs VR128:$dst),
1442 (ins VR128:$src1, f128mem:$src2, i8imm:$src3), asm,
1443 [(set VR128:$dst, (vt (shufp:$src3
1444 VR128:$src1, (mem_frag addr:$src2))))], d>;
1445 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1446 def rri : PIi8<0xC6, MRMSrcReg, (outs VR128:$dst),
1447 (ins VR128:$src1, VR128:$src2, i8imm:$src3), asm,
1448 [(set VR128:$dst,
1449 (vt (shufp:$src3 VR128:$src1, VR128:$src2)))], d>;
1450 }
1452 let isAsmParserOnly = 1 in {
1453 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1454 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1455 memopv4f32, SSEPackedSingle>, VEX_4V;
1456 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1457 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1458 memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
1459 }
1461 let Constraints = "$src1 = $dst" in {
1462 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1463 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1464 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1465 TB;
1466 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1467 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1468 memopv2f64, SSEPackedDouble>, TB, OpSize;
1469 }
1471 //===----------------------------------------------------------------------===//
1472 // SSE 1 & 2 - Unpack Instructions
1473 //===----------------------------------------------------------------------===//
1475 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1476 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1477 PatFrag mem_frag, RegisterClass RC,
1478 X86MemOperand x86memop, string asm,
1479 Domain d> {
1480 def rr : PI<opc, MRMSrcReg,
1481 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1482 asm, [(set RC:$dst,
1483 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1484 def rm : PI<opc, MRMSrcMem,
1485 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1486 asm, [(set RC:$dst,
1487 (vt (OpNode RC:$src1,
1488 (mem_frag addr:$src2))))], d>;
1489 }
1491 let AddedComplexity = 10 in {
1492 let isAsmParserOnly = 1 in {
1493 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1494 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1495 SSEPackedSingle>, VEX_4V;
1496 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1497 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1498 SSEPackedDouble>, OpSize, VEX_4V;
1499 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1500 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1501 SSEPackedSingle>, VEX_4V;
1502 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1503 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1504 SSEPackedDouble>, OpSize, VEX_4V;
1505 }
1507 let Constraints = "$src1 = $dst" in {
1508 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1509 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1510 SSEPackedSingle>, TB;
1511 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1512 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1513 SSEPackedDouble>, TB, OpSize;
1514 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1515 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1516 SSEPackedSingle>, TB;
1517 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1518 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1519 SSEPackedDouble>, TB, OpSize;
1520 } // Constraints = "$src1 = $dst"
1521 } // AddedComplexity
1523 //===----------------------------------------------------------------------===//
1524 // SSE 1 & 2 - Extract Floating-Point Sign mask
1525 //===----------------------------------------------------------------------===//
1527 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1528 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1529 Domain d> {
1530 def rr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1531 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1532 [(set GR32:$dst, (Int RC:$src))], d>;
1533 }
1535 // Mask creation
1536 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1537 SSEPackedSingle>, TB;
1538 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1539 SSEPackedDouble>, TB, OpSize;
1541 let isAsmParserOnly = 1 in {
1542 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1543 "movmskps", SSEPackedSingle>, VEX;
1544 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1545 "movmskpd", SSEPackedDouble>, OpSize,
1546 VEX;
1547 }
1549 //===----------------------------------------------------------------------===//
1550 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1551 //===----------------------------------------------------------------------===//
1553 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1554 // names that start with 'Fs'.
1556 // Alias instructions that map fld0 to pxor for sse.
1557 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1558 canFoldAsLoad = 1 in {
1559 // FIXME: Set encoding to pseudo!
1560 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1561 [(set FR32:$dst, fp32imm0)]>,
1562 Requires<[HasSSE1]>, TB, OpSize;
1563 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1564 [(set FR64:$dst, fpimm0)]>,
1565 Requires<[HasSSE2]>, TB, OpSize;
1566 }
1568 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1569 // bits are disregarded.
1570 let neverHasSideEffects = 1 in {
1571 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1572 "movaps\t{$src, $dst|$dst, $src}", []>;
1573 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1574 "movapd\t{$src, $dst|$dst, $src}", []>;
1575 }
1577 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1578 // bits are disregarded.
1579 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1580 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1581 "movaps\t{$src, $dst|$dst, $src}",
1582 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1583 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1584 "movapd\t{$src, $dst|$dst, $src}",
1585 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1586 }
1588 //===----------------------------------------------------------------------===//
1589 // SSE 1 & 2 - Logical Instructions
1590 //===----------------------------------------------------------------------===//
1592 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1593 ///
1594 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1595 SDNode OpNode, bit MayLoad = 0> {
1596 let isAsmParserOnly = 1 in {
1597 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1598 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR32,
1599 f32, f128mem, memopfsf32, SSEPackedSingle, MayLoad>, VEX_4V;
1601 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1602 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR64,
1603 f64, f128mem, memopfsf64, SSEPackedDouble, MayLoad>, OpSize,
1604 VEX_4V;
1605 }
1607 let Constraints = "$src1 = $dst" in {
1608 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1609 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, FR32, f32,
1610 f128mem, memopfsf32, SSEPackedSingle, MayLoad>, TB;
1612 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1613 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, FR64, f64,
1614 f128mem, memopfsf64, SSEPackedDouble, MayLoad>, TB, OpSize;
1615 }
1616 }
1618 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1619 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1620 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1621 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1623 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1624 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1>;
1626 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1627 ///
1628 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1629 SDNode OpNode, int HasPat = 0,
1630 list<list<dag>> Pattern = []> {
1631 let isAsmParserOnly = 1 in {
1632 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1633 !strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1634 f128mem,
1635 !if(HasPat, Pattern[0], // rr
1636 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1637 VR128:$src2)))]),
1638 !if(HasPat, Pattern[2], // rm
1639 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1640 (memopv2i64 addr:$src2)))])>,
1641 VEX_4V;
1643 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1644 !strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1645 f128mem,
1646 !if(HasPat, Pattern[1], // rr
1647 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1648 (bc_v2i64 (v2f64
1649 VR128:$src2))))]),
1650 !if(HasPat, Pattern[3], // rm
1651 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1652 (memopv2i64 addr:$src2)))])>,
1653 OpSize, VEX_4V;
1654 }
1655 let Constraints = "$src1 = $dst" in {
1656 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1657 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), f128mem,
1658 !if(HasPat, Pattern[0], // rr
1659 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1660 VR128:$src2)))]),
1661 !if(HasPat, Pattern[2], // rm
1662 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1663 (memopv2i64 addr:$src2)))])>, TB;
1665 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1666 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), f128mem,
1667 !if(HasPat, Pattern[1], // rr
1668 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1669 (bc_v2i64 (v2f64
1670 VR128:$src2))))]),
1671 !if(HasPat, Pattern[3], // rm
1672 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1673 (memopv2i64 addr:$src2)))])>,
1674 TB, OpSize;
1675 }
1676 }
1678 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1679 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1680 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1681 let isCommutable = 0 in
1682 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1683 // single r+r
1684 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1685 (bc_v2i64 (v4i32 immAllOnesV))),
1686 VR128:$src2)))],
1687 // double r+r
1688 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1689 (bc_v2i64 (v2f64 VR128:$src2))))],
1690 // single r+m
1691 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1692 (bc_v2i64 (v4i32 immAllOnesV))),
1693 (memopv2i64 addr:$src2))))],
1694 // double r+m
1695 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1696 (memopv2i64 addr:$src2)))]]>;
1698 //===----------------------------------------------------------------------===//
1699 // SSE 1 & 2 - Arithmetic Instructions
1700 //===----------------------------------------------------------------------===//
1702 /// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
1703 /// vector forms.
1704 ///
1705 /// In addition, we also have a special variant of the scalar form here to
1706 /// represent the associated intrinsic operation. This form is unlike the
1707 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1708 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1709 ///
1710 /// These three forms can each be reg+reg or reg+mem.
1711 ///
1712 multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
1713 SDNode OpNode> {
1715 let isAsmParserOnly = 1 in {
1716 defm V#NAME#SS : sse12_fp_scalar<opc,
1717 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1718 OpNode, FR32, f32mem>, XS, VEX_4V;
1720 defm V#NAME#SD : sse12_fp_scalar<opc,
1721 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1722 OpNode, FR64, f64mem>, XD, VEX_4V;
1724 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1725 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1726 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
1727 VEX_4V;
1729 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1730 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1731 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
1732 OpSize, VEX_4V;
1734 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1735 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1736 "", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
1738 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1739 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1740 "2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
1741 }
1743 let Constraints = "$src1 = $dst" in {
1744 defm SS : sse12_fp_scalar<opc,
1745 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1746 OpNode, FR32, f32mem>, XS;
1748 defm SD : sse12_fp_scalar<opc,
1749 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1750 OpNode, FR64, f64mem>, XD;
1752 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1753 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
1754 f128mem, memopv4f32, SSEPackedSingle>, TB;
1756 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1757 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
1758 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
1760 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1761 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1762 "", "_ss", ssmem, sse_load_f32>, XS;
1764 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1765 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1766 "2", "_sd", sdmem, sse_load_f64>, XD;
1767 }
1768 }
1770 // Arithmetic instructions
1771 defm ADD : basic_sse12_fp_binop_rm<0x58, "add", fadd>;
1772 defm MUL : basic_sse12_fp_binop_rm<0x59, "mul", fmul>;
1774 let isCommutable = 0 in {
1775 defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>;
1776 defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>;
1777 }
1779 /// sse12_fp_binop_rm - Other SSE 1 & 2 binops
1780 ///
1781 /// This multiclass is like basic_sse12_fp_binop_rm, with the addition of
1782 /// instructions for a full-vector intrinsic form. Operations that map
1783 /// onto C operators don't use this form since they just use the plain
1784 /// vector form instead of having a separate vector intrinsic form.
1785 ///
1786 multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
1787 SDNode OpNode> {
1789 let isAsmParserOnly = 1 in {
1790 // Scalar operation, reg+reg.
1791 defm V#NAME#SS : sse12_fp_scalar<opc,
1792 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1793 OpNode, FR32, f32mem>, XS, VEX_4V;
1795 defm V#NAME#SD : sse12_fp_scalar<opc,
1796 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1797 OpNode, FR64, f64mem>, XD, VEX_4V;
1799 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1800 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1801 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
1802 VEX_4V;
1804 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1805 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1806 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
1807 OpSize, VEX_4V;
1809 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1810 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1811 "", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
1813 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1814 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1815 "2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
1817 defm V#NAME#PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1818 !strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1819 "", "_ps", f128mem, memopv4f32, SSEPackedSingle>, VEX_4V;
1821 defm V#NAME#PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1822 !strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1823 "2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, OpSize,
1824 VEX_4V;
1825 }
1827 let Constraints = "$src1 = $dst" in {
1828 // Scalar operation, reg+reg.
1829 defm SS : sse12_fp_scalar<opc,
1830 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1831 OpNode, FR32, f32mem>, XS;
1832 defm SD : sse12_fp_scalar<opc,
1833 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1834 OpNode, FR64, f64mem>, XD;
1835 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1836 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
1837 f128mem, memopv4f32, SSEPackedSingle>, TB;
1839 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1840 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
1841 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
1843 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1844 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1845 "", "_ss", ssmem, sse_load_f32>, XS;
1847 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1848 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1849 "2", "_sd", sdmem, sse_load_f64>, XD;
1851 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1852 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
1853 "", "_ps", f128mem, memopv4f32, SSEPackedSingle>, TB;
1855 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1856 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1857 "2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
1858 }
1859 }
1861 let isCommutable = 0 in {
1862 defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>;
1863 defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
1864 }
1866 /// Unop Arithmetic
1867 /// In addition, we also have a special variant of the scalar form here to
1868 /// represent the associated intrinsic operation. This form is unlike the
1869 /// plain scalar form, in that it takes an entire vector (instead of a
1870 /// scalar) and leaves the top elements undefined.
1871 ///
1872 /// And, we have a special variant form for a full-vector intrinsic form.
1874 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1875 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1876 SDNode OpNode, Intrinsic F32Int> {
1877 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1878 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1879 [(set FR32:$dst, (OpNode FR32:$src))]>;
1880 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1881 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1882 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1883 Requires<[HasSSE1, OptForSize]>;
1884 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1885 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1886 [(set VR128:$dst, (F32Int VR128:$src))]>;
1887 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1888 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1889 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1890 }
1892 /// sse1_fp_unop_p - SSE1 unops in scalar form.
1893 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr,
1894 SDNode OpNode, Intrinsic V4F32Int> {
1895 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1896 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1897 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1898 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1899 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1900 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1901 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1902 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1903 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1904 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1905 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1906 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1907 }
1909 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1910 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1911 SDNode OpNode, Intrinsic F32Int> {
1912 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1913 !strconcat(!strconcat("v", OpcodeStr),
1914 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1915 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1916 !strconcat(!strconcat("v", OpcodeStr),
1917 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1918 []>, XS, Requires<[HasAVX, HasSSE1, OptForSize]>;
1919 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
1920 (ins VR128:$src1, VR128:$src2),
1921 !strconcat(!strconcat("v", OpcodeStr),
1922 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1923 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
1924 (ins VR128:$src1, ssmem:$src2),
1925 !strconcat(!strconcat("v", OpcodeStr),
1926 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1927 }
1929 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1930 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1931 SDNode OpNode, Intrinsic F64Int> {
1932 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1933 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1934 [(set FR64:$dst, (OpNode FR64:$src))]>;
1935 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1936 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1937 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1938 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1939 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1940 [(set VR128:$dst, (F64Int VR128:$src))]>;
1941 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1942 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1943 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1944 }
1946 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1947 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1948 SDNode OpNode, Intrinsic V2F64Int> {
1949 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1950 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1951 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1952 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1953 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1954 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1955 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1956 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1957 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1958 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1959 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1960 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1961 }
1963 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1964 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1965 SDNode OpNode, Intrinsic F64Int> {
1966 def SDr : VSDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1967 !strconcat(OpcodeStr,
1968 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1969 def SDm : VSDI<opc, MRMSrcMem, (outs FR64:$dst),
1970 (ins FR64:$src1, f64mem:$src2),
1971 !strconcat(OpcodeStr,
1972 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1973 def SDr_Int : VSDI<opc, MRMSrcReg, (outs VR128:$dst),
1974 (ins VR128:$src1, VR128:$src2),
1975 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1976 []>;
1977 def SDm_Int : VSDI<opc, MRMSrcMem, (outs VR128:$dst),
1978 (ins VR128:$src1, sdmem:$src2),
1979 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1980 []>;
1981 }
1983 let isAsmParserOnly = 1 in {
1984 // Square root.
1985 let Predicates = [HasAVX, HasSSE2] in {
1986 defm VSQRT : sse2_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1987 VEX_4V;
1989 defm VSQRT : sse2_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_pd>, VEX;
1990 }
1992 let Predicates = [HasAVX, HasSSE1] in {
1993 defm VSQRT : sse1_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1994 VEX_4V;
1995 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ps>, VEX;
1996 // Reciprocal approximations. Note that these typically require refinement
1997 // in order to obtain suitable precision.
1998 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "rsqrt", X86frsqrt,
1999 int_x86_sse_rsqrt_ss>, VEX_4V;
2000 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, int_x86_sse_rsqrt_ps>,
2001 VEX;
2002 defm VRCP : sse1_fp_unop_s_avx<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2003 VEX_4V;
2004 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ps>,
2005 VEX;
2006 }
2007 }
2009 // Square root.
2010 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
2011 sse1_fp_unop_p<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ps>,
2012 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
2013 sse2_fp_unop_p<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_pd>;
2015 // Reciprocal approximations. Note that these typically require refinement
2016 // in order to obtain suitable precision.
2017 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
2018 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ps>;
2019 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2020 sse1_fp_unop_p<0x53, "rcp", X86frcp, int_x86_sse_rcp_ps>;
2022 // There is no f64 version of the reciprocal approximation instructions.
2024 //===----------------------------------------------------------------------===//
2025 // SSE 1 & 2 - Non-temporal stores
2026 //===----------------------------------------------------------------------===//
2028 let isAsmParserOnly = 1 in {
2029 def VMOVNTPSmr_Int : VPSI<0x2B, MRMDestMem, (outs),
2030 (ins i128mem:$dst, VR128:$src),
2031 "movntps\t{$src, $dst|$dst, $src}",
2032 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>, VEX;
2033 def VMOVNTPDmr_Int : VPDI<0x2B, MRMDestMem, (outs),
2034 (ins i128mem:$dst, VR128:$src),
2035 "movntpd\t{$src, $dst|$dst, $src}",
2036 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>, VEX;
2038 let ExeDomain = SSEPackedInt in
2039 def VMOVNTDQmr_Int : VPDI<0xE7, MRMDestMem, (outs),
2040 (ins f128mem:$dst, VR128:$src),
2041 "movntdq\t{$src, $dst|$dst, $src}",
2042 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>, VEX;
2044 let AddedComplexity = 400 in { // Prefer non-temporal versions
2045 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2046 (ins f128mem:$dst, VR128:$src),
2047 "movntps\t{$src, $dst|$dst, $src}",
2048 [(alignednontemporalstore (v4f32 VR128:$src),
2049 addr:$dst)]>, VEX;
2050 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2051 (ins f128mem:$dst, VR128:$src),
2052 "movntpd\t{$src, $dst|$dst, $src}",
2053 [(alignednontemporalstore (v2f64 VR128:$src),
2054 addr:$dst)]>, VEX;
2055 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2056 (ins f128mem:$dst, VR128:$src),
2057 "movntdq\t{$src, $dst|$dst, $src}",
2058 [(alignednontemporalstore (v2f64 VR128:$src),
2059 addr:$dst)]>, VEX;
2060 let ExeDomain = SSEPackedInt in
2061 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2062 (ins f128mem:$dst, VR128:$src),
2063 "movntdq\t{$src, $dst|$dst, $src}",
2064 [(alignednontemporalstore (v4f32 VR128:$src),
2065 addr:$dst)]>, VEX;
2066 }
2067 }
2069 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2070 "movntps\t{$src, $dst|$dst, $src}",
2071 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
2072 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2073 "movntpd\t{$src, $dst|$dst, $src}",
2074 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2076 let ExeDomain = SSEPackedInt in
2077 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2078 "movntdq\t{$src, $dst|$dst, $src}",
2079 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2081 let AddedComplexity = 400 in { // Prefer non-temporal versions
2082 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2083 "movntps\t{$src, $dst|$dst, $src}",
2084 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2085 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2086 "movntpd\t{$src, $dst|$dst, $src}",
2087 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2089 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2090 "movntdq\t{$src, $dst|$dst, $src}",
2091 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2093 let ExeDomain = SSEPackedInt in
2094 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2095 "movntdq\t{$src, $dst|$dst, $src}",
2096 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2098 // There is no AVX form for instructions below this point
2099 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2100 "movnti\t{$src, $dst|$dst, $src}",
2101 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2102 TB, Requires<[HasSSE2]>;
2104 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2105 "movnti\t{$src, $dst|$dst, $src}",
2106 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2107 TB, Requires<[HasSSE2]>;
2109 }
2110 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2111 "movnti\t{$src, $dst|$dst, $src}",
2112 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2113 TB, Requires<[HasSSE2]>;
2115 //===----------------------------------------------------------------------===//
2116 // SSE 1 & 2 - Misc Instructions (No AVX form)
2117 //===----------------------------------------------------------------------===//
2119 // Prefetch intrinsic.
2120 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2121 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
2122 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2123 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
2124 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2125 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
2126 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2127 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
2129 // Load, store, and memory fence
2130 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2131 TB, Requires<[HasSSE1]>;
2133 // Alias instructions that map zero vector to pxor / xorp* for sse.
2134 // We set canFoldAsLoad because this can be converted to a constant-pool
2135 // load of an all-zeros value if folding it would be beneficial.
2136 // FIXME: Change encoding to pseudo!
2137 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2138 isCodeGenOnly = 1 in {
2139 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2140 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2141 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2142 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2143 let ExeDomain = SSEPackedInt in
2144 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2145 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2146 }
2148 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2149 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2150 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2152 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2153 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2155 //===----------------------------------------------------------------------===//
2156 // SSE 1 & 2 - Load/Store XCSR register
2157 //===----------------------------------------------------------------------===//
2159 let isAsmParserOnly = 1 in {
2160 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2161 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2162 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2163 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2164 }
2166 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2167 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2168 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2169 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2171 //===---------------------------------------------------------------------===//
2172 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2173 //===---------------------------------------------------------------------===//
2174 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2176 let isAsmParserOnly = 1 in {
2177 let neverHasSideEffects = 1 in
2178 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2179 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2180 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2181 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2183 let canFoldAsLoad = 1, mayLoad = 1 in {
2184 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2185 "movdqa\t{$src, $dst|$dst, $src}",
2186 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>,
2187 VEX;
2188 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2189 "vmovdqu\t{$src, $dst|$dst, $src}",
2190 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2191 XS, VEX, Requires<[HasAVX, HasSSE2]>;
2192 }
2194 let mayStore = 1 in {
2195 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2196 (ins i128mem:$dst, VR128:$src),
2197 "movdqa\t{$src, $dst|$dst, $src}",
2198 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>, VEX;
2199 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2200 "vmovdqu\t{$src, $dst|$dst, $src}",
2201 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2202 XS, VEX, Requires<[HasAVX, HasSSE2]>;
2203 }
2204 }
2206 let neverHasSideEffects = 1 in
2207 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2208 "movdqa\t{$src, $dst|$dst, $src}", []>;
2210 let canFoldAsLoad = 1, mayLoad = 1 in {
2211 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2212 "movdqa\t{$src, $dst|$dst, $src}",
2213 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2214 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2215 "movdqu\t{$src, $dst|$dst, $src}",
2216 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2217 XS, Requires<[HasSSE2]>;
2218 }
2220 let mayStore = 1 in {
2221 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2222 "movdqa\t{$src, $dst|$dst, $src}",
2223 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2224 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2225 "movdqu\t{$src, $dst|$dst, $src}",
2226 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2227 XS, Requires<[HasSSE2]>;
2228 }
2230 // Intrinsic forms of MOVDQU load and store
2231 let isAsmParserOnly = 1 in {
2232 let canFoldAsLoad = 1 in
2233 def VMOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2234 "vmovdqu\t{$src, $dst|$dst, $src}",
2235 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2236 XS, VEX, Requires<[HasAVX, HasSSE2]>;
2237 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2238 "vmovdqu\t{$src, $dst|$dst, $src}",
2239 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2240 XS, VEX, Requires<[HasAVX, HasSSE2]>;
2241 }
2243 let canFoldAsLoad = 1 in
2244 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2245 "movdqu\t{$src, $dst|$dst, $src}",
2246 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2247 XS, Requires<[HasSSE2]>;
2248 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2249 "movdqu\t{$src, $dst|$dst, $src}",
2250 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2251 XS, Requires<[HasSSE2]>;
2253 } // ExeDomain = SSEPackedInt
2255 //===---------------------------------------------------------------------===//
2256 // SSE2 - Packed Integer Arithmetic Instructions
2257 //===---------------------------------------------------------------------===//
2259 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2261 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2262 bit Is2Addr = 1> {
2263 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2264 (ins VR128:$src1, VR128:$src2),
2265 !if(Is2Addr,
2266 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2267 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2268 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2269 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2270 (ins VR128:$src1, i128mem:$src2),
2271 !if(Is2Addr,
2272 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2273 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2274 [(set VR128:$dst, (IntId VR128:$src1,
2275 (bitconvert (memopv2i64 addr:$src2))))]>;
2276 }
2278 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2279 string OpcodeStr, Intrinsic IntId,
2280 Intrinsic IntId2, bit Is2Addr = 1> {
2281 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2282 (ins VR128:$src1, VR128:$src2),
2283 !if(Is2Addr,
2284 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2285 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2286 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2287 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2288 (ins VR128:$src1, i128mem:$src2),
2289 !if(Is2Addr,
2290 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2291 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2292 [(set VR128:$dst, (IntId VR128:$src1,
2293 (bitconvert (memopv2i64 addr:$src2))))]>;
2294 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2295 (ins VR128:$src1, i32i8imm:$src2),
2296 !if(Is2Addr,
2297 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2298 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2299 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2300 }
2302 /// PDI_binop_rm - Simple SSE2 binary operator.
2303 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2304 ValueType OpVT, bit Is2Addr = 1> {
2305 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2306 (ins VR128:$src1, VR128:$src2),
2307 !if(Is2Addr,
2308 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2309 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2310 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2311 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2312 (ins VR128:$src1, i128mem:$src2),
2313 !if(Is2Addr,
2314 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2315 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2316 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2317 (bitconvert (memopv2i64 addr:$src2)))))]>;
2318 }
2320 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2321 ///
2322 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2323 /// to collapse (bitconvert VT to VT) into its operand.
2324 ///
2325 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2326 bit Is2Addr = 1> {
2327 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2328 (ins VR128:$src1, VR128:$src2),
2329 !if(Is2Addr,
2330 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2331 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2332 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2333 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2334 (ins VR128:$src1, i128mem:$src2),
2335 !if(Is2Addr,
2336 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2337 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2338 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2339 }
2341 } // ExeDomain = SSEPackedInt
2343 // 128-bit Integer Arithmetic
2345 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
2346 let isCommutable = 1 in {
2347 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 0 /* 3 addr */>, VEX_4V;
2348 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 0>, VEX_4V;
2349 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 0>, VEX_4V;
2350 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 0>, VEX_4V;
2351 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 0>, VEX_4V;
2352 }
2353 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0>, VEX_4V;
2354 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0>, VEX_4V;
2355 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0>, VEX_4V;
2356 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0>, VEX_4V;
2358 // Intrinsic forms
2359 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0>,
2360 VEX_4V;
2361 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0>,
2362 VEX_4V;
2363 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0>,
2364 VEX_4V;
2365 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0>,
2366 VEX_4V;
2367 let isCommutable = 1 in {
2368 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 0>,
2369 VEX_4V;
2370 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 0>,
2371 VEX_4V;
2372 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 0>,
2373 VEX_4V;
2374 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 0>,
2375 VEX_4V;
2376 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 0>,
2377 VEX_4V;
2378 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 0>,
2379 VEX_4V;
2380 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 0>,
2381 VEX_4V;
2382 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 0>,
2383 VEX_4V;
2384 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 0>,
2385 VEX_4V;
2386 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 0>,
2387 VEX_4V;
2388 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 0>,
2389 VEX_4V;
2390 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 0>,
2391 VEX_4V;
2392 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 0>,
2393 VEX_4V;
2394 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 0>,
2395 VEX_4V;
2396 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 0>,
2397 VEX_4V;
2398 }
2399 }
2401 let Constraints = "$src1 = $dst" in {
2402 let isCommutable = 1 in {
2403 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8>;
2404 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16>;
2405 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32>;
2406 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add>;
2407 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16>;
2408 }
2409 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2410 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2411 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2412 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2414 // Intrinsic forms
2415 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2416 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2417 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2418 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2419 let isCommutable = 1 in {
2420 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b>;
2421 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w>;
2422 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b>;
2423 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w>;
2424 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w>;
2425 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w>;
2426 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq>;
2427 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd>;
2428 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b>;
2429 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w>;
2430 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b>;
2431 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w>;
2432 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b>;
2433 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w>;
2434 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw>;
2435 }
2437 } // Constraints = "$src1 = $dst"
2439 //===---------------------------------------------------------------------===//
2440 // SSE2 - Packed Integer Logical Instructions
2441 //===---------------------------------------------------------------------===//
2443 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
2444 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2445 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2446 VEX_4V;
2447 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2448 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2449 VEX_4V;
2450 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2451 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2452 VEX_4V;
2454 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2455 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2456 VEX_4V;
2457 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2458 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2459 VEX_4V;
2460 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2461 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2462 VEX_4V;
2464 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2465 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2466 VEX_4V;
2467 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2468 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2469 VEX_4V;
2471 let isCommutable = 1 in {
2472 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 0>, VEX_4V;
2473 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 0>, VEX_4V;
2474 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 0>, VEX_4V;
2475 }
2477 let ExeDomain = SSEPackedInt in {
2478 let neverHasSideEffects = 1 in {
2479 // 128-bit logical shifts.
2480 def VPSLLDQri : PDIi8<0x73, MRM7r,
2481 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2482 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2483 VEX_4V;
2484 def VPSRLDQri : PDIi8<0x73, MRM3r,
2485 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2486 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2487 VEX_4V;
2488 // PSRADQri doesn't exist in SSE[1-3].
2489 }
2490 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2491 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2492 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2493 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2494 VR128:$src2)))]>, VEX_4V;
2496 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2497 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2498 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2499 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2500 (memopv2i64 addr:$src2))))]>,
2501 VEX_4V;
2502 }
2503 }
2505 let Constraints = "$src1 = $dst" in {
2506 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2507 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2508 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2509 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2510 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2511 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2513 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2514 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2515 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2516 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2517 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2518 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2520 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2521 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2522 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2523 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2525 let isCommutable = 1 in {
2526 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and>;
2527 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or>;
2528 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor>;
2529 }
2531 let ExeDomain = SSEPackedInt in {
2532 let neverHasSideEffects = 1 in {
2533 // 128-bit logical shifts.
2534 def PSLLDQri : PDIi8<0x73, MRM7r,
2535 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2536 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2537 def PSRLDQri : PDIi8<0x73, MRM3r,
2538 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2539 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2540 // PSRADQri doesn't exist in SSE[1-3].
2541 }
2542 def PANDNrr : PDI<0xDF, MRMSrcReg,
2543 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2544 "pandn\t{$src2, $dst|$dst, $src2}",
2545 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2546 VR128:$src2)))]>;
2548 def PANDNrm : PDI<0xDF, MRMSrcMem,
2549 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2550 "pandn\t{$src2, $dst|$dst, $src2}",
2551 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2552 (memopv2i64 addr:$src2))))]>;
2553 }
2554 } // Constraints = "$src1 = $dst"
2556 let Predicates = [HasSSE2] in {
2557 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2558 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2559 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2560 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2561 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2562 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2563 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2564 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2565 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2566 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2568 // Shift up / down and insert zero's.
2569 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2570 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2571 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2572 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2573 }
2575 //===---------------------------------------------------------------------===//
2576 // SSE2 - Packed Integer Comparison Instructions
2577 //===---------------------------------------------------------------------===//
2579 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
2580 let isCommutable = 1 in {
2581 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 0>,
2582 VEX_4V;
2583 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 0>,
2584 VEX_4V;
2585 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 0>,
2586 VEX_4V;
2587 }
2588 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0>,
2589 VEX_4V;
2590 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0>,
2591 VEX_4V;
2592 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0>,
2593 VEX_4V;
2594 }
2596 let Constraints = "$src1 = $dst" in {
2597 let isCommutable = 1 in {
2598 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2599 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2600 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2601 }
2602 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2603 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2604 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2605 } // Constraints = "$src1 = $dst"
2607 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2608 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2609 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2610 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2611 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2612 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2613 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2614 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2615 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2616 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2617 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2618 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2620 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2621 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2622 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2623 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2624 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2625 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2626 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2627 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2628 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2629 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2630 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2631 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2633 //===---------------------------------------------------------------------===//
2634 // SSE2 - Packed Integer Pack Instructions
2635 //===---------------------------------------------------------------------===//
2637 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
2638 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2639 0>, VEX_4V;
2640 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2641 0>, VEX_4V;
2642 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2643 0>, VEX_4V;
2644 }
2646 let Constraints = "$src1 = $dst" in {
2647 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2648 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2649 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2650 } // Constraints = "$src1 = $dst"
2652 //===---------------------------------------------------------------------===//
2653 // SSE2 - Packed Integer Shuffle Instructions
2654 //===---------------------------------------------------------------------===//
2656 let ExeDomain = SSEPackedInt in {
2657 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2658 PatFrag bc_frag> {
2659 def ri : Ii8<0x70, MRMSrcReg,
2660 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2661 !strconcat(OpcodeStr,
2662 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2663 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2664 (undef))))]>;
2665 def mi : Ii8<0x70, MRMSrcMem,
2666 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2667 !strconcat(OpcodeStr,
2668 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2669 [(set VR128:$dst, (vt (pshuf_frag:$src2
2670 (bc_frag (memopv2i64 addr:$src1)),
2671 (undef))))]>;
2672 }
2673 } // ExeDomain = SSEPackedInt
2675 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
2676 let AddedComplexity = 5 in
2677 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2678 VEX;
2680 // SSE2 with ImmT == Imm8 and XS prefix.
2681 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2682 VEX;
2684 // SSE2 with ImmT == Imm8 and XD prefix.
2685 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2686 VEX;
2687 }
2689 let Predicates = [HasSSE2] in {
2690 let AddedComplexity = 5 in
2691 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2693 // SSE2 with ImmT == Imm8 and XS prefix.
2694 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2696 // SSE2 with ImmT == Imm8 and XD prefix.
2697 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2698 }
2700 //===---------------------------------------------------------------------===//
2701 // SSE2 - Packed Integer Unpack Instructions
2702 //===---------------------------------------------------------------------===//
2704 let ExeDomain = SSEPackedInt in {
2706 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2707 PatFrag unp_frag, PatFrag bc_frag> {
2708 def rr : PDI<opc, MRMSrcReg,
2709 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2710 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2711 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2712 def rm : PDI<opc, MRMSrcMem,
2713 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2714 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2715 [(set VR128:$dst, (unp_frag VR128:$src1,
2716 (bc_frag (memopv2i64
2717 addr:$src2))))]>;
2718 }
2720 let Constraints = "$src1 = $dst" in {
2721 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2722 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2723 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2725 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2726 /// knew to collapse (bitconvert VT to VT) into its operand.
2727 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2728 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2729 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2730 [(set VR128:$dst,
2731 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2732 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2733 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2734 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2735 [(set VR128:$dst,
2736 (v2i64 (unpckl VR128:$src1,
2737 (memopv2i64 addr:$src2))))]>;
2739 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2740 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2741 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2743 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2744 /// knew to collapse (bitconvert VT to VT) into its operand.
2745 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2746 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2747 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2748 [(set VR128:$dst,
2749 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2750 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2751 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2752 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2753 [(set VR128:$dst,
2754 (v2i64 (unpckh VR128:$src1,
2755 (memopv2i64 addr:$src2))))]>;
2756 }
2758 } // ExeDomain = SSEPackedInt
2760 //===---------------------------------------------------------------------===//
2761 // SSE2 - Packed Misc Integer Instructions
2762 //===---------------------------------------------------------------------===//
2764 let ExeDomain = SSEPackedInt in {
2766 // Extract / Insert
2767 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2768 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2769 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2770 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2771 imm:$src2))]>;
2772 let Constraints = "$src1 = $dst" in {
2773 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2774 (outs VR128:$dst), (ins VR128:$src1,
2775 GR32:$src2, i32i8imm:$src3),
2776 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2777 [(set VR128:$dst,
2778 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2779 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2780 (outs VR128:$dst), (ins VR128:$src1,
2781 i16mem:$src2, i32i8imm:$src3),
2782 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2783 [(set VR128:$dst,
2784 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2785 imm:$src3))]>;
2786 }
2788 // Mask creation
2789 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2790 "pmovmskb\t{$src, $dst|$dst, $src}",
2791 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2793 // Conditional store
2794 let Uses = [EDI] in
2795 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2796 "maskmovdqu\t{$mask, $src|$src, $mask}",
2797 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2799 let Uses = [RDI] in
2800 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2801 "maskmovdqu\t{$mask, $src|$src, $mask}",
2802 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2804 } // ExeDomain = SSEPackedInt
2806 // Flush cache
2807 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2808 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2809 TB, Requires<[HasSSE2]>;
2811 // Load, store, and memory fence
2812 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2813 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2814 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2815 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2817 // Pause. This "instruction" is encoded as "rep; nop", so even though it
2818 // was introduced with SSE2, it's backward compatible.
2819 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
2821 //TODO: custom lower this so as to never even generate the noop
2822 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2823 (i8 0)), (NOOP)>;
2824 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2825 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2826 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2827 (i8 1)), (MFENCE)>;
2829 // Alias instructions that map zero vector to pxor / xorp* for sse.
2830 // We set canFoldAsLoad because this can be converted to a constant-pool
2831 // load of an all-ones value if folding it would be beneficial.
2832 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2833 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
2834 // FIXME: Change encoding to pseudo.
2835 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2836 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2838 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2839 "movd\t{$src, $dst|$dst, $src}",
2840 [(set VR128:$dst,
2841 (v4i32 (scalar_to_vector GR32:$src)))]>;
2842 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2843 "movd\t{$src, $dst|$dst, $src}",
2844 [(set VR128:$dst,
2845 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2847 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2848 "movd\t{$src, $dst|$dst, $src}",
2849 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2851 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2852 "movd\t{$src, $dst|$dst, $src}",
2853 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2855 // SSE2 instructions with XS prefix
2856 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2857 "movq\t{$src, $dst|$dst, $src}",
2858 [(set VR128:$dst,
2859 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2860 Requires<[HasSSE2]>;
2861 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2862 "movq\t{$src, $dst|$dst, $src}",
2863 [(store (i64 (vector_extract (v2i64 VR128:$src),
2864 (iPTR 0))), addr:$dst)]>;
2866 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2867 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
2869 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2870 "movd\t{$src, $dst|$dst, $src}",
2871 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2872 (iPTR 0)))]>;
2873 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2874 "movd\t{$src, $dst|$dst, $src}",
2875 [(store (i32 (vector_extract (v4i32 VR128:$src),
2876 (iPTR 0))), addr:$dst)]>;
2878 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2879 "movd\t{$src, $dst|$dst, $src}",
2880 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2881 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2882 "movd\t{$src, $dst|$dst, $src}",
2883 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2885 // Store / copy lower 64-bits of a XMM register.
2886 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2887 "movq\t{$src, $dst|$dst, $src}",
2888 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2890 // movd / movq to XMM register zero-extends
2891 let AddedComplexity = 15 in {
2892 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2893 "movd\t{$src, $dst|$dst, $src}",
2894 [(set VR128:$dst, (v4i32 (X86vzmovl
2895 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2896 // This is X86-64 only.
2897 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2898 "mov{d|q}\t{$src, $dst|$dst, $src}",
2899 [(set VR128:$dst, (v2i64 (X86vzmovl
2900 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2901 }
2903 let AddedComplexity = 20 in {
2904 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2905 "movd\t{$src, $dst|$dst, $src}",
2906 [(set VR128:$dst,
2907 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2908 (loadi32 addr:$src))))))]>;
2910 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2911 (MOVZDI2PDIrm addr:$src)>;
2912 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2913 (MOVZDI2PDIrm addr:$src)>;
2914 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2915 (MOVZDI2PDIrm addr:$src)>;
2917 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2918 "movq\t{$src, $dst|$dst, $src}",
2919 [(set VR128:$dst,
2920 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2921 (loadi64 addr:$src))))))]>, XS,
2922 Requires<[HasSSE2]>;
2924 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2925 (MOVZQI2PQIrm addr:$src)>;
2926 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2927 (MOVZQI2PQIrm addr:$src)>;
2928 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2929 }
2931 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2932 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2933 let AddedComplexity = 15 in
2934 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2935 "movq\t{$src, $dst|$dst, $src}",
2936 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2937 XS, Requires<[HasSSE2]>;
2939 let AddedComplexity = 20 in {
2940 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2941 "movq\t{$src, $dst|$dst, $src}",
2942 [(set VR128:$dst, (v2i64 (X86vzmovl
2943 (loadv2i64 addr:$src))))]>,
2944 XS, Requires<[HasSSE2]>;
2946 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2947 (MOVZPQILo2PQIrm addr:$src)>;
2948 }
2950 // Instructions for the disassembler
2951 // xr = XMM register
2952 // xm = mem64
2954 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2955 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2957 //===---------------------------------------------------------------------===//
2958 // SSE3 Instructions
2959 //===---------------------------------------------------------------------===//
2961 // Conversion Instructions
2962 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2963 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
2964 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2965 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
2966 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2967 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
2968 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2969 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
2971 // Move Instructions
2972 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2973 "movshdup\t{$src, $dst|$dst, $src}",
2974 [(set VR128:$dst, (v4f32 (movshdup
2975 VR128:$src, (undef))))]>;
2976 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2977 "movshdup\t{$src, $dst|$dst, $src}",
2978 [(set VR128:$dst, (movshdup
2979 (memopv4f32 addr:$src), (undef)))]>;
2981 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2982 "movsldup\t{$src, $dst|$dst, $src}",
2983 [(set VR128:$dst, (v4f32 (movsldup
2984 VR128:$src, (undef))))]>;
2985 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2986 "movsldup\t{$src, $dst|$dst, $src}",
2987 [(set VR128:$dst, (movsldup
2988 (memopv4f32 addr:$src), (undef)))]>;
2990 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2991 "movddup\t{$src, $dst|$dst, $src}",
2992 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2993 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2994 "movddup\t{$src, $dst|$dst, $src}",
2995 [(set VR128:$dst,
2996 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2997 (undef))))]>;
2999 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3000 (undef)),
3001 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3003 let AddedComplexity = 5 in {
3004 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3005 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3006 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3007 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3008 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3009 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3010 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3011 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3012 }
3014 // Arithmetic
3015 let Constraints = "$src1 = $dst" in {
3016 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
3017 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3018 "addsubps\t{$src2, $dst|$dst, $src2}",
3019 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
3020 VR128:$src2))]>;
3021 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
3022 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
3023 "addsubps\t{$src2, $dst|$dst, $src2}",
3024 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
3025 (memop addr:$src2)))]>;
3026 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
3027 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3028 "addsubpd\t{$src2, $dst|$dst, $src2}",
3029 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
3030 VR128:$src2))]>;
3031 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
3032 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
3033 "addsubpd\t{$src2, $dst|$dst, $src2}",
3034 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
3035 (memop addr:$src2)))]>;
3036 }
3038 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3039 "lddqu\t{$src, $dst|$dst, $src}",
3040 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3042 // Horizontal ops
3043 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
3044 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3045 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3046 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
3047 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
3048 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
3049 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3050 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
3051 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
3052 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3053 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3054 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
3055 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
3056 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
3057 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3058 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
3060 let Constraints = "$src1 = $dst" in {
3061 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
3062 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
3063 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
3064 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
3065 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
3066 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
3067 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
3068 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
3069 }
3071 // Thread synchronization
3072 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
3073 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
3074 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
3075 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
3077 // vector_shuffle v1, <undef> <1, 1, 3, 3>
3078 let AddedComplexity = 15 in
3079 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
3080 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3081 let AddedComplexity = 20 in
3082 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3083 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3085 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3086 let AddedComplexity = 15 in
3087 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3088 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3089 let AddedComplexity = 20 in
3090 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3091 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3093 //===---------------------------------------------------------------------===//
3094 // SSSE3 Instructions
3095 //===---------------------------------------------------------------------===//
3097 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
3098 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
3099 Intrinsic IntId64, Intrinsic IntId128> {
3100 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
3101 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3102 [(set VR64:$dst, (IntId64 VR64:$src))]>;
3104 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
3105 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3106 [(set VR64:$dst,
3107 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
3109 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3110 (ins VR128:$src),
3111 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3112 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3113 OpSize;
3115 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3116 (ins i128mem:$src),
3117 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3118 [(set VR128:$dst,
3119 (IntId128
3120 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
3121 }
3123 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
3124 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
3125 Intrinsic IntId64, Intrinsic IntId128> {
3126 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3127 (ins VR64:$src),
3128 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3129 [(set VR64:$dst, (IntId64 VR64:$src))]>;
3131 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3132 (ins i64mem:$src),
3133 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3134 [(set VR64:$dst,
3135 (IntId64
3136 (bitconvert (memopv4i16 addr:$src))))]>;
3138 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3139 (ins VR128:$src),
3140 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3141 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3142 OpSize;
3144 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3145 (ins i128mem:$src),
3146 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3147 [(set VR128:$dst,
3148 (IntId128
3149 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3150 }
3152 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
3153 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
3154 Intrinsic IntId64, Intrinsic IntId128> {
3155 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3156 (ins VR64:$src),
3157 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3158 [(set VR64:$dst, (IntId64 VR64:$src))]>;
3160 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3161 (ins i64mem:$src),
3162 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3163 [(set VR64:$dst,
3164 (IntId64
3165 (bitconvert (memopv2i32 addr:$src))))]>;
3167 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3168 (ins VR128:$src),
3169 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3170 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3171 OpSize;
3173 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3174 (ins i128mem:$src),
3175 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3176 [(set VR128:$dst,
3177 (IntId128
3178 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
3179 }
3181 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
3182 int_x86_ssse3_pabs_b,
3183 int_x86_ssse3_pabs_b_128>;
3184 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
3185 int_x86_ssse3_pabs_w,
3186 int_x86_ssse3_pabs_w_128>;
3187 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
3188 int_x86_ssse3_pabs_d,
3189 int_x86_ssse3_pabs_d_128>;
3191 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
3192 let Constraints = "$src1 = $dst" in {
3193 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
3194 Intrinsic IntId64, Intrinsic IntId128,
3195 bit Commutable = 0> {
3196 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3197 (ins VR64:$src1, VR64:$src2),
3198 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3199 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
3200 let isCommutable = Commutable;
3201 }
3202 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3203 (ins VR64:$src1, i64mem:$src2),
3204 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3205 [(set VR64:$dst,
3206 (IntId64 VR64:$src1,
3207 (bitconvert (memopv8i8 addr:$src2))))]>;
3209 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3210 (ins VR128:$src1, VR128:$src2),
3211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3212 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3213 OpSize {
3214 let isCommutable = Commutable;
3215 }
3216 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3217 (ins VR128:$src1, i128mem:$src2),
3218 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3219 [(set VR128:$dst,
3220 (IntId128 VR128:$src1,
3221 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3222 }
3223 }
3225 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
3226 let Constraints = "$src1 = $dst" in {
3227 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
3228 Intrinsic IntId64, Intrinsic IntId128,
3229 bit Commutable = 0> {
3230 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3231 (ins VR64:$src1, VR64:$src2),
3232 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3233 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
3234 let isCommutable = Commutable;
3235 }
3236 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3237 (ins VR64:$src1, i64mem:$src2),
3238 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3239 [(set VR64:$dst,
3240 (IntId64 VR64:$src1,
3241 (bitconvert (memopv4i16 addr:$src2))))]>;
3243 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3244 (ins VR128:$src1, VR128:$src2),
3245 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3246 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3247 OpSize {
3248 let isCommutable = Commutable;
3249 }
3250 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3251 (ins VR128:$src1, i128mem:$src2),
3252 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3253 [(set VR128:$dst,
3254 (IntId128 VR128:$src1,
3255 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
3256 }
3257 }
3259 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
3260 let Constraints = "$src1 = $dst" in {
3261 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
3262 Intrinsic IntId64, Intrinsic IntId128,
3263 bit Commutable = 0> {
3264 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3265 (ins VR64:$src1, VR64:$src2),
3266 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3267 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
3268 let isCommutable = Commutable;
3269 }
3270 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3271 (ins VR64:$src1, i64mem:$src2),
3272 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3273 [(set VR64:$dst,
3274 (IntId64 VR64:$src1,
3275 (bitconvert (memopv2i32 addr:$src2))))]>;
3277 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3278 (ins VR128:$src1, VR128:$src2),
3279 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3280 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3281 OpSize {
3282 let isCommutable = Commutable;
3283 }
3284 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3285 (ins VR128:$src1, i128mem:$src2),
3286 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3287 [(set VR128:$dst,
3288 (IntId128 VR128:$src1,
3289 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
3290 }
3291 }
3293 let ImmT = NoImm in { // None of these have i8 immediate fields.
3294 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
3295 int_x86_ssse3_phadd_w,
3296 int_x86_ssse3_phadd_w_128>;
3297 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
3298 int_x86_ssse3_phadd_d,
3299 int_x86_ssse3_phadd_d_128>;
3300 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
3301 int_x86_ssse3_phadd_sw,
3302 int_x86_ssse3_phadd_sw_128>;
3303 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
3304 int_x86_ssse3_phsub_w,
3305 int_x86_ssse3_phsub_w_128>;
3306 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
3307 int_x86_ssse3_phsub_d,
3308 int_x86_ssse3_phsub_d_128>;
3309 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
3310 int_x86_ssse3_phsub_sw,
3311 int_x86_ssse3_phsub_sw_128>;
3312 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
3313 int_x86_ssse3_pmadd_ub_sw,
3314 int_x86_ssse3_pmadd_ub_sw_128>;
3315 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
3316 int_x86_ssse3_pmul_hr_sw,
3317 int_x86_ssse3_pmul_hr_sw_128, 1>;
3319 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
3320 int_x86_ssse3_pshuf_b,
3321 int_x86_ssse3_pshuf_b_128>;
3322 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
3323 int_x86_ssse3_psign_b,
3324 int_x86_ssse3_psign_b_128>;
3325 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
3326 int_x86_ssse3_psign_w,
3327 int_x86_ssse3_psign_w_128>;
3328 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
3329 int_x86_ssse3_psign_d,
3330 int_x86_ssse3_psign_d_128>;
3331 }
3333 // palignr patterns.
3334 let Constraints = "$src1 = $dst" in {
3335 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
3336 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
3337 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3338 []>;
3339 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
3340 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
3341 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3342 []>;
3344 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3345 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3346 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3347 []>, OpSize;
3348 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3349 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3350 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3351 []>, OpSize;
3352 }
3354 let AddedComplexity = 5 in {
3356 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
3357 (PALIGNR64rr VR64:$src2, VR64:$src1,
3358 (SHUFFLE_get_palign_imm VR64:$src3))>,
3359 Requires<[HasSSSE3]>;
3360 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
3361 (PALIGNR64rr VR64:$src2, VR64:$src1,
3362 (SHUFFLE_get_palign_imm VR64:$src3))>,
3363 Requires<[HasSSSE3]>;
3364 def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
3365 (PALIGNR64rr VR64:$src2, VR64:$src1,
3366 (SHUFFLE_get_palign_imm VR64:$src3))>,
3367 Requires<[HasSSSE3]>;
3368 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
3369 (PALIGNR64rr VR64:$src2, VR64:$src1,
3370 (SHUFFLE_get_palign_imm VR64:$src3))>,
3371 Requires<[HasSSSE3]>;
3372 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
3373 (PALIGNR64rr VR64:$src2, VR64:$src1,
3374 (SHUFFLE_get_palign_imm VR64:$src3))>,
3375 Requires<[HasSSSE3]>;
3377 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3378 (PALIGNR128rr VR128:$src2, VR128:$src1,
3379 (SHUFFLE_get_palign_imm VR128:$src3))>,
3380 Requires<[HasSSSE3]>;
3381 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3382 (PALIGNR128rr VR128:$src2, VR128:$src1,
3383 (SHUFFLE_get_palign_imm VR128:$src3))>,
3384 Requires<[HasSSSE3]>;
3385 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3386 (PALIGNR128rr VR128:$src2, VR128:$src1,
3387 (SHUFFLE_get_palign_imm VR128:$src3))>,
3388 Requires<[HasSSSE3]>;
3389 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3390 (PALIGNR128rr VR128:$src2, VR128:$src1,
3391 (SHUFFLE_get_palign_imm VR128:$src3))>,
3392 Requires<[HasSSSE3]>;
3393 }
3395 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3396 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3397 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3398 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3400 //===---------------------------------------------------------------------===//
3401 // Non-Instruction Patterns
3402 //===---------------------------------------------------------------------===//
3404 // extload f32 -> f64. This matches load+fextend because we have a hack in
3405 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3406 // combine.
3407 // Since these loads aren't folded into the fextend, we have to match it
3408 // explicitly here.
3409 let Predicates = [HasSSE2] in
3410 def : Pat<(fextend (loadf32 addr:$src)),
3411 (CVTSS2SDrm addr:$src)>;
3413 // bit_convert
3414 let Predicates = [HasSSE2] in {
3415 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3416 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3417 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3418 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3419 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3420 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3421 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3422 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3423 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3424 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3425 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3426 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3427 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3428 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3429 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3430 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3431 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3432 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3433 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3434 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3435 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3436 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3437 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3438 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3439 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3440 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3441 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3442 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3443 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3444 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3445 }
3447 // Move scalar to XMM zero-extended
3448 // movd to XMM register zero-extends
3449 let AddedComplexity = 15 in {
3450 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3451 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3452 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3453 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3454 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3455 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3456 (MOVSSrr (v4f32 (V_SET0PS)),
3457 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3458 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3459 (MOVSSrr (v4i32 (V_SET0PI)),
3460 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3461 }
3463 // Splat v2f64 / v2i64
3464 let AddedComplexity = 10 in {
3465 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3466 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3467 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3468 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3469 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3470 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3471 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3472 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3473 }
3475 // Special unary SHUFPSrri case.
3476 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3477 (SHUFPSrri VR128:$src1, VR128:$src1,
3478 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3479 let AddedComplexity = 5 in
3480 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3481 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3482 Requires<[HasSSE2]>;
3483 // Special unary SHUFPDrri case.
3484 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3485 (SHUFPDrri VR128:$src1, VR128:$src1,
3486 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3487 Requires<[HasSSE2]>;
3488 // Special unary SHUFPDrri case.
3489 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3490 (SHUFPDrri VR128:$src1, VR128:$src1,
3491 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3492 Requires<[HasSSE2]>;
3493 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3494 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3495 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3496 Requires<[HasSSE2]>;
3498 // Special binary v4i32 shuffle cases with SHUFPS.
3499 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3500 (SHUFPSrri VR128:$src1, VR128:$src2,
3501 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3502 Requires<[HasSSE2]>;
3503 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3504 (SHUFPSrmi VR128:$src1, addr:$src2,
3505 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3506 Requires<[HasSSE2]>;
3507 // Special binary v2i64 shuffle cases using SHUFPDrri.
3508 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3509 (SHUFPDrri VR128:$src1, VR128:$src2,
3510 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3511 Requires<[HasSSE2]>;
3513 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3514 let AddedComplexity = 15 in {
3515 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3516 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3517 Requires<[OptForSpeed, HasSSE2]>;
3518 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3519 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3520 Requires<[OptForSpeed, HasSSE2]>;
3521 }
3522 let AddedComplexity = 10 in {
3523 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3524 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3525 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3526 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3527 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3528 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3529 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3530 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3531 }
3533 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3534 let AddedComplexity = 15 in {
3535 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3536 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3537 Requires<[OptForSpeed, HasSSE2]>;
3538 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3539 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3540 Requires<[OptForSpeed, HasSSE2]>;
3541 }
3542 let AddedComplexity = 10 in {
3543 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3544 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3545 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3546 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3547 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3548 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3549 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3550 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3551 }
3553 let AddedComplexity = 20 in {
3554 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3555 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3556 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3558 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3559 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3560 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3562 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3563 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3564 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3565 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3566 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3567 }
3569 let AddedComplexity = 20 in {
3570 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3571 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3572 (MOVLPSrm VR128:$src1, addr:$src2)>;
3573 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3574 (MOVLPDrm VR128:$src1, addr:$src2)>;
3575 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3576 (MOVLPSrm VR128:$src1, addr:$src2)>;
3577 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3578 (MOVLPDrm VR128:$src1, addr:$src2)>;
3579 }
3581 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3582 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3583 (MOVLPSmr addr:$src1, VR128:$src2)>;
3584 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3585 (MOVLPDmr addr:$src1, VR128:$src2)>;
3586 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3587 addr:$src1),
3588 (MOVLPSmr addr:$src1, VR128:$src2)>;
3589 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3590 (MOVLPDmr addr:$src1, VR128:$src2)>;
3592 let AddedComplexity = 15 in {
3593 // Setting the lowest element in the vector.
3594 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3595 (MOVSSrr (v4i32 VR128:$src1),
3596 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3597 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3598 (MOVSDrr (v2i64 VR128:$src1),
3599 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3601 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3602 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3603 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3604 Requires<[HasSSE2]>;
3605 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3606 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3607 Requires<[HasSSE2]>;
3608 }
3610 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3611 // fall back to this for SSE1)
3612 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3613 (SHUFPSrri VR128:$src2, VR128:$src1,
3614 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3616 // Set lowest element and zero upper elements.
3617 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3618 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3620 // Some special case pandn patterns.
3621 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3622 VR128:$src2)),
3623 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3624 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3625 VR128:$src2)),
3626 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3627 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3628 VR128:$src2)),
3629 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3631 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3632 (memop addr:$src2))),
3633 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3634 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3635 (memop addr:$src2))),
3636 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3637 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3638 (memop addr:$src2))),
3639 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3641 // vector -> vector casts
3642 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3643 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3644 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3645 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3646 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3647 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3648 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3649 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3651 // Use movaps / movups for SSE integer load / store (one byte shorter).
3652 def : Pat<(alignedloadv4i32 addr:$src),
3653 (MOVAPSrm addr:$src)>;
3654 def : Pat<(loadv4i32 addr:$src),
3655 (MOVUPSrm addr:$src)>;
3656 def : Pat<(alignedloadv2i64 addr:$src),
3657 (MOVAPSrm addr:$src)>;
3658 def : Pat<(loadv2i64 addr:$src),
3659 (MOVUPSrm addr:$src)>;
3661 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3662 (MOVAPSmr addr:$dst, VR128:$src)>;
3663 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3664 (MOVAPSmr addr:$dst, VR128:$src)>;
3665 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3666 (MOVAPSmr addr:$dst, VR128:$src)>;
3667 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3668 (MOVAPSmr addr:$dst, VR128:$src)>;
3669 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3670 (MOVUPSmr addr:$dst, VR128:$src)>;
3671 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3672 (MOVUPSmr addr:$dst, VR128:$src)>;
3673 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3674 (MOVUPSmr addr:$dst, VR128:$src)>;
3675 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3676 (MOVUPSmr addr:$dst, VR128:$src)>;
3678 //===----------------------------------------------------------------------===//
3679 // SSE4.1 Instructions
3680 //===----------------------------------------------------------------------===//
3682 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3683 string OpcodeStr,
3684 Intrinsic V4F32Int,
3685 Intrinsic V2F64Int> {
3686 // Intrinsic operation, reg.
3687 // Vector intrinsic operation, reg
3688 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3689 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3690 !strconcat(OpcodeStr,
3691 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3692 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3693 OpSize;
3695 // Vector intrinsic operation, mem
3696 def PSm_Int : Ii8<opcps, MRMSrcMem,
3697 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3698 !strconcat(OpcodeStr,
3699 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3700 [(set VR128:$dst,
3701 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3702 TA, OpSize,
3703 Requires<[HasSSE41]>;
3705 // Vector intrinsic operation, reg
3706 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3707 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3708 !strconcat(OpcodeStr,
3709 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3710 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3711 OpSize;
3713 // Vector intrinsic operation, mem
3714 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3715 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3716 !strconcat(OpcodeStr,
3717 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3718 [(set VR128:$dst,
3719 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3720 OpSize;
3721 }
3723 let Constraints = "$src1 = $dst" in {
3724 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3725 string OpcodeStr,
3726 Intrinsic F32Int,
3727 Intrinsic F64Int> {
3728 // Intrinsic operation, reg.
3729 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3730 (outs VR128:$dst),
3731 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3732 !strconcat(OpcodeStr,
3733 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3734 [(set VR128:$dst,
3735 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3736 OpSize;
3738 // Intrinsic operation, mem.
3739 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3740 (outs VR128:$dst),
3741 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3742 !strconcat(OpcodeStr,
3743 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3744 [(set VR128:$dst,
3745 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3746 OpSize;
3748 // Intrinsic operation, reg.
3749 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3750 (outs VR128:$dst),
3751 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3752 !strconcat(OpcodeStr,
3753 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3754 [(set VR128:$dst,
3755 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3756 OpSize;
3758 // Intrinsic operation, mem.
3759 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3760 (outs VR128:$dst),
3761 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3762 !strconcat(OpcodeStr,
3763 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3764 [(set VR128:$dst,
3765 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3766 OpSize;
3767 }
3768 }
3770 // FP round - roundss, roundps, roundsd, roundpd
3771 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3772 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3773 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3774 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3776 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3777 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3778 Intrinsic IntId128> {
3779 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3780 (ins VR128:$src),
3781 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3782 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3783 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3784 (ins i128mem:$src),
3785 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3786 [(set VR128:$dst,
3787 (IntId128
3788 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3789 }
3791 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3792 int_x86_sse41_phminposuw>;
3794 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3795 let Constraints = "$src1 = $dst" in {
3796 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3797 Intrinsic IntId128, bit Commutable = 0> {
3798 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3799 (ins VR128:$src1, VR128:$src2),
3800 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3801 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3802 OpSize {
3803 let isCommutable = Commutable;
3804 }
3805 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3806 (ins VR128:$src1, i128mem:$src2),
3807 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3808 [(set VR128:$dst,
3809 (IntId128 VR128:$src1,
3810 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3811 }
3812 }
3814 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3815 int_x86_sse41_pcmpeqq, 1>;
3816 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3817 int_x86_sse41_packusdw, 0>;
3818 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3819 int_x86_sse41_pminsb, 1>;
3820 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3821 int_x86_sse41_pminsd, 1>;
3822 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3823 int_x86_sse41_pminud, 1>;
3824 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3825 int_x86_sse41_pminuw, 1>;
3826 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3827 int_x86_sse41_pmaxsb, 1>;
3828 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3829 int_x86_sse41_pmaxsd, 1>;
3830 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3831 int_x86_sse41_pmaxud, 1>;
3832 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3833 int_x86_sse41_pmaxuw, 1>;
3835 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3837 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3838 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3839 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3840 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3842 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3843 let Constraints = "$src1 = $dst" in {
3844 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3845 SDNode OpNode, Intrinsic IntId128,
3846 bit Commutable = 0> {
3847 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3848 (ins VR128:$src1, VR128:$src2),
3849 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3850 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3851 VR128:$src2))]>, OpSize {
3852 let isCommutable = Commutable;
3853 }
3854 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3855 (ins VR128:$src1, VR128:$src2),
3856 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3857 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3858 OpSize {
3859 let isCommutable = Commutable;
3860 }
3861 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3862 (ins VR128:$src1, i128mem:$src2),
3863 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3864 [(set VR128:$dst,
3865 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3866 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3867 (ins VR128:$src1, i128mem:$src2),
3868 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3869 [(set VR128:$dst,
3870 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3871 OpSize;
3872 }
3873 }
3875 /// SS48I_binop_rm - Simple SSE41 binary operator.
3876 let Constraints = "$src1 = $dst" in {
3877 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3878 ValueType OpVT, bit Commutable = 0> {
3879 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3880 (ins VR128:$src1, VR128:$src2),
3881 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3882 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
3883 OpSize {
3884 let isCommutable = Commutable;
3885 }
3886 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3887 (ins VR128:$src1, i128mem:$src2),
3888 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3889 [(set VR128:$dst, (OpNode VR128:$src1,
3890 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
3891 OpSize;
3892 }
3893 }
3895 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
3897 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3898 let Constraints = "$src1 = $dst" in {
3899 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3900 Intrinsic IntId128, bit Commutable = 0> {
3901 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3902 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3903 !strconcat(OpcodeStr,
3904 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3905 [(set VR128:$dst,
3906 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3907 OpSize {
3908 let isCommutable = Commutable;
3909 }
3910 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3911 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3912 !strconcat(OpcodeStr,
3913 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3914 [(set VR128:$dst,
3915 (IntId128 VR128:$src1,
3916 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3917 OpSize;
3918 }
3919 }
3921 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3922 int_x86_sse41_blendps, 0>;
3923 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3924 int_x86_sse41_blendpd, 0>;
3925 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3926 int_x86_sse41_pblendw, 0>;
3927 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3928 int_x86_sse41_dpps, 1>;
3929 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3930 int_x86_sse41_dppd, 1>;
3931 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3932 int_x86_sse41_mpsadbw, 0>;
3935 /// SS41I_ternary_int - SSE 4.1 ternary operator
3936 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3937 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3938 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3939 (ins VR128:$src1, VR128:$src2),
3940 !strconcat(OpcodeStr,
3941 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3942 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3943 OpSize;
3945 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3946 (ins VR128:$src1, i128mem:$src2),
3947 !strconcat(OpcodeStr,
3948 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3949 [(set VR128:$dst,
3950 (IntId VR128:$src1,
3951 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3952 }
3953 }
3955 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3956 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3957 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3960 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3961 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3962 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3963 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3965 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3966 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3967 [(set VR128:$dst,
3968 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3969 OpSize;
3970 }
3972 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3973 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3974 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3975 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3976 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3977 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3979 // Common patterns involving scalar load.
3980 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3981 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3982 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3983 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3985 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3986 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3987 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3988 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3990 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3991 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3992 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3993 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3995 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3996 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3997 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3998 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4000 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4001 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4002 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4003 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4005 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4006 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4007 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4008 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4011 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4012 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4013 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4014 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4016 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4017 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4018 [(set VR128:$dst,
4019 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4020 OpSize;
4021 }
4023 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4024 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4025 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4026 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4028 // Common patterns involving scalar load
4029 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4030 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4031 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4032 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4034 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4035 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4036 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4037 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4040 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4041 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4042 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4043 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4045 // Expecting a i16 load any extended to i32 value.
4046 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4047 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4048 [(set VR128:$dst, (IntId (bitconvert
4049 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4050 OpSize;
4051 }
4053 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4054 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4056 // Common patterns involving scalar load
4057 def : Pat<(int_x86_sse41_pmovsxbq
4058 (bitconvert (v4i32 (X86vzmovl
4059 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4060 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4062 def : Pat<(int_x86_sse41_pmovzxbq
4063 (bitconvert (v4i32 (X86vzmovl
4064 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4065 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4068 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4069 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4070 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4071 (ins VR128:$src1, i32i8imm:$src2),
4072 !strconcat(OpcodeStr,
4073 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4074 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4075 OpSize;
4076 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4077 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4078 !strconcat(OpcodeStr,
4079 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4080 []>, OpSize;
4081 // FIXME:
4082 // There's an AssertZext in the way of writing the store pattern
4083 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4084 }
4086 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4089 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4090 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4091 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4092 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4093 !strconcat(OpcodeStr,
4094 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4095 []>, OpSize;
4096 // FIXME:
4097 // There's an AssertZext in the way of writing the store pattern
4098 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4099 }
4101 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4104 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4105 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4106 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4107 (ins VR128:$src1, i32i8imm:$src2),
4108 !strconcat(OpcodeStr,
4109 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4110 [(set GR32:$dst,
4111 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4112 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4113 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4114 !strconcat(OpcodeStr,
4115 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4116 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4117 addr:$dst)]>, OpSize;
4118 }
4120 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4123 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4124 /// destination
4125 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4126 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4127 (ins VR128:$src1, i32i8imm:$src2),
4128 !strconcat(OpcodeStr,
4129 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4130 [(set GR32:$dst,
4131 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4132 OpSize;
4133 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4134 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4135 !strconcat(OpcodeStr,
4136 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4137 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4138 addr:$dst)]>, OpSize;
4139 }
4141 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4143 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4144 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4145 imm:$src2))),
4146 addr:$dst),
4147 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4148 Requires<[HasSSE41]>;
4150 let Constraints = "$src1 = $dst" in {
4151 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
4152 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4153 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4154 !strconcat(OpcodeStr,
4155 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4156 [(set VR128:$dst,
4157 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4158 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4159 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4160 !strconcat(OpcodeStr,
4161 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4162 [(set VR128:$dst,
4163 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4164 imm:$src3))]>, OpSize;
4165 }
4166 }
4168 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4170 let Constraints = "$src1 = $dst" in {
4171 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
4172 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4173 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4174 !strconcat(OpcodeStr,
4175 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4176 [(set VR128:$dst,
4177 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4178 OpSize;
4179 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4180 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4181 !strconcat(OpcodeStr,
4182 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4183 [(set VR128:$dst,
4184 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4185 imm:$src3)))]>, OpSize;
4186 }
4187 }
4189 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4191 // insertps has a few different modes, there's the first two here below which
4192 // are optimized inserts that won't zero arbitrary elements in the destination
4193 // vector. The next one matches the intrinsic and could zero arbitrary elements
4194 // in the target vector.
4195 let Constraints = "$src1 = $dst" in {
4196 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
4197 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4198 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4199 !strconcat(OpcodeStr,
4200 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4201 [(set VR128:$dst,
4202 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4203 OpSize;
4204 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4205 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4206 !strconcat(OpcodeStr,
4207 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4208 [(set VR128:$dst,
4209 (X86insrtps VR128:$src1,
4210 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4211 imm:$src3))]>, OpSize;
4212 }
4213 }
4215 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4217 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4218 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
4220 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4221 // the intel intrinsic that corresponds to this.
4222 let Defs = [EFLAGS] in {
4223 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4224 "ptest \t{$src2, $src1|$src1, $src2}",
4225 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
4226 OpSize;
4227 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
4228 "ptest \t{$src2, $src1|$src1, $src2}",
4229 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
4230 OpSize;
4231 }
4233 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4234 "movntdqa\t{$src, $dst|$dst, $src}",
4235 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4236 OpSize;
4239 //===----------------------------------------------------------------------===//
4240 // SSE4.2 Instructions
4241 //===----------------------------------------------------------------------===//
4243 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4244 let Constraints = "$src1 = $dst" in {
4245 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4246 Intrinsic IntId128, bit Commutable = 0> {
4247 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4248 (ins VR128:$src1, VR128:$src2),
4249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4250 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4251 OpSize {
4252 let isCommutable = Commutable;
4253 }
4254 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4255 (ins VR128:$src1, i128mem:$src2),
4256 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4257 [(set VR128:$dst,
4258 (IntId128 VR128:$src1,
4259 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4260 }
4261 }
4263 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4265 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4266 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4267 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4268 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4270 // crc intrinsic instruction
4271 // This set of instructions are only rm, the only difference is the size
4272 // of r and m.
4273 let Constraints = "$src1 = $dst" in {
4274 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
4275 (ins GR32:$src1, i8mem:$src2),
4276 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4277 [(set GR32:$dst,
4278 (int_x86_sse42_crc32_8 GR32:$src1,
4279 (load addr:$src2)))]>;
4280 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
4281 (ins GR32:$src1, GR8:$src2),
4282 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4283 [(set GR32:$dst,
4284 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
4285 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4286 (ins GR32:$src1, i16mem:$src2),
4287 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4288 [(set GR32:$dst,
4289 (int_x86_sse42_crc32_16 GR32:$src1,
4290 (load addr:$src2)))]>,
4291 OpSize;
4292 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4293 (ins GR32:$src1, GR16:$src2),
4294 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4295 [(set GR32:$dst,
4296 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
4297 OpSize;
4298 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4299 (ins GR32:$src1, i32mem:$src2),
4300 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4301 [(set GR32:$dst,
4302 (int_x86_sse42_crc32_32 GR32:$src1,
4303 (load addr:$src2)))]>;
4304 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4305 (ins GR32:$src1, GR32:$src2),
4306 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4307 [(set GR32:$dst,
4308 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
4309 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
4310 (ins GR64:$src1, i8mem:$src2),
4311 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4312 [(set GR64:$dst,
4313 (int_x86_sse42_crc64_8 GR64:$src1,
4314 (load addr:$src2)))]>,
4315 REX_W;
4316 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
4317 (ins GR64:$src1, GR8:$src2),
4318 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4319 [(set GR64:$dst,
4320 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
4321 REX_W;
4322 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
4323 (ins GR64:$src1, i64mem:$src2),
4324 "crc32{q} \t{$src2, $src1|$src1, $src2}",
4325 [(set GR64:$dst,
4326 (int_x86_sse42_crc64_64 GR64:$src1,
4327 (load addr:$src2)))]>,
4328 REX_W;
4329 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
4330 (ins GR64:$src1, GR64:$src2),
4331 "crc32{q} \t{$src2, $src1|$src1, $src2}",
4332 [(set GR64:$dst,
4333 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
4334 REX_W;
4335 }
4337 // String/text processing instructions.
4338 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4339 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
4340 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4341 "#PCMPISTRM128rr PSEUDO!",
4342 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4343 imm:$src3))]>, OpSize;
4344 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
4345 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4346 "#PCMPISTRM128rm PSEUDO!",
4347 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
4348 imm:$src3))]>, OpSize;
4349 }
4351 let Defs = [XMM0, EFLAGS] in {
4352 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4353 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4354 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4355 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4356 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4357 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4358 }
4360 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4361 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
4362 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4363 "#PCMPESTRM128rr PSEUDO!",
4364 [(set VR128:$dst,
4365 (int_x86_sse42_pcmpestrm128
4366 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
4368 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
4369 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4370 "#PCMPESTRM128rm PSEUDO!",
4371 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4372 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
4373 OpSize;
4374 }
4376 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4377 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4378 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4379 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4380 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4381 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4382 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4383 }
4385 let Defs = [ECX, EFLAGS] in {
4386 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
4387 def rr : SS42AI<0x63, MRMSrcReg, (outs),
4388 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4389 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
4390 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
4391 (implicit EFLAGS)]>, OpSize;
4392 def rm : SS42AI<0x63, MRMSrcMem, (outs),
4393 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4394 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
4395 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
4396 (implicit EFLAGS)]>, OpSize;
4397 }
4398 }
4400 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
4401 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
4402 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
4403 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
4404 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
4405 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
4407 let Defs = [ECX, EFLAGS] in {
4408 let Uses = [EAX, EDX] in {
4409 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
4410 def rr : SS42AI<0x61, MRMSrcReg, (outs),
4411 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4412 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4413 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4414 (implicit EFLAGS)]>, OpSize;
4415 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4416 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4417 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4418 [(set ECX,
4419 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4420 (implicit EFLAGS)]>, OpSize;
4421 }
4422 }
4423 }
4425 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4426 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4427 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4428 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4429 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4430 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
4432 //===----------------------------------------------------------------------===//
4433 // AES-NI Instructions
4434 //===----------------------------------------------------------------------===//
4436 let Constraints = "$src1 = $dst" in {
4437 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
4438 Intrinsic IntId128, bit Commutable = 0> {
4439 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
4440 (ins VR128:$src1, VR128:$src2),
4441 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4442 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4443 OpSize {
4444 let isCommutable = Commutable;
4445 }
4446 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
4447 (ins VR128:$src1, i128mem:$src2),
4448 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4449 [(set VR128:$dst,
4450 (IntId128 VR128:$src1,
4451 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4452 }
4453 }
4455 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
4456 int_x86_aesni_aesenc>;
4457 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
4458 int_x86_aesni_aesenclast>;
4459 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
4460 int_x86_aesni_aesdec>;
4461 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
4462 int_x86_aesni_aesdeclast>;
4464 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
4465 (AESENCrr VR128:$src1, VR128:$src2)>;
4466 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
4467 (AESENCrm VR128:$src1, addr:$src2)>;
4468 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
4469 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
4470 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
4471 (AESENCLASTrm VR128:$src1, addr:$src2)>;
4472 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
4473 (AESDECrr VR128:$src1, VR128:$src2)>;
4474 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
4475 (AESDECrm VR128:$src1, addr:$src2)>;
4476 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
4477 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
4478 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
4479 (AESDECLASTrm VR128:$src1, addr:$src2)>;
4481 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
4482 (ins VR128:$src1),
4483 "aesimc\t{$src1, $dst|$dst, $src1}",
4484 [(set VR128:$dst,
4485 (int_x86_aesni_aesimc VR128:$src1))]>,
4486 OpSize;
4488 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
4489 (ins i128mem:$src1),
4490 "aesimc\t{$src1, $dst|$dst, $src1}",
4491 [(set VR128:$dst,
4492 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
4493 OpSize;
4495 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
4496 (ins VR128:$src1, i8imm:$src2),
4497 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4498 [(set VR128:$dst,
4499 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
4500 OpSize;
4501 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
4502 (ins i128mem:$src1, i8imm:$src2),
4503 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4504 [(set VR128:$dst,
4505 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
4506 imm:$src2))]>,
4507 OpSize;