lib/Target/MSP430/MSP430RegisterInfo.cpp

   1 //===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the MSP430 implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "msp430-reg-info"
  15
  16 #include "MSP430.h"
  17 #include "MSP430MachineFunctionInfo.h"
  18 #include "MSP430RegisterInfo.h"
  19 #include "MSP430TargetMachine.h"
  20 #include "llvm/Function.h"
  21 #include "llvm/CodeGen/MachineFrameInfo.h"
  22 #include "llvm/CodeGen/MachineFunction.h"
  23 #include "llvm/CodeGen/MachineInstrBuilder.h"
  24 #include "llvm/Target/TargetMachine.h"
  25 #include "llvm/Target/TargetOptions.h"
  26 #include "llvm/ADT/BitVector.h"
  27 #include "llvm/Support/ErrorHandling.h"
  28
  29 using namespace llvm;
  30
  31 // FIXME: Provide proper call frame setup / destroy opcodes.
  32 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
  33                                        const TargetInstrInfo &tii)
  34   : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
  35     TM(tm), TII(tii) {
  36   StackAlign = TM.getFrameInfo()->getStackAlignment();
  37 }
  38
  39 const unsigned*
  40 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
  41   const Function* F = MF->getFunction();
  42   static const unsigned CalleeSavedRegs[] = {
  43     MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
  44     MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
  45     0
  46   };
  47   static const unsigned CalleeSavedRegsFP[] = {
  48     MSP430::R5W, MSP430::R6W, MSP430::R7W,
  49     MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
  50     0
  51   };
  52   static const unsigned CalleeSavedRegsIntr[] = {
  53     MSP430::FPW,  MSP430::R5W,  MSP430::R6W,  MSP430::R7W,
  54     MSP430::R8W,  MSP430::R9W,  MSP430::R10W, MSP430::R11W,
  55     MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
  56     0
  57   };
  58   static const unsigned CalleeSavedRegsIntrFP[] = {
  59     MSP430::R5W,  MSP430::R6W,  MSP430::R7W,
  60     MSP430::R8W,  MSP430::R9W,  MSP430::R10W, MSP430::R11W,
  61     MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
  62     0
  63   };
  64
  65   if (hasFP(*MF))
  66     return (F->getCallingConv() == CallingConv::MSP430_INTR ?
  67             CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
  68   else
  69     return (F->getCallingConv() == CallingConv::MSP430_INTR ?
  70             CalleeSavedRegsIntr : CalleeSavedRegs);
  71
  72 }
  73
  74 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
  75   BitVector Reserved(getNumRegs());
  76
  77   // Mark 4 special registers as reserved.
  78   Reserved.set(MSP430::PCW);
  79   Reserved.set(MSP430::SPW);
  80   Reserved.set(MSP430::SRW);
  81   Reserved.set(MSP430::CGW);
  82
  83   // Mark frame pointer as reserved if needed.
  84   if (hasFP(MF))
  85     Reserved.set(MSP430::FPW);
  86
  87   return Reserved;
  88 }
  89
  90 const TargetRegisterClass *
  91 MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
  92   return &MSP430::GR16RegClass;
  93 }
  94
  95
  96 bool MSP430RegisterInfo::hasFP(const MachineFunction &MF) const {
  97   const MachineFrameInfo *MFI = MF.getFrameInfo();
  98
  99   return (DisableFramePointerElim(MF) ||
 100           MF.getFrameInfo()->hasVarSizedObjects() ||
 101           MFI->isFrameAddressTaken());
 102 }
 103
 104 bool MSP430RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
 105   return !MF.getFrameInfo()->hasVarSizedObjects();
 106 }
 107
 108 void MSP430RegisterInfo::
 109 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
 110                               MachineBasicBlock::iterator I) const {
 111   if (!hasReservedCallFrame(MF)) {
 112     // If the stack pointer can be changed after prologue, turn the
 113     // adjcallstackup instruction into a 'sub SPW, <amt>' and the
 114     // adjcallstackdown instruction into 'add SPW, <amt>'
 115     // TODO: consider using push / pop instead of sub + store / add
 116     MachineInstr *Old = I;
 117     uint64_t Amount = Old->getOperand(0).getImm();
 118     if (Amount != 0) {
 119       // We need to keep the stack aligned properly.  To do this, we round the
 120       // amount of space needed for the outgoing arguments up to the next
 121       // alignment boundary.
 122       Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
 123
 124       MachineInstr *New = 0;
 125       if (Old->getOpcode() == getCallFrameSetupOpcode()) {
 126         New = BuildMI(MF, Old->getDebugLoc(),
 127                       TII.get(MSP430::SUB16ri), MSP430::SPW)
 128           .addReg(MSP430::SPW).addImm(Amount);
 129       } else {
 130         assert(Old->getOpcode() == getCallFrameDestroyOpcode());
 131         // factor out the amount the callee already popped.
 132         uint64_t CalleeAmt = Old->getOperand(1).getImm();
 133         Amount -= CalleeAmt;
 134         if (Amount)
 135           New = BuildMI(MF, Old->getDebugLoc(),
 136                         TII.get(MSP430::ADD16ri), MSP430::SPW)
 137             .addReg(MSP430::SPW).addImm(Amount);
 138       }
 139
 140       if (New) {
 141         // The SRW implicit def is dead.
 142         New->getOperand(3).setIsDead();
 143
 144         // Replace the pseudo instruction with a new instruction...
 145         MBB.insert(I, New);
 146       }
 147     }
 148   } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
 149     // If we are performing frame pointer elimination and if the callee pops
 150     // something off the stack pointer, add it back.
 151     if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
 152       MachineInstr *Old = I;
 153       MachineInstr *New =
 154         BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
 155                 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
 156       // The SRW implicit def is dead.
 157       New->getOperand(3).setIsDead();
 158
 159       MBB.insert(I, New);
 160     }
 161   }
 162
 163   MBB.erase(I);
 164 }
 165
 166 void
 167 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 168                                         int SPAdj, RegScavenger *RS) const {
 169   assert(SPAdj == 0 && "Unexpected");
 170
 171   unsigned i = 0;
 172   MachineInstr &MI = *II;
 173   MachineBasicBlock &MBB = *MI.getParent();
 174   MachineFunction &MF = *MBB.getParent();
 175   DebugLoc dl = MI.getDebugLoc();
 176   while (!MI.getOperand(i).isFI()) {
 177     ++i;
 178     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
 179   }
 180
 181   int FrameIndex = MI.getOperand(i).getIndex();
 182
 183   unsigned BasePtr = (hasFP(MF) ? MSP430::FPW : MSP430::SPW);
 184   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
 185
 186   // Skip the saved PC
 187   Offset += 2;
 188
 189   if (!hasFP(MF))
 190     Offset += MF.getFrameInfo()->getStackSize();
 191   else
 192     Offset += 2; // Skip the saved FPW
 193
 194   // Fold imm into offset
 195   Offset += MI.getOperand(i+1).getImm();
 196
 197   if (MI.getOpcode() == MSP430::ADD16ri) {
 198     // This is actually "load effective address" of the stack slot
 199     // instruction. We have only two-address instructions, thus we need to
 200     // expand it into mov + add
 201
 202     MI.setDesc(TII.get(MSP430::MOV16rr));
 203     MI.getOperand(i).ChangeToRegister(BasePtr, false);
 204
 205     if (Offset == 0)
 206       return;
 207
 208     // We need to materialize the offset via add instruction.
 209     unsigned DstReg = MI.getOperand(0).getReg();
 210     if (Offset < 0)
 211       BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
 212         .addReg(DstReg).addImm(-Offset);
 213     else
 214       BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
 215         .addReg(DstReg).addImm(Offset);
 216
 217     return;
 218   }
 219
 220   MI.getOperand(i).ChangeToRegister(BasePtr, false);
 221   MI.getOperand(i+1).ChangeToImmediate(Offset);
 222 }
 223
 224 void
 225 MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
 226                                                                          const {
 227   // Create a frame entry for the FPW register that must be saved.
 228   if (hasFP(MF)) {
 229     int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4, true);
 230     (void)FrameIdx;
 231     assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
 232            "Slot for FPW register must be last in order to be found!");
 233   }
 234 }
 235
 236
 237 void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const {
 238   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
 239   MachineFrameInfo *MFI = MF.getFrameInfo();
 240   MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
 241   MachineBasicBlock::iterator MBBI = MBB.begin();
 242   DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
 243
 244   // Get the number of bytes to allocate from the FrameInfo.
 245   uint64_t StackSize = MFI->getStackSize();
 246
 247   uint64_t NumBytes = 0;
 248   if (hasFP(MF)) {
 249     // Calculate required stack adjustment
 250     uint64_t FrameSize = StackSize - 2;
 251     NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize();
 252
 253     // Get the offset of the stack slot for the EBP register... which is
 254     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
 255     // Update the frame offset adjustment.
 256     MFI->setOffsetAdjustment(-NumBytes);
 257
 258     // Save FPW into the appropriate stack slot...
 259     BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
 260       .addReg(MSP430::FPW, RegState::Kill);
 261
 262     // Update FPW with the new base value...
 263     BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
 264       .addReg(MSP430::SPW);
 265
 266     // Mark the FramePtr as live-in in every block except the entry.
 267     for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
 268          I != E; ++I)
 269       I->addLiveIn(MSP430::FPW);
 270
 271   } else
 272     NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
 273
 274   // Skip the callee-saved push instructions.
 275   while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
 276     ++MBBI;
 277
 278   if (MBBI != MBB.end())
 279     DL = MBBI->getDebugLoc();
 280
 281   if (NumBytes) { // adjust stack pointer: SPW -= numbytes
 282     // If there is an SUB16ri of SPW immediately before this instruction, merge
 283     // the two.
 284     //NumBytes -= mergeSPUpdates(MBB, MBBI, true);
 285     // If there is an ADD16ri or SUB16ri of SPW immediately after this
 286     // instruction, merge the two instructions.
 287     // mergeSPUpdatesDown(MBB, MBBI, &NumBytes);
 288
 289     if (NumBytes) {
 290       MachineInstr *MI =
 291         BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
 292         .addReg(MSP430::SPW).addImm(NumBytes);
 293       // The SRW implicit def is dead.
 294       MI->getOperand(3).setIsDead();
 295     }
 296   }
 297 }
 298
 299 void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF,
 300                                       MachineBasicBlock &MBB) const {
 301   const MachineFrameInfo *MFI = MF.getFrameInfo();
 302   MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
 303   MachineBasicBlock::iterator MBBI = prior(MBB.end());
 304   unsigned RetOpcode = MBBI->getOpcode();
 305   DebugLoc DL = MBBI->getDebugLoc();
 306
 307   switch (RetOpcode) {
 308   case MSP430::RET:
 309   case MSP430::RETI: break;  // These are ok
 310   default:
 311     llvm_unreachable("Can only insert epilog into returning blocks");
 312   }
 313
 314   // Get the number of bytes to allocate from the FrameInfo
 315   uint64_t StackSize = MFI->getStackSize();
 316   unsigned CSSize = MSP430FI->getCalleeSavedFrameSize();
 317   uint64_t NumBytes = 0;
 318
 319   if (hasFP(MF)) {
 320     // Calculate required stack adjustment
 321     uint64_t FrameSize = StackSize - 2;
 322     NumBytes = FrameSize - CSSize;
 323
 324     // pop FPW.
 325     BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
 326   } else
 327     NumBytes = StackSize - CSSize;
 328
 329   // Skip the callee-saved pop instructions.
 330   while (MBBI != MBB.begin()) {
 331     MachineBasicBlock::iterator PI = prior(MBBI);
 332     unsigned Opc = PI->getOpcode();
 333     if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator())
 334       break;
 335     --MBBI;
 336   }
 337
 338   DL = MBBI->getDebugLoc();
 339
 340   // If there is an ADD16ri or SUB16ri of SPW immediately before this
 341   // instruction, merge the two instructions.
 342   //if (NumBytes || MFI->hasVarSizedObjects())
 343   //  mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
 344
 345   if (MFI->hasVarSizedObjects()) {
 346     BuildMI(MBB, MBBI, DL,
 347             TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
 348     if (CSSize) {
 349       MachineInstr *MI =
 350         BuildMI(MBB, MBBI, DL,
 351                 TII.get(MSP430::SUB16ri), MSP430::SPW)
 352         .addReg(MSP430::SPW).addImm(CSSize);
 353       // The SRW implicit def is dead.
 354       MI->getOperand(3).setIsDead();
 355     }
 356   } else {
 357     // adjust stack pointer back: SPW += numbytes
 358     if (NumBytes) {
 359       MachineInstr *MI =
 360         BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
 361         .addReg(MSP430::SPW).addImm(NumBytes);
 362       // The SRW implicit def is dead.
 363       MI->getOperand(3).setIsDead();
 364     }
 365   }
 366 }
 367
 368 unsigned MSP430RegisterInfo::getRARegister() const {
 369   return MSP430::PCW;
 370 }
 371
 372 unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
 373   return hasFP(MF) ? MSP430::FPW : MSP430::SPW;
 374 }
 375
 376 int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 377   llvm_unreachable("Not implemented yet!");
 378   return 0;
 379 }
 380
 381 #include "MSP430GenRegisterInfo.inc"