lib/Target/MSP430/MSP430InstrInfo.cpp

   1 //===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "MSP430.h"
  15 #include "MSP430InstrInfo.h"
  16 #include "MSP430MachineFunctionInfo.h"
  17 #include "MSP430TargetMachine.h"
  18 #include "MSP430GenInstrInfo.inc"
  19 #include "llvm/Function.h"
  20 #include "llvm/CodeGen/MachineFrameInfo.h"
  21 #include "llvm/CodeGen/MachineInstrBuilder.h"
  22 #include "llvm/CodeGen/MachineRegisterInfo.h"
  23 #include "llvm/CodeGen/PseudoSourceValue.h"
  24 #include "llvm/Support/ErrorHandling.h"
  25
  26 using namespace llvm;
  27
  28 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
  29   : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
  30     RI(tm, *this), TM(tm) {}
  31
  32 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
  33                                           MachineBasicBlock::iterator MI,
  34                                     unsigned SrcReg, bool isKill, int FrameIdx,
  35                                           const TargetRegisterClass *RC,
  36                                           const TargetRegisterInfo *TRI) const {
  37   DebugLoc DL;
  38   if (MI != MBB.end()) DL = MI->getDebugLoc();
  39   MachineFunction &MF = *MBB.getParent();
  40   MachineFrameInfo &MFI = *MF.getFrameInfo();
  41
  42   MachineMemOperand *MMO =
  43     MF.getMachineMemOperand(
  44               MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
  45                             MachineMemOperand::MOStore,
  46                             MFI.getObjectSize(FrameIdx),
  47                             MFI.getObjectAlignment(FrameIdx));
  48
  49   if (RC == &MSP430::GR16RegClass)
  50     BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
  51       .addFrameIndex(FrameIdx).addImm(0)
  52       .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
  53   else if (RC == &MSP430::GR8RegClass)
  54     BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
  55       .addFrameIndex(FrameIdx).addImm(0)
  56       .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
  57   else
  58     llvm_unreachable("Cannot store this register to stack slot!");
  59 }
  60
  61 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
  62                                            MachineBasicBlock::iterator MI,
  63                                            unsigned DestReg, int FrameIdx,
  64                                            const TargetRegisterClass *RC,
  65                                            const TargetRegisterInfo *TRI) const{
  66   DebugLoc DL;
  67   if (MI != MBB.end()) DL = MI->getDebugLoc();
  68   MachineFunction &MF = *MBB.getParent();
  69   MachineFrameInfo &MFI = *MF.getFrameInfo();
  70
  71   MachineMemOperand *MMO =
  72     MF.getMachineMemOperand(
  73               MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
  74                             MachineMemOperand::MOLoad,
  75                             MFI.getObjectSize(FrameIdx),
  76                             MFI.getObjectAlignment(FrameIdx));
  77
  78   if (RC == &MSP430::GR16RegClass)
  79     BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
  80       .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
  81   else if (RC == &MSP430::GR8RegClass)
  82     BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
  83       .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
  84   else
  85     llvm_unreachable("Cannot store this register to stack slot!");
  86 }
  87
  88 void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
  89                                   MachineBasicBlock::iterator I, DebugLoc DL,
  90                                   unsigned DestReg, unsigned SrcReg,
  91                                   bool KillSrc) const {
  92   unsigned Opc;
  93   if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
  94     Opc = MSP430::MOV16rr;
  95   else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
  96     Opc = MSP430::MOV8rr;
  97   else
  98     llvm_unreachable("Impossible reg-to-reg copy");
  99
 100   BuildMI(MBB, I, DL, get(Opc), DestReg)
 101     .addReg(SrcReg, getKillRegState(KillSrc));
 102 }
 103
 104 bool
 105 MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
 106                                            MachineBasicBlock::iterator MI,
 107                                         const std::vector<CalleeSavedInfo> &CSI,
 108                                           const TargetRegisterInfo *TRI) const {
 109   if (CSI.empty())
 110     return false;
 111
 112   DebugLoc DL;
 113   if (MI != MBB.end()) DL = MI->getDebugLoc();
 114
 115   MachineFunction &MF = *MBB.getParent();
 116   MSP430MachineFunctionInfo *MFI = MF.getInfo<MSP430MachineFunctionInfo>();
 117   MFI->setCalleeSavedFrameSize(CSI.size() * 2);
 118
 119   for (unsigned i = CSI.size(); i != 0; --i) {
 120     unsigned Reg = CSI[i-1].getReg();
 121     // Add the callee-saved register as live-in. It's killed at the spill.
 122     MBB.addLiveIn(Reg);
 123     BuildMI(MBB, MI, DL, get(MSP430::PUSH16r))
 124       .addReg(Reg, RegState::Kill);
 125   }
 126   return true;
 127 }
 128
 129 bool
 130 MSP430InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
 131                                              MachineBasicBlock::iterator MI,
 132                                         const std::vector<CalleeSavedInfo> &CSI,
 133                                           const TargetRegisterInfo *TRI) const {
 134   if (CSI.empty())
 135     return false;
 136
 137   DebugLoc DL;
 138   if (MI != MBB.end()) DL = MI->getDebugLoc();
 139
 140   for (unsigned i = 0, e = CSI.size(); i != e; ++i)
 141     BuildMI(MBB, MI, DL, get(MSP430::POP16r), CSI[i].getReg());
 142
 143   return true;
 144 }
 145
 146 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
 147   MachineBasicBlock::iterator I = MBB.end();
 148   unsigned Count = 0;
 149
 150   while (I != MBB.begin()) {
 151     --I;
 152     if (I->isDebugValue())
 153       continue;
 154     if (I->getOpcode() != MSP430::JMP &&
 155         I->getOpcode() != MSP430::JCC &&
 156         I->getOpcode() != MSP430::Br &&
 157         I->getOpcode() != MSP430::Bm)
 158       break;
 159     // Remove the branch.
 160     I->eraseFromParent();
 161     I = MBB.end();
 162     ++Count;
 163   }
 164
 165   return Count;
 166 }
 167
 168 bool MSP430InstrInfo::
 169 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
 170   assert(Cond.size() == 1 && "Invalid Xbranch condition!");
 171
 172   MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
 173
 174   switch (CC) {
 175   default:
 176     assert(0 && "Invalid branch condition!");
 177     break;
 178   case MSP430CC::COND_E:
 179     CC = MSP430CC::COND_NE;
 180     break;
 181   case MSP430CC::COND_NE:
 182     CC = MSP430CC::COND_E;
 183     break;
 184   case MSP430CC::COND_L:
 185     CC = MSP430CC::COND_GE;
 186     break;
 187   case MSP430CC::COND_GE:
 188     CC = MSP430CC::COND_L;
 189     break;
 190   case MSP430CC::COND_HS:
 191     CC = MSP430CC::COND_LO;
 192     break;
 193   case MSP430CC::COND_LO:
 194     CC = MSP430CC::COND_HS;
 195     break;
 196   }
 197
 198   Cond[0].setImm(CC);
 199   return false;
 200 }
 201
 202 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
 203   const TargetInstrDesc &TID = MI->getDesc();
 204   if (!TID.isTerminator()) return false;
 205
 206   // Conditional branch is a special case.
 207   if (TID.isBranch() && !TID.isBarrier())
 208     return true;
 209   if (!TID.isPredicable())
 210     return true;
 211   return !isPredicated(MI);
 212 }
 213
 214 bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
 215                                     MachineBasicBlock *&TBB,
 216                                     MachineBasicBlock *&FBB,
 217                                     SmallVectorImpl<MachineOperand> &Cond,
 218                                     bool AllowModify) const {
 219   // Start from the bottom of the block and work up, examining the
 220   // terminator instructions.
 221   MachineBasicBlock::iterator I = MBB.end();
 222   while (I != MBB.begin()) {
 223     --I;
 224     if (I->isDebugValue())
 225       continue;
 226
 227     // Working from the bottom, when we see a non-terminator
 228     // instruction, we're done.
 229     if (!isUnpredicatedTerminator(I))
 230       break;
 231
 232     // A terminator that isn't a branch can't easily be handled
 233     // by this analysis.
 234     if (!I->getDesc().isBranch())
 235       return true;
 236
 237     // Cannot handle indirect branches.
 238     if (I->getOpcode() == MSP430::Br ||
 239         I->getOpcode() == MSP430::Bm)
 240       return true;
 241
 242     // Handle unconditional branches.
 243     if (I->getOpcode() == MSP430::JMP) {
 244       if (!AllowModify) {
 245         TBB = I->getOperand(0).getMBB();
 246         continue;
 247       }
 248
 249       // If the block has any instructions after a JMP, delete them.
 250       while (llvm::next(I) != MBB.end())
 251         llvm::next(I)->eraseFromParent();
 252       Cond.clear();
 253       FBB = 0;
 254
 255       // Delete the JMP if it's equivalent to a fall-through.
 256       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
 257         TBB = 0;
 258         I->eraseFromParent();
 259         I = MBB.end();
 260         continue;
 261       }
 262
 263       // TBB is used to indicate the unconditinal destination.
 264       TBB = I->getOperand(0).getMBB();
 265       continue;
 266     }
 267
 268     // Handle conditional branches.
 269     assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
 270     MSP430CC::CondCodes BranchCode =
 271       static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
 272     if (BranchCode == MSP430CC::COND_INVALID)
 273       return true;  // Can't handle weird stuff.
 274
 275     // Working from the bottom, handle the first conditional branch.
 276     if (Cond.empty()) {
 277       FBB = TBB;
 278       TBB = I->getOperand(0).getMBB();
 279       Cond.push_back(MachineOperand::CreateImm(BranchCode));
 280       continue;
 281     }
 282
 283     // Handle subsequent conditional branches. Only handle the case where all
 284     // conditional branches branch to the same destination.
 285     assert(Cond.size() == 1);
 286     assert(TBB);
 287
 288     // Only handle the case where all conditional branches branch to
 289     // the same destination.
 290     if (TBB != I->getOperand(0).getMBB())
 291       return true;
 292
 293     MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
 294     // If the conditions are the same, we can leave them alone.
 295     if (OldBranchCode == BranchCode)
 296       continue;
 297
 298     return true;
 299   }
 300
 301   return false;
 302 }
 303
 304 unsigned
 305 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 306                               MachineBasicBlock *FBB,
 307                               const SmallVectorImpl<MachineOperand> &Cond,
 308                               DebugLoc DL) const {
 309   // Shouldn't be a fall through.
 310   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 311   assert((Cond.size() == 1 || Cond.size() == 0) &&
 312          "MSP430 branch conditions have one component!");
 313
 314   if (Cond.empty()) {
 315     // Unconditional branch?
 316     assert(!FBB && "Unconditional branch with multiple successors!");
 317     BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
 318     return 1;
 319   }
 320
 321   // Conditional branch.
 322   unsigned Count = 0;
 323   BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
 324   ++Count;
 325
 326   if (FBB) {
 327     // Two-way Conditional branch. Insert the second branch.
 328     BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
 329     ++Count;
 330   }
 331   return Count;
 332 }
 333
 334 /// GetInstSize - Return the number of bytes of code the specified
 335 /// instruction may be.  This returns the maximum number of bytes.
 336 ///
 337 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
 338   const TargetInstrDesc &Desc = MI->getDesc();
 339
 340   switch (Desc.TSFlags & MSP430II::SizeMask) {
 341   default:
 342     switch (Desc.getOpcode()) {
 343     default:
 344       assert(0 && "Unknown instruction size!");
 345     case TargetOpcode::PROLOG_LABEL:
 346     case TargetOpcode::EH_LABEL:
 347     case TargetOpcode::IMPLICIT_DEF:
 348     case TargetOpcode::KILL:
 349     case TargetOpcode::DBG_VALUE:
 350       return 0;
 351     case TargetOpcode::INLINEASM: {
 352       const MachineFunction *MF = MI->getParent()->getParent();
 353       const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
 354       return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
 355                                     *MF->getTarget().getMCAsmInfo());
 356     }
 357     }
 358   case MSP430II::SizeSpecial:
 359     switch (MI->getOpcode()) {
 360     default:
 361       assert(0 && "Unknown instruction size!");
 362     case MSP430::SAR8r1c:
 363     case MSP430::SAR16r1c:
 364       return 4;
 365     }
 366   case MSP430II::Size2Bytes:
 367     return 2;
 368   case MSP430II::Size4Bytes:
 369     return 4;
 370   case MSP430II::Size6Bytes:
 371     return 6;
 372   }
 373
 374   return 6;
 375 }