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Use pseudo instructions for 2-register Neon instructions for scalar FP.
[llvm.git] / lib / Target / ARM / ARMExpandPseudoInsts.cpp
blob79ca3fc50e39ff894211f1babdb8931ee4fa5e38
1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
14 //
15 //===----------------------------------------------------------------------===//
16
17 #define DEBUG_TYPE "arm-pseudo"
18 #include "ARM.h"
19 #include "ARMAddressingModes.h"
20 #include "ARMBaseInstrInfo.h"
21 #include "ARMBaseRegisterInfo.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMRegisterInfo.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
30 using namespace llvm;
31
32 namespace {
33 class ARMExpandPseudo : public MachineFunctionPass {
34 public:
35 static char ID;
36 ARMExpandPseudo() : MachineFunctionPass(ID) {}
37
38 const ARMBaseInstrInfo *TII;
39 const TargetRegisterInfo *TRI;
40 const ARMSubtarget *STI;
41
42 virtual bool runOnMachineFunction(MachineFunction &Fn);
43
44 virtual const char *getPassName() const {
45 return "ARM pseudo instruction expansion pass";
46 }
47
48 private:
49 void TransferImpOps(MachineInstr &OldMI,
50 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
51 bool ExpandMBB(MachineBasicBlock &MBB);
52 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
53 void ExpandVST(MachineBasicBlock::iterator &MBBI);
54 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
55 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
56 unsigned Opc, bool IsExt, unsigned NumRegs);
57 void ExpandNeonSFP2(MachineBasicBlock::iterator &MBBI, unsigned Opc);
58 };
59 char ARMExpandPseudo::ID = 0;
60 }
61
62 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
63 /// the instructions created from the expansion.
64 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
65 MachineInstrBuilder &UseMI,
66 MachineInstrBuilder &DefMI) {
67 const TargetInstrDesc &Desc = OldMI.getDesc();
68 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
69 i != e; ++i) {
70 const MachineOperand &MO = OldMI.getOperand(i);
71 assert(MO.isReg() && MO.getReg());
72 if (MO.isUse())
73 UseMI.addOperand(MO);
74 else
75 DefMI.addOperand(MO);
76 }
77 }
78
79 namespace {
80 // Constants for register spacing in NEON load/store instructions.
81 // For quad-register load-lane and store-lane pseudo instructors, the
82 // spacing is initially assumed to be EvenDblSpc, and that is changed to
83 // OddDblSpc depending on the lane number operand.
84 enum NEONRegSpacing {
85 SingleSpc,
86 EvenDblSpc,
87 OddDblSpc
88 };
89
90 // Entries for NEON load/store information table. The table is sorted by
91 // PseudoOpc for fast binary-search lookups.
92 struct NEONLdStTableEntry {
93 unsigned PseudoOpc;
94 unsigned RealOpc;
95 bool IsLoad;
96 bool HasWriteBack;
97 NEONRegSpacing RegSpacing;
98 unsigned char NumRegs; // D registers loaded or stored
99 unsigned char RegElts; // elements per D register; used for lane ops
100
101 // Comparison methods for binary search of the table.
102 bool operator<(const NEONLdStTableEntry &TE) const {
103 return PseudoOpc < TE.PseudoOpc;
104 }
105 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
106 return TE.PseudoOpc < PseudoOpc;
107 }
108 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
109 const NEONLdStTableEntry &TE) {
110 return PseudoOpc < TE.PseudoOpc;
111 }
112 };
113 }
114
115 static const NEONLdStTableEntry NEONLdStTable[] = {
116 { ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, SingleSpc, 2, 4},
117 { ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true, SingleSpc, 2, 4},
118 { ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, SingleSpc, 2, 2},
119 { ARM::VLD1DUPq32Pseudo_UPD, ARM::VLD1DUPq32_UPD, true, true, SingleSpc, 2, 2},
120 { ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, SingleSpc, 2, 8},
121 { ARM::VLD1DUPq8Pseudo_UPD, ARM::VLD1DUPq8_UPD, true, true, SingleSpc, 2, 8},
122
123 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, EvenDblSpc, 1, 4 },
124 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, EvenDblSpc, 1, 4 },
125 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, EvenDblSpc, 1, 2 },
126 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, EvenDblSpc, 1, 2 },
127 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, EvenDblSpc, 1, 8 },
128 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, EvenDblSpc, 1, 8 },
129
130 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 },
131 { ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 },
132 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 },
133 { ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 },
134
135 { ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 },
136 { ARM::VLD1q16Pseudo_UPD, ARM::VLD1q16_UPD, true, true, SingleSpc, 2, 4 },
137 { ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 },
138 { ARM::VLD1q32Pseudo_UPD, ARM::VLD1q32_UPD, true, true, SingleSpc, 2, 2 },
139 { ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 },
140 { ARM::VLD1q64Pseudo_UPD, ARM::VLD1q64_UPD, true, true, SingleSpc, 2, 1 },
141 { ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 },
142 { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 },
143
144 { ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, SingleSpc, 2, 4},
145 { ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true, SingleSpc, 2, 4},
146 { ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, SingleSpc, 2, 2},
147 { ARM::VLD2DUPd32Pseudo_UPD, ARM::VLD2DUPd32_UPD, true, true, SingleSpc, 2, 2},
148 { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, SingleSpc, 2, 8},
149 { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd8_UPD, true, true, SingleSpc, 2, 8},
150
151 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 },
152 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 },
153 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 },
154 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 },
155 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 },
156 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 },
157 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 },
158 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 },
159 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 },
160 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 },
161
162 { ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 },
163 { ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 },
164 { ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 },
165 { ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 },
166 { ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 },
167 { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 },
168
169 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 },
170 { ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 },
171 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 },
172 { ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 },
173 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 },
174 { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 },
175
176 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, SingleSpc, 3, 4},
177 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, SingleSpc, 3, 4},
178 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, SingleSpc, 3, 2},
179 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, SingleSpc, 3, 2},
180 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, SingleSpc, 3, 8},
181 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, SingleSpc, 3, 8},
182
183 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 },
184 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 },
185 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 },
186 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 },
187 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 },
188 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 },
189 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 },
190 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 },
191 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 },
192 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 },
193
194 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 },
195 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 },
196 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 },
197 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 },
198 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 },
199 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 },
200
201 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 },
202 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 },
203 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 },
204 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 },
205 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 },
206 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 },
207
208 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, SingleSpc, 4, 4},
209 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, SingleSpc, 4, 4},
210 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, SingleSpc, 4, 2},
211 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, SingleSpc, 4, 2},
212 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, SingleSpc, 4, 8},
213 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, SingleSpc, 4, 8},
214
215 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 },
216 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 },
217 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 },
218 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 },
219 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 },
220 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 },
221 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 },
222 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 },
223 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 },
224 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 },
225
226 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 },
227 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 },
228 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 },
229 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 },
230 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 },
231 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 },
232
233 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 },
234 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 },
235 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 },
236 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 },
237 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 },
238 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 },
239
240 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, EvenDblSpc, 1, 4 },
241 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,false, true, EvenDblSpc, 1, 4 },
242 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, EvenDblSpc, 1, 2 },
243 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,false, true, EvenDblSpc, 1, 2 },
244 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, EvenDblSpc, 1, 8 },
245 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, EvenDblSpc, 1, 8 },
246
247 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 },
248 { ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 },
249 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 },
250 { ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 },
251
252 { ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 },
253 { ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 },
254 { ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 },
255 { ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 },
256 { ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 },
257 { ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 },
258 { ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 },
259 { ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 },
260
261 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 },
262 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 },
263 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 },
264 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 },
265 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 },
266 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 },
267 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4},
268 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4},
269 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2},
270 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2},
271
272 { ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 },
273 { ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 },
274 { ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 },
275 { ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 },
276 { ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 },
277 { ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 },
278
279 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 },
280 { ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 },
281 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 },
282 { ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 },
283 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 },
284 { ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 },
285
286 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 },
287 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 },
288 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 },
289 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 },
290 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 },
291 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 },
292 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4},
293 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4},
294 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2},
295 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2},
296
297 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 },
298 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 },
299 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 },
300 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 },
301 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 },
302 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 },
303
304 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 },
305 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 },
306 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 },
307 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 },
308 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 },
309 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 },
310
311 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 },
312 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 },
313 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 },
314 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 },
315 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 },
316 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 },
317 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4},
318 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4},
319 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2},
320 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2},
321
322 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 },
323 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 },
324 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 },
325 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 },
326 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 },
327 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 },
328
329 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 },
330 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 },
331 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 },
332 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 },
333 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 },
334 { ARM::VST4q8oddPseudo_UPD , ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 }
335 };
336
337 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
338 /// load or store pseudo instruction.
339 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
340 unsigned NumEntries = array_lengthof(NEONLdStTable);
341
342 #ifndef NDEBUG
343 // Make sure the table is sorted.
344 static bool TableChecked = false;
345 if (!TableChecked) {
346 for (unsigned i = 0; i != NumEntries-1; ++i)
347 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
348 "NEONLdStTable is not sorted!");
349 TableChecked = true;
350 }
351 #endif
352
353 const NEONLdStTableEntry *I =
354 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
355 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
356 return I;
357 return NULL;
358 }
359
360 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
361 /// corresponding to the specified register spacing. Not all of the results
362 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
363 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
364 const TargetRegisterInfo *TRI, unsigned &D0,
365 unsigned &D1, unsigned &D2, unsigned &D3) {
366 if (RegSpc == SingleSpc) {
367 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
368 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
369 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
370 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
371 } else if (RegSpc == EvenDblSpc) {
372 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
373 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
374 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
375 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
376 } else {
377 assert(RegSpc == OddDblSpc && "unknown register spacing");
378 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
379 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
380 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
381 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
382 }
383 }
384
385 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
386 /// operands to real VLD instructions with D register operands.
387 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
388 MachineInstr &MI = *MBBI;
389 MachineBasicBlock &MBB = *MI.getParent();
390
391 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
392 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
393 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
394 unsigned NumRegs = TableEntry->NumRegs;
395
396 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
397 TII->get(TableEntry->RealOpc));
398 unsigned OpIdx = 0;
399
400 bool DstIsDead = MI.getOperand(OpIdx).isDead();
401 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
402 unsigned D0, D1, D2, D3;
403 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
404 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
405 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
406 if (NumRegs > 2)
407 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
408 if (NumRegs > 3)
409 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
410
411 if (TableEntry->HasWriteBack)
412 MIB.addOperand(MI.getOperand(OpIdx++));
413
414 // Copy the addrmode6 operands.
415 MIB.addOperand(MI.getOperand(OpIdx++));
416 MIB.addOperand(MI.getOperand(OpIdx++));
417 // Copy the am6offset operand.
418 if (TableEntry->HasWriteBack)
419 MIB.addOperand(MI.getOperand(OpIdx++));
420
421 // For an instruction writing double-spaced subregs, the pseudo instruction
422 // has an extra operand that is a use of the super-register. Record the
423 // operand index and skip over it.
424 unsigned SrcOpIdx = 0;
425 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
426 SrcOpIdx = OpIdx++;
427
428 // Copy the predicate operands.
429 MIB.addOperand(MI.getOperand(OpIdx++));
430 MIB.addOperand(MI.getOperand(OpIdx++));
431
432 // Copy the super-register source operand used for double-spaced subregs over
433 // to the new instruction as an implicit operand.
434 if (SrcOpIdx != 0) {
435 MachineOperand MO = MI.getOperand(SrcOpIdx);
436 MO.setImplicit(true);
437 MIB.addOperand(MO);
438 }
439 // Add an implicit def for the super-register.
440 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
441 TransferImpOps(MI, MIB, MIB);
442 MI.eraseFromParent();
443 }
444
445 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
446 /// operands to real VST instructions with D register operands.
447 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
448 MachineInstr &MI = *MBBI;
449 MachineBasicBlock &MBB = *MI.getParent();
450
451 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
452 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
453 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
454 unsigned NumRegs = TableEntry->NumRegs;
455
456 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
457 TII->get(TableEntry->RealOpc));
458 unsigned OpIdx = 0;
459 if (TableEntry->HasWriteBack)
460 MIB.addOperand(MI.getOperand(OpIdx++));
461
462 // Copy the addrmode6 operands.
463 MIB.addOperand(MI.getOperand(OpIdx++));
464 MIB.addOperand(MI.getOperand(OpIdx++));
465 // Copy the am6offset operand.
466 if (TableEntry->HasWriteBack)
467 MIB.addOperand(MI.getOperand(OpIdx++));
468
469 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
470 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
471 unsigned D0, D1, D2, D3;
472 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
473 MIB.addReg(D0).addReg(D1);
474 if (NumRegs > 2)
475 MIB.addReg(D2);
476 if (NumRegs > 3)
477 MIB.addReg(D3);
478
479 // Copy the predicate operands.
480 MIB.addOperand(MI.getOperand(OpIdx++));
481 MIB.addOperand(MI.getOperand(OpIdx++));
482
483 if (SrcIsKill)
484 // Add an implicit kill for the super-reg.
485 (*MIB).addRegisterKilled(SrcReg, TRI, true);
486 TransferImpOps(MI, MIB, MIB);
487 MI.eraseFromParent();
488 }
489
490 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
491 /// register operands to real instructions with D register operands.
492 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
493 MachineInstr &MI = *MBBI;
494 MachineBasicBlock &MBB = *MI.getParent();
495
496 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
497 assert(TableEntry && "NEONLdStTable lookup failed");
498 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
499 unsigned NumRegs = TableEntry->NumRegs;
500 unsigned RegElts = TableEntry->RegElts;
501
502 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
503 TII->get(TableEntry->RealOpc));
504 unsigned OpIdx = 0;
505 // The lane operand is always the 3rd from last operand, before the 2
506 // predicate operands.
507 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
508
509 // Adjust the lane and spacing as needed for Q registers.
510 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
511 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
512 RegSpc = OddDblSpc;
513 Lane -= RegElts;
514 }
515 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
516
517 unsigned D0, D1, D2, D3;
518 unsigned DstReg = 0;
519 bool DstIsDead = false;
520 if (TableEntry->IsLoad) {
521 DstIsDead = MI.getOperand(OpIdx).isDead();
522 DstReg = MI.getOperand(OpIdx++).getReg();
523 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
524 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
525 if (NumRegs > 1)
526 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
527 if (NumRegs > 2)
528 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
529 if (NumRegs > 3)
530 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
531 }
532
533 if (TableEntry->HasWriteBack)
534 MIB.addOperand(MI.getOperand(OpIdx++));
535
536 // Copy the addrmode6 operands.
537 MIB.addOperand(MI.getOperand(OpIdx++));
538 MIB.addOperand(MI.getOperand(OpIdx++));
539 // Copy the am6offset operand.
540 if (TableEntry->HasWriteBack)
541 MIB.addOperand(MI.getOperand(OpIdx++));
542
543 // Grab the super-register source.
544 MachineOperand MO = MI.getOperand(OpIdx++);
545 if (!TableEntry->IsLoad)
546 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
547
548 // Add the subregs as sources of the new instruction.
549 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
550 getKillRegState(MO.isKill()));
551 MIB.addReg(D0, SrcFlags);
552 if (NumRegs > 1)
553 MIB.addReg(D1, SrcFlags);
554 if (NumRegs > 2)
555 MIB.addReg(D2, SrcFlags);
556 if (NumRegs > 3)
557 MIB.addReg(D3, SrcFlags);
558
559 // Add the lane number operand.
560 MIB.addImm(Lane);
561 OpIdx += 1;
562
563 // Copy the predicate operands.
564 MIB.addOperand(MI.getOperand(OpIdx++));
565 MIB.addOperand(MI.getOperand(OpIdx++));
566
567 // Copy the super-register source to be an implicit source.
568 MO.setImplicit(true);
569 MIB.addOperand(MO);
570 if (TableEntry->IsLoad)
571 // Add an implicit def for the super-register.
572 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
573 TransferImpOps(MI, MIB, MIB);
574 MI.eraseFromParent();
575 }
576
577 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
578 /// register operands to real instructions with D register operands.
579 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
580 unsigned Opc, bool IsExt, unsigned NumRegs) {
581 MachineInstr &MI = *MBBI;
582 MachineBasicBlock &MBB = *MI.getParent();
583
584 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
585 unsigned OpIdx = 0;
586
587 // Transfer the destination register operand.
588 MIB.addOperand(MI.getOperand(OpIdx++));
589 if (IsExt)
590 MIB.addOperand(MI.getOperand(OpIdx++));
591
592 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
593 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
594 unsigned D0, D1, D2, D3;
595 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
596 MIB.addReg(D0).addReg(D1);
597 if (NumRegs > 2)
598 MIB.addReg(D2);
599 if (NumRegs > 3)
600 MIB.addReg(D3);
601
602 // Copy the other source register operand.
603 MIB.addOperand(MI.getOperand(OpIdx++));
604
605 // Copy the predicate operands.
606 MIB.addOperand(MI.getOperand(OpIdx++));
607 MIB.addOperand(MI.getOperand(OpIdx++));
608
609 if (SrcIsKill)
610 // Add an implicit kill for the super-reg.
611 (*MIB).addRegisterKilled(SrcReg, TRI, true);
612 TransferImpOps(MI, MIB, MIB);
613 MI.eraseFromParent();
614 }
615
616 /// ExpandNeonSFP2 - Translate a 2-register Neon pseudo instruction used for
617 /// scalar floating-point to a real instruction.
618 void ARMExpandPseudo::ExpandNeonSFP2(MachineBasicBlock::iterator &MBBI,
619 unsigned Opc) {
620 MachineInstr &MI = *MBBI;
621 MachineBasicBlock &MBB = *MI.getParent();
622 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
623 MIB.addOperand(MI.getOperand(0)) // destination register
624 .addOperand(MI.getOperand(1)) // source register
625 .addOperand(MI.getOperand(2)) // predicate
626 .addOperand(MI.getOperand(3)); // predicate register
627 TransferImpOps(MI, MIB, MIB);
628 MI.eraseFromParent();
629 }
630
631 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
632 bool Modified = false;
633
634 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
635 while (MBBI != E) {
636 MachineInstr &MI = *MBBI;
637 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
638
639 bool ModifiedOp = true;
640 unsigned Opcode = MI.getOpcode();
641 switch (Opcode) {
642 default:
643 ModifiedOp = false;
644 break;
645
646 case ARM::Int_eh_sjlj_dispatchsetup: {
647 MachineFunction &MF = *MI.getParent()->getParent();
648 const ARMBaseInstrInfo *AII =
649 static_cast<const ARMBaseInstrInfo*>(TII);
650 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
651 // For functions using a base pointer, we rematerialize it (via the frame
652 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
653 // for us. Otherwise, expand to nothing.
654 if (RI.hasBasePointer(MF)) {
655 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
656 int32_t NumBytes = AFI->getFramePtrSpillOffset();
657 unsigned FramePtr = RI.getFrameRegister(MF);
658 assert(MF.getTarget().getFrameInfo()->hasFP(MF) &&
659 "base pointer without frame pointer?");
660
661 if (AFI->isThumb2Function()) {
662 llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
663 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
664 } else if (AFI->isThumbFunction()) {
665 llvm::emitThumbRegPlusImmediate(MBB, MBBI, ARM::R6,
666 FramePtr, -NumBytes,
667 *TII, RI, MI.getDebugLoc());
668 } else {
669 llvm::emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
670 FramePtr, -NumBytes, ARMCC::AL, 0,
671 *TII);
672 }
673 // If there's dynamic realignment, adjust for it.
674 if (RI.needsStackRealignment(MF)) {
675 MachineFrameInfo *MFI = MF.getFrameInfo();
676 unsigned MaxAlign = MFI->getMaxAlignment();
677 assert (!AFI->isThumb1OnlyFunction());
678 // Emit bic r6, r6, MaxAlign
679 unsigned bicOpc = AFI->isThumbFunction() ?
680 ARM::t2BICri : ARM::BICri;
681 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
682 TII->get(bicOpc), ARM::R6)
683 .addReg(ARM::R6, RegState::Kill)
684 .addImm(MaxAlign-1)));
685 }
686
687 }
688 MI.eraseFromParent();
689 break;
690 }
691
692 case ARM::MOVsrl_flag:
693 case ARM::MOVsra_flag: {
694 // These are just fancy MOVs insructions.
695 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
696 MI.getOperand(0).getReg())
697 .addOperand(MI.getOperand(1))
698 .addReg(0)
699 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr
700 : ARM_AM::asr), 1)))
701 .addReg(ARM::CPSR, RegState::Define);
702 MI.eraseFromParent();
703 break;
704 }
705 case ARM::RRX: {
706 // This encodes as "MOVs Rd, Rm, rrx
707 MachineInstrBuilder MIB =
708 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
709 MI.getOperand(0).getReg())
710 .addOperand(MI.getOperand(1))
711 .addOperand(MI.getOperand(1))
712 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
713 .addReg(0);
714 TransferImpOps(MI, MIB, MIB);
715 MI.eraseFromParent();
716 break;
717 }
718 case ARM::TPsoft: {
719 MachineInstrBuilder MIB =
720 BuildMI(MBB, MBBI, MI.getDebugLoc(),
721 TII->get(ARM::BL))
722 .addExternalSymbol("__aeabi_read_tp", 0);
723
724 (*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
725 TransferImpOps(MI, MIB, MIB);
726 MI.eraseFromParent();
727 break;
728 }
729 case ARM::t2LDRHpci:
730 case ARM::t2LDRBpci:
731 case ARM::t2LDRSHpci:
732 case ARM::t2LDRSBpci:
733 case ARM::t2LDRpci: {
734 unsigned NewLdOpc;
735 if (Opcode == ARM::t2LDRpci)
736 NewLdOpc = ARM::t2LDRi12;
737 else if (Opcode == ARM::t2LDRHpci)
738 NewLdOpc = ARM::t2LDRHi12;
739 else if (Opcode == ARM::t2LDRBpci)
740 NewLdOpc = ARM::t2LDRBi12;
741 else if (Opcode == ARM::t2LDRSHpci)
742 NewLdOpc = ARM::t2LDRSHi12;
743 else if (Opcode == ARM::t2LDRSBpci)
744 NewLdOpc = ARM::t2LDRSBi12;
745 else
746 llvm_unreachable("Not a known opcode?");
747
748 unsigned DstReg = MI.getOperand(0).getReg();
749 MachineInstrBuilder MIB =
750 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
751 TII->get(NewLdOpc), DstReg)
752 .addReg(ARM::PC)
753 .addOperand(MI.getOperand(1)));
754 (*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
755 TransferImpOps(MI, MIB, MIB);
756 MI.eraseFromParent();
757 break;
758 }
759 case ARM::tLDRpci_pic:
760 case ARM::t2LDRpci_pic: {
761 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
762 ? ARM::tLDRpci : ARM::t2LDRi12;
763 unsigned DstReg = MI.getOperand(0).getReg();
764 bool DstIsDead = MI.getOperand(0).isDead();
765 MachineInstrBuilder MIB1 =
766 BuildMI(MBB, MBBI, MI.getDebugLoc(),
767 TII->get(NewLdOpc), DstReg);
768 if (Opcode == ARM::t2LDRpci_pic) MIB1.addReg(ARM::PC);
769 MIB1.addOperand(MI.getOperand(1));
770 AddDefaultPred(MIB1);
771 (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
772 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
773 TII->get(ARM::tPICADD))
774 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
775 .addReg(DstReg)
776 .addOperand(MI.getOperand(2));
777 TransferImpOps(MI, MIB1, MIB2);
778 MI.eraseFromParent();
779 break;
780 }
781
782 case ARM::MOVi32imm:
783 case ARM::MOVCCi32imm:
784 case ARM::t2MOVi32imm:
785 case ARM::t2MOVCCi32imm: {
786 unsigned PredReg = 0;
787 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
788 unsigned DstReg = MI.getOperand(0).getReg();
789 bool DstIsDead = MI.getOperand(0).isDead();
790 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
791 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
792 MachineInstrBuilder LO16, HI16;
793
794 if (!STI->hasV6T2Ops() &&
795 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
796 // Expand into a movi + orr.
797 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
798 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
799 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
800 .addReg(DstReg);
801
802 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
803 unsigned ImmVal = (unsigned)MO.getImm();
804 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
805 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
806 LO16 = LO16.addImm(SOImmValV1);
807 HI16 = HI16.addImm(SOImmValV2);
808 (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
809 (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
810 LO16.addImm(Pred).addReg(PredReg).addReg(0);
811 HI16.addImm(Pred).addReg(PredReg).addReg(0);
812 TransferImpOps(MI, LO16, HI16);
813 MI.eraseFromParent();
814 break;
815 }
816
817 bool isThumb =
818 (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm);
819
820 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
821 TII->get(isThumb ? ARM::t2MOVi16 : ARM::MOVi16),
822 DstReg);
823 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
824 TII->get(isThumb ? ARM::t2MOVTi16 : ARM::MOVTi16))
825 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
826 .addReg(DstReg);
827
828 if (MO.isImm()) {
829 unsigned Imm = MO.getImm();
830 unsigned Lo16 = Imm & 0xffff;
831 unsigned Hi16 = (Imm >> 16) & 0xffff;
832 LO16 = LO16.addImm(Lo16);
833 HI16 = HI16.addImm(Hi16);
834 } else {
835 const GlobalValue *GV = MO.getGlobal();
836 unsigned TF = MO.getTargetFlags();
837 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
838 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
839 }
840 (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
841 (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
842 LO16.addImm(Pred).addReg(PredReg);
843 HI16.addImm(Pred).addReg(PredReg);
844 TransferImpOps(MI, LO16, HI16);
845 MI.eraseFromParent();
846 break;
847 }
848
849 case ARM::VMOVQQ: {
850 unsigned DstReg = MI.getOperand(0).getReg();
851 bool DstIsDead = MI.getOperand(0).isDead();
852 unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0);
853 unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1);
854 unsigned SrcReg = MI.getOperand(1).getReg();
855 bool SrcIsKill = MI.getOperand(1).isKill();
856 unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0);
857 unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1);
858 MachineInstrBuilder Even =
859 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
860 TII->get(ARM::VMOVQ))
861 .addReg(EvenDst,
862 RegState::Define | getDeadRegState(DstIsDead))
863 .addReg(EvenSrc, getKillRegState(SrcIsKill)));
864 MachineInstrBuilder Odd =
865 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
866 TII->get(ARM::VMOVQ))
867 .addReg(OddDst,
868 RegState::Define | getDeadRegState(DstIsDead))
869 .addReg(OddSrc, getKillRegState(SrcIsKill)));
870 TransferImpOps(MI, Even, Odd);
871 MI.eraseFromParent();
872 break;
873 }
874
875 case ARM::VLDMQIA:
876 case ARM::VLDMQDB: {
877 unsigned NewOpc = (Opcode == ARM::VLDMQIA) ? ARM::VLDMDIA : ARM::VLDMDDB;
878 MachineInstrBuilder MIB =
879 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
880 unsigned OpIdx = 0;
881
882 // Grab the Q register destination.
883 bool DstIsDead = MI.getOperand(OpIdx).isDead();
884 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
885
886 // Copy the source register.
887 MIB.addOperand(MI.getOperand(OpIdx++));
888
889 // Copy the predicate operands.
890 MIB.addOperand(MI.getOperand(OpIdx++));
891 MIB.addOperand(MI.getOperand(OpIdx++));
892
893 // Add the destination operands (D subregs).
894 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
895 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
896 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
897 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
898
899 // Add an implicit def for the super-register.
900 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
901 TransferImpOps(MI, MIB, MIB);
902 MI.eraseFromParent();
903 break;
904 }
905
906 case ARM::VSTMQIA:
907 case ARM::VSTMQDB: {
908 unsigned NewOpc = (Opcode == ARM::VSTMQIA) ? ARM::VSTMDIA : ARM::VSTMDDB;
909 MachineInstrBuilder MIB =
910 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
911 unsigned OpIdx = 0;
912
913 // Grab the Q register source.
914 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
915 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
916
917 // Copy the destination register.
918 MIB.addOperand(MI.getOperand(OpIdx++));
919
920 // Copy the predicate operands.
921 MIB.addOperand(MI.getOperand(OpIdx++));
922 MIB.addOperand(MI.getOperand(OpIdx++));
923
924 // Add the source operands (D subregs).
925 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
926 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
927 MIB.addReg(D0).addReg(D1);
928
929 if (SrcIsKill)
930 // Add an implicit kill for the Q register.
931 (*MIB).addRegisterKilled(SrcReg, TRI, true);
932
933 TransferImpOps(MI, MIB, MIB);
934 MI.eraseFromParent();
935 break;
936 }
937 case ARM::VDUPfqf:
938 case ARM::VDUPfdf:{
939 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLNfq : ARM::VDUPLNfd;
940 MachineInstrBuilder MIB =
941 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
942 unsigned OpIdx = 0;
943 unsigned SrcReg = MI.getOperand(1).getReg();
944 unsigned Lane = getARMRegisterNumbering(SrcReg) & 1;
945 unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
946 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
947 // The lane is [0,1] for the containing DReg superregister.
948 // Copy the dst/src register operands.
949 MIB.addOperand(MI.getOperand(OpIdx++));
950 MIB.addReg(DReg);
951 ++OpIdx;
952 // Add the lane select operand.
953 MIB.addImm(Lane);
954 // Add the predicate operands.
955 MIB.addOperand(MI.getOperand(OpIdx++));
956 MIB.addOperand(MI.getOperand(OpIdx++));
957
958 TransferImpOps(MI, MIB, MIB);
959 MI.eraseFromParent();
960 break;
961 }
962
963 case ARM::VLD1q8Pseudo:
964 case ARM::VLD1q16Pseudo:
965 case ARM::VLD1q32Pseudo:
966 case ARM::VLD1q64Pseudo:
967 case ARM::VLD1q8Pseudo_UPD:
968 case ARM::VLD1q16Pseudo_UPD:
969 case ARM::VLD1q32Pseudo_UPD:
970 case ARM::VLD1q64Pseudo_UPD:
971 case ARM::VLD2d8Pseudo:
972 case ARM::VLD2d16Pseudo:
973 case ARM::VLD2d32Pseudo:
974 case ARM::VLD2q8Pseudo:
975 case ARM::VLD2q16Pseudo:
976 case ARM::VLD2q32Pseudo:
977 case ARM::VLD2d8Pseudo_UPD:
978 case ARM::VLD2d16Pseudo_UPD:
979 case ARM::VLD2d32Pseudo_UPD:
980 case ARM::VLD2q8Pseudo_UPD:
981 case ARM::VLD2q16Pseudo_UPD:
982 case ARM::VLD2q32Pseudo_UPD:
983 case ARM::VLD3d8Pseudo:
984 case ARM::VLD3d16Pseudo:
985 case ARM::VLD3d32Pseudo:
986 case ARM::VLD1d64TPseudo:
987 case ARM::VLD3d8Pseudo_UPD:
988 case ARM::VLD3d16Pseudo_UPD:
989 case ARM::VLD3d32Pseudo_UPD:
990 case ARM::VLD1d64TPseudo_UPD:
991 case ARM::VLD3q8Pseudo_UPD:
992 case ARM::VLD3q16Pseudo_UPD:
993 case ARM::VLD3q32Pseudo_UPD:
994 case ARM::VLD3q8oddPseudo_UPD:
995 case ARM::VLD3q16oddPseudo_UPD:
996 case ARM::VLD3q32oddPseudo_UPD:
997 case ARM::VLD4d8Pseudo:
998 case ARM::VLD4d16Pseudo:
999 case ARM::VLD4d32Pseudo:
1000 case ARM::VLD1d64QPseudo:
1001 case ARM::VLD4d8Pseudo_UPD:
1002 case ARM::VLD4d16Pseudo_UPD:
1003 case ARM::VLD4d32Pseudo_UPD:
1004 case ARM::VLD1d64QPseudo_UPD:
1005 case ARM::VLD4q8Pseudo_UPD:
1006 case ARM::VLD4q16Pseudo_UPD:
1007 case ARM::VLD4q32Pseudo_UPD:
1008 case ARM::VLD4q8oddPseudo_UPD:
1009 case ARM::VLD4q16oddPseudo_UPD:
1010 case ARM::VLD4q32oddPseudo_UPD:
1011 case ARM::VLD1DUPq8Pseudo:
1012 case ARM::VLD1DUPq16Pseudo:
1013 case ARM::VLD1DUPq32Pseudo:
1014 case ARM::VLD1DUPq8Pseudo_UPD:
1015 case ARM::VLD1DUPq16Pseudo_UPD:
1016 case ARM::VLD1DUPq32Pseudo_UPD:
1017 case ARM::VLD2DUPd8Pseudo:
1018 case ARM::VLD2DUPd16Pseudo:
1019 case ARM::VLD2DUPd32Pseudo:
1020 case ARM::VLD2DUPd8Pseudo_UPD:
1021 case ARM::VLD2DUPd16Pseudo_UPD:
1022 case ARM::VLD2DUPd32Pseudo_UPD:
1023 case ARM::VLD3DUPd8Pseudo:
1024 case ARM::VLD3DUPd16Pseudo:
1025 case ARM::VLD3DUPd32Pseudo:
1026 case ARM::VLD3DUPd8Pseudo_UPD:
1027 case ARM::VLD3DUPd16Pseudo_UPD:
1028 case ARM::VLD3DUPd32Pseudo_UPD:
1029 case ARM::VLD4DUPd8Pseudo:
1030 case ARM::VLD4DUPd16Pseudo:
1031 case ARM::VLD4DUPd32Pseudo:
1032 case ARM::VLD4DUPd8Pseudo_UPD:
1033 case ARM::VLD4DUPd16Pseudo_UPD:
1034 case ARM::VLD4DUPd32Pseudo_UPD:
1035 ExpandVLD(MBBI);
1036 break;
1037
1038 case ARM::VST1q8Pseudo:
1039 case ARM::VST1q16Pseudo:
1040 case ARM::VST1q32Pseudo:
1041 case ARM::VST1q64Pseudo:
1042 case ARM::VST1q8Pseudo_UPD:
1043 case ARM::VST1q16Pseudo_UPD:
1044 case ARM::VST1q32Pseudo_UPD:
1045 case ARM::VST1q64Pseudo_UPD:
1046 case ARM::VST2d8Pseudo:
1047 case ARM::VST2d16Pseudo:
1048 case ARM::VST2d32Pseudo:
1049 case ARM::VST2q8Pseudo:
1050 case ARM::VST2q16Pseudo:
1051 case ARM::VST2q32Pseudo:
1052 case ARM::VST2d8Pseudo_UPD:
1053 case ARM::VST2d16Pseudo_UPD:
1054 case ARM::VST2d32Pseudo_UPD:
1055 case ARM::VST2q8Pseudo_UPD:
1056 case ARM::VST2q16Pseudo_UPD:
1057 case ARM::VST2q32Pseudo_UPD:
1058 case ARM::VST3d8Pseudo:
1059 case ARM::VST3d16Pseudo:
1060 case ARM::VST3d32Pseudo:
1061 case ARM::VST1d64TPseudo:
1062 case ARM::VST3d8Pseudo_UPD:
1063 case ARM::VST3d16Pseudo_UPD:
1064 case ARM::VST3d32Pseudo_UPD:
1065 case ARM::VST1d64TPseudo_UPD:
1066 case ARM::VST3q8Pseudo_UPD:
1067 case ARM::VST3q16Pseudo_UPD:
1068 case ARM::VST3q32Pseudo_UPD:
1069 case ARM::VST3q8oddPseudo_UPD:
1070 case ARM::VST3q16oddPseudo_UPD:
1071 case ARM::VST3q32oddPseudo_UPD:
1072 case ARM::VST4d8Pseudo:
1073 case ARM::VST4d16Pseudo:
1074 case ARM::VST4d32Pseudo:
1075 case ARM::VST1d64QPseudo:
1076 case ARM::VST4d8Pseudo_UPD:
1077 case ARM::VST4d16Pseudo_UPD:
1078 case ARM::VST4d32Pseudo_UPD:
1079 case ARM::VST1d64QPseudo_UPD:
1080 case ARM::VST4q8Pseudo_UPD:
1081 case ARM::VST4q16Pseudo_UPD:
1082 case ARM::VST4q32Pseudo_UPD:
1083 case ARM::VST4q8oddPseudo_UPD:
1084 case ARM::VST4q16oddPseudo_UPD:
1085 case ARM::VST4q32oddPseudo_UPD:
1086 ExpandVST(MBBI);
1087 break;
1088
1089 case ARM::VLD1LNq8Pseudo:
1090 case ARM::VLD1LNq16Pseudo:
1091 case ARM::VLD1LNq32Pseudo:
1092 case ARM::VLD1LNq8Pseudo_UPD:
1093 case ARM::VLD1LNq16Pseudo_UPD:
1094 case ARM::VLD1LNq32Pseudo_UPD:
1095 case ARM::VLD2LNd8Pseudo:
1096 case ARM::VLD2LNd16Pseudo:
1097 case ARM::VLD2LNd32Pseudo:
1098 case ARM::VLD2LNq16Pseudo:
1099 case ARM::VLD2LNq32Pseudo:
1100 case ARM::VLD2LNd8Pseudo_UPD:
1101 case ARM::VLD2LNd16Pseudo_UPD:
1102 case ARM::VLD2LNd32Pseudo_UPD:
1103 case ARM::VLD2LNq16Pseudo_UPD:
1104 case ARM::VLD2LNq32Pseudo_UPD:
1105 case ARM::VLD3LNd8Pseudo:
1106 case ARM::VLD3LNd16Pseudo:
1107 case ARM::VLD3LNd32Pseudo:
1108 case ARM::VLD3LNq16Pseudo:
1109 case ARM::VLD3LNq32Pseudo:
1110 case ARM::VLD3LNd8Pseudo_UPD:
1111 case ARM::VLD3LNd16Pseudo_UPD:
1112 case ARM::VLD3LNd32Pseudo_UPD:
1113 case ARM::VLD3LNq16Pseudo_UPD:
1114 case ARM::VLD3LNq32Pseudo_UPD:
1115 case ARM::VLD4LNd8Pseudo:
1116 case ARM::VLD4LNd16Pseudo:
1117 case ARM::VLD4LNd32Pseudo:
1118 case ARM::VLD4LNq16Pseudo:
1119 case ARM::VLD4LNq32Pseudo:
1120 case ARM::VLD4LNd8Pseudo_UPD:
1121 case ARM::VLD4LNd16Pseudo_UPD:
1122 case ARM::VLD4LNd32Pseudo_UPD:
1123 case ARM::VLD4LNq16Pseudo_UPD:
1124 case ARM::VLD4LNq32Pseudo_UPD:
1125 case ARM::VST1LNq8Pseudo:
1126 case ARM::VST1LNq16Pseudo:
1127 case ARM::VST1LNq32Pseudo:
1128 case ARM::VST1LNq8Pseudo_UPD:
1129 case ARM::VST1LNq16Pseudo_UPD:
1130 case ARM::VST1LNq32Pseudo_UPD:
1131 case ARM::VST2LNd8Pseudo:
1132 case ARM::VST2LNd16Pseudo:
1133 case ARM::VST2LNd32Pseudo:
1134 case ARM::VST2LNq16Pseudo:
1135 case ARM::VST2LNq32Pseudo:
1136 case ARM::VST2LNd8Pseudo_UPD:
1137 case ARM::VST2LNd16Pseudo_UPD:
1138 case ARM::VST2LNd32Pseudo_UPD:
1139 case ARM::VST2LNq16Pseudo_UPD:
1140 case ARM::VST2LNq32Pseudo_UPD:
1141 case ARM::VST3LNd8Pseudo:
1142 case ARM::VST3LNd16Pseudo:
1143 case ARM::VST3LNd32Pseudo:
1144 case ARM::VST3LNq16Pseudo:
1145 case ARM::VST3LNq32Pseudo:
1146 case ARM::VST3LNd8Pseudo_UPD:
1147 case ARM::VST3LNd16Pseudo_UPD:
1148 case ARM::VST3LNd32Pseudo_UPD:
1149 case ARM::VST3LNq16Pseudo_UPD:
1150 case ARM::VST3LNq32Pseudo_UPD:
1151 case ARM::VST4LNd8Pseudo:
1152 case ARM::VST4LNd16Pseudo:
1153 case ARM::VST4LNd32Pseudo:
1154 case ARM::VST4LNq16Pseudo:
1155 case ARM::VST4LNq32Pseudo:
1156 case ARM::VST4LNd8Pseudo_UPD:
1157 case ARM::VST4LNd16Pseudo_UPD:
1158 case ARM::VST4LNd32Pseudo_UPD:
1159 case ARM::VST4LNq16Pseudo_UPD:
1160 case ARM::VST4LNq32Pseudo_UPD:
1161 ExpandLaneOp(MBBI);
1162 break;
1163
1164 case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break;
1165 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break;
1166 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break;
1167 case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break;
1168 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break;
1169 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break;
1170
1171 case ARM::VABSfd_sfp: ExpandNeonSFP2(MBBI, ARM::VABSfd); break;
1172 case ARM::VNEGfd_sfp: ExpandNeonSFP2(MBBI, ARM::VNEGfd); break;
1173 case ARM::VCVTf2sd_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTf2sd); break;
1174 case ARM::VCVTf2ud_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTf2ud); break;
1175 case ARM::VCVTs2fd_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTs2fd); break;
1176 case ARM::VCVTu2fd_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTu2fd); break;
1177 }
1178
1179 if (ModifiedOp)
1180 Modified = true;
1181 MBBI = NMBBI;
1182 }
1183
1184 return Modified;
1185 }
1186
1187 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1188 TII = static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
1189 TRI = MF.getTarget().getRegisterInfo();
1190 STI = &MF.getTarget().getSubtarget<ARMSubtarget>();
1191
1192 bool Modified = false;
1193 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1194 ++MFI)
1195 Modified |= ExpandMBB(*MFI);
1196 return Modified;
1197 }
1198
1199 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1200 /// expansion pass.
1201 FunctionPass *llvm::createARMExpandPseudoPass() {
1202 return new ARMExpandPseudo();
1203 }
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