lib/Target/X86/X86FloatingPointRegKill.cpp

   1 //===-- X86FloatingPoint.cpp - FP_REG_KILL inserter -----------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the pass which inserts FP_REG_KILL instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "x86-codegen"
  15 #include "X86.h"
  16 #include "X86InstrInfo.h"
  17 #include "X86Subtarget.h"
  18 #include "llvm/Instructions.h"
  19 #include "llvm/CodeGen/MachineFunctionPass.h"
  20 #include "llvm/CodeGen/MachineInstrBuilder.h"
  21 #include "llvm/CodeGen/MachineRegisterInfo.h"
  22 #include "llvm/CodeGen/Passes.h"
  23 #include "llvm/Target/TargetMachine.h"
  24 #include "llvm/Support/Debug.h"
  25 #include "llvm/Support/CFG.h"
  26 #include "llvm/ADT/Statistic.h"
  27 using namespace llvm;
  28
  29 STATISTIC(NumFPKill, "Number of FP_REG_KILL instructions added");
  30
  31 namespace {
  32   struct FPRegKiller : public MachineFunctionPass {
  33     static char ID;
  34     FPRegKiller() : MachineFunctionPass(&ID) {}
  35
  36     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
  37       AU.setPreservesCFG();
  38       AU.addPreservedID(MachineLoopInfoID);
  39       AU.addPreservedID(MachineDominatorsID);
  40       MachineFunctionPass::getAnalysisUsage(AU);
  41     }
  42
  43     virtual bool runOnMachineFunction(MachineFunction &MF);
  44
  45     virtual const char *getPassName() const { return "X86 FP_REG_KILL inserter"; }
  46   };
  47   char FPRegKiller::ID = 0;
  48 }
  49
  50 FunctionPass *llvm::createX87FPRegKillInserterPass() { return new FPRegKiller(); }
  51
  52 bool FPRegKiller::runOnMachineFunction(MachineFunction &MF) {
  53   // If we are emitting FP stack code, scan the basic block to determine if this
  54   // block defines any FP values.  If so, put an FP_REG_KILL instruction before
  55   // the terminator of the block.
  56
  57   // Note that FP stack instructions are used in all modes for long double,
  58   // so we always need to do this check.
  59   // Also note that it's possible for an FP stack register to be live across
  60   // an instruction that produces multiple basic blocks (SSE CMOV) so we
  61   // must check all the generated basic blocks.
  62
  63   // Scan all of the machine instructions in these MBBs, checking for FP
  64   // stores.  (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.)
  65
  66   // Fast-path: If nothing is using the x87 registers, we don't need to do
  67   // any scanning.
  68   MachineRegisterInfo &MRI = MF.getRegInfo();
  69   if (MRI.getRegClassVirtRegs(X86::RFP80RegisterClass).empty() &&
  70       MRI.getRegClassVirtRegs(X86::RFP64RegisterClass).empty() &&
  71       MRI.getRegClassVirtRegs(X86::RFP32RegisterClass).empty())
  72     return false;
  73
  74   bool Changed = false;
  75   const X86Subtarget &Subtarget = MF.getTarget().getSubtarget<X86Subtarget>();
  76   MachineFunction::iterator MBBI = MF.begin();
  77   MachineFunction::iterator EndMBB = MF.end();
  78   for (; MBBI != EndMBB; ++MBBI) {
  79     MachineBasicBlock *MBB = MBBI;
  80
  81     // If this block returns, ignore it.  We don't want to insert an FP_REG_KILL
  82     // before the return.
  83     if (!MBB->empty()) {
  84       MachineBasicBlock::iterator EndI = MBB->end();
  85       --EndI;
  86       if (EndI->getDesc().isReturn())
  87         continue;
  88     }
  89
  90     bool ContainsFPCode = false;
  91     for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
  92          !ContainsFPCode && I != E; ++I) {
  93       if (I->getNumOperands() != 0 && I->getOperand(0).isReg()) {
  94         const TargetRegisterClass *clas;
  95         for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
  96           if (I->getOperand(op).isReg() && I->getOperand(op).isDef() &&
  97             TargetRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
  98               ((clas = MRI.getRegClass(I->getOperand(op).getReg())) ==
  99                  X86::RFP32RegisterClass ||
 100                clas == X86::RFP64RegisterClass ||
 101                clas == X86::RFP80RegisterClass)) {
 102             ContainsFPCode = true;
 103             break;
 104           }
 105         }
 106       }
 107     }
 108     // Check PHI nodes in successor blocks.  These PHI's will be lowered to have
 109     // a copy of the input value in this block.  In SSE mode, we only care about
 110     // 80-bit values.
 111     if (!ContainsFPCode) {
 112       // Final check, check LLVM BB's that are successors to the LLVM BB
 113       // corresponding to BB for FP PHI nodes.
 114       const BasicBlock *LLVMBB = MBB->getBasicBlock();
 115       const PHINode *PN;
 116       for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
 117            !ContainsFPCode && SI != E; ++SI) {
 118         for (BasicBlock::const_iterator II = SI->begin();
 119              (PN = dyn_cast<PHINode>(II)); ++II) {
 120           if (PN->getType()==Type::getX86_FP80Ty(LLVMBB->getContext()) ||
 121               (!Subtarget.hasSSE1() && PN->getType()->isFloatingPoint()) ||
 122               (!Subtarget.hasSSE2() &&
 123                 PN->getType()==Type::getDoubleTy(LLVMBB->getContext()))) {
 124             ContainsFPCode = true;
 125             break;
 126           }
 127         }
 128       }
 129     }
 130     // Finally, if we found any FP code, emit the FP_REG_KILL instruction.
 131     if (ContainsFPCode) {
 132       BuildMI(*MBB, MBBI->getFirstTerminator(), DebugLoc::getUnknownLoc(),
 133               MF.getTarget().getInstrInfo()->get(X86::FP_REG_KILL));
 134       ++NumFPKill;
 135       Changed = true;
 136     }
 137   }
 138
 139   return Changed;
 140 }