lib/CodeGen/LowerSubregs.cpp

   1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a MachineFunction pass which runs after register
  11 // allocation that turns subreg insert/extract instructions into register
  12 // copies, as needed. This ensures correct codegen even if the coalescer
  13 // isn't able to remove all subreg instructions.
  14 //
  15 //===----------------------------------------------------------------------===//
  16
  17 #define DEBUG_TYPE "lowersubregs"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Function.h"
  20 #include "llvm/CodeGen/MachineFunctionPass.h"
  21 #include "llvm/CodeGen/MachineInstr.h"
  22 #include "llvm/CodeGen/MachineInstrBuilder.h"
  23 #include "llvm/CodeGen/MachineRegisterInfo.h"
  24 #include "llvm/Target/TargetRegisterInfo.h"
  25 #include "llvm/Target/TargetInstrInfo.h"
  26 #include "llvm/Target/TargetMachine.h"
  27 #include "llvm/Support/Debug.h"
  28 #include "llvm/Support/raw_ostream.h"
  29 using namespace llvm;
  30
  31 namespace {
  32   struct LowerSubregsInstructionPass : public MachineFunctionPass {
  33     static char ID; // Pass identification, replacement for typeid
  34     LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
  35
  36     const char *getPassName() const {
  37       return "Subregister lowering instruction pass";
  38     }
  39
  40     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
  41       AU.setPreservesCFG();
  42       AU.addPreservedID(MachineLoopInfoID);
  43       AU.addPreservedID(MachineDominatorsID);
  44       MachineFunctionPass::getAnalysisUsage(AU);
  45     }
  46
  47     /// runOnMachineFunction - pass entry point
  48     bool runOnMachineFunction(MachineFunction&);
  49
  50     bool LowerExtract(MachineInstr *MI);
  51     bool LowerInsert(MachineInstr *MI);
  52     bool LowerSubregToReg(MachineInstr *MI);
  53
  54     void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
  55                           const TargetRegisterInfo &TRI);
  56     void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
  57                           const TargetRegisterInfo &TRI,
  58                           bool AddIfNotFound = false);
  59   };
  60
  61   char LowerSubregsInstructionPass::ID = 0;
  62 }
  63
  64 FunctionPass *llvm::createLowerSubregsPass() {
  65   return new LowerSubregsInstructionPass();
  66 }
  67
  68 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
  69 /// and the lowered replacement instructions immediately precede it.
  70 /// Mark the replacement instructions with the dead flag.
  71 void
  72 LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
  73                                               unsigned DstReg,
  74                                               const TargetRegisterInfo &TRI) {
  75   for (MachineBasicBlock::iterator MII =
  76         prior(MachineBasicBlock::iterator(MI)); ; --MII) {
  77     if (MII->addRegisterDead(DstReg, &TRI))
  78       break;
  79     assert(MII != MI->getParent()->begin() &&
  80            "copyRegToReg output doesn't reference destination register!");
  81   }
  82 }
  83
  84 /// TransferKillFlag - MI is a pseudo-instruction with SrcReg killed,
  85 /// and the lowered replacement instructions immediately precede it.
  86 /// Mark the replacement instructions with the kill flag.
  87 void
  88 LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
  89                                               unsigned SrcReg,
  90                                               const TargetRegisterInfo &TRI,
  91                                               bool AddIfNotFound) {
  92   for (MachineBasicBlock::iterator MII =
  93         prior(MachineBasicBlock::iterator(MI)); ; --MII) {
  94     if (MII->addRegisterKilled(SrcReg, &TRI, AddIfNotFound))
  95       break;
  96     assert(MII != MI->getParent()->begin() &&
  97            "copyRegToReg output doesn't reference source register!");
  98   }
  99 }
 100
 101 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
 102   MachineBasicBlock *MBB = MI->getParent();
 103   MachineFunction &MF = *MBB->getParent();
 104   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
 105   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
 106
 107   assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
 108          MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
 109          MI->getOperand(2).isImm() && "Malformed extract_subreg");
 110
 111   unsigned DstReg   = MI->getOperand(0).getReg();
 112   unsigned SuperReg = MI->getOperand(1).getReg();
 113   unsigned SubIdx   = MI->getOperand(2).getImm();
 114   unsigned SrcReg   = TRI.getSubReg(SuperReg, SubIdx);
 115
 116   assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
 117          "Extract supperg source must be a physical register");
 118   assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
 119          "Extract destination must be in a physical register");
 120   assert(SrcReg && "invalid subregister index for register");
 121
 122   DEBUG(errs() << "subreg: CONVERTING: " << *MI);
 123
 124   if (SrcReg == DstReg) {
 125     // No need to insert an identity copy instruction.
 126     if (MI->getOperand(1).isKill()) {
 127       // We must make sure the super-register gets killed. Replace the
 128       // instruction with KILL.
 129       MI->setDesc(TII.get(TargetInstrInfo::KILL));
 130       MI->RemoveOperand(2);     // SubIdx
 131       DEBUG(errs() << "subreg: replace by: " << *MI);
 132       return true;
 133     }
 134
 135     DEBUG(errs() << "subreg: eliminated!");
 136   } else {
 137     // Insert copy
 138     const TargetRegisterClass *TRCS = TRI.getPhysicalRegisterRegClass(DstReg);
 139     const TargetRegisterClass *TRCD = TRI.getPhysicalRegisterRegClass(SrcReg);
 140     bool Emitted = TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS);
 141     (void)Emitted;
 142     assert(Emitted && "Subreg and Dst must be of compatible register class");
 143     // Transfer the kill/dead flags, if needed.
 144     if (MI->getOperand(0).isDead())
 145       TransferDeadFlag(MI, DstReg, TRI);
 146     if (MI->getOperand(1).isKill())
 147       TransferKillFlag(MI, SuperReg, TRI, true);
 148     DEBUG({
 149         MachineBasicBlock::iterator dMI = MI;
 150         errs() << "subreg: " << *(--dMI);
 151       });
 152   }
 153
 154   DEBUG(errs() << '\n');
 155   MBB->erase(MI);
 156   return true;
 157 }
 158
 159 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
 160   MachineBasicBlock *MBB = MI->getParent();
 161   MachineFunction &MF = *MBB->getParent();
 162   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
 163   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
 164   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
 165          MI->getOperand(1).isImm() &&
 166          (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
 167           MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
 168
 169   unsigned DstReg  = MI->getOperand(0).getReg();
 170   unsigned InsReg  = MI->getOperand(2).getReg();
 171   unsigned InsSIdx = MI->getOperand(2).getSubReg();
 172   unsigned SubIdx  = MI->getOperand(3).getImm();
 173
 174   assert(SubIdx != 0 && "Invalid index for insert_subreg");
 175   unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
 176
 177   assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
 178          "Insert destination must be in a physical register");
 179   assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
 180          "Inserted value must be in a physical register");
 181
 182   DEBUG(errs() << "subreg: CONVERTING: " << *MI);
 183
 184   if (DstSubReg == InsReg && InsSIdx == 0) {
 185     // No need to insert an identify copy instruction.
 186     // Watch out for case like this:
 187     // %RAX<def> = ...
 188     // %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
 189     // The first def is defining RAX, not EAX so the top bits were not
 190     // zero extended.
 191     DEBUG(errs() << "subreg: eliminated!");
 192   } else {
 193     // Insert sub-register copy
 194     const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
 195     const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
 196     bool Emitted = TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
 197     (void)Emitted;
 198     assert(Emitted && "Subreg and Dst must be of compatible register class");
 199     // Transfer the kill/dead flags, if needed.
 200     if (MI->getOperand(0).isDead())
 201       TransferDeadFlag(MI, DstSubReg, TRI);
 202     if (MI->getOperand(2).isKill())
 203       TransferKillFlag(MI, InsReg, TRI);
 204     DEBUG({
 205         MachineBasicBlock::iterator dMI = MI;
 206         errs() << "subreg: " << *(--dMI);
 207       });
 208   }
 209
 210   DEBUG(errs() << '\n');
 211   MBB->erase(MI);
 212   return true;
 213 }
 214
 215 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
 216   MachineBasicBlock *MBB = MI->getParent();
 217   MachineFunction &MF = *MBB->getParent();
 218   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
 219   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
 220   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
 221          (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
 222          (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
 223           MI->getOperand(3).isImm() && "Invalid insert_subreg");
 224
 225   unsigned DstReg = MI->getOperand(0).getReg();
 226 #ifndef NDEBUG
 227   unsigned SrcReg = MI->getOperand(1).getReg();
 228 #endif
 229   unsigned InsReg = MI->getOperand(2).getReg();
 230   unsigned SubIdx = MI->getOperand(3).getImm();
 231
 232   assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
 233   assert(SubIdx != 0 && "Invalid index for insert_subreg");
 234   unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
 235   assert(DstSubReg && "invalid subregister index for register");
 236   assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
 237          "Insert superreg source must be in a physical register");
 238   assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
 239          "Inserted value must be in a physical register");
 240
 241   DEBUG(errs() << "subreg: CONVERTING: " << *MI);
 242
 243   if (DstSubReg == InsReg) {
 244     // No need to insert an identity copy instruction. If the SrcReg was
 245     // <undef>, we need to make sure it is alive by inserting a KILL
 246     if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
 247       MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
 248                                 TII.get(TargetInstrInfo::KILL), DstReg);
 249       if (MI->getOperand(2).isUndef())
 250         MIB.addReg(InsReg, RegState::Undef);
 251       else
 252         MIB.addReg(InsReg, RegState::Kill);
 253     } else {
 254       DEBUG(errs() << "subreg: eliminated!\n");
 255       MBB->erase(MI);
 256       return true;
 257     }
 258   } else {
 259     // Insert sub-register copy
 260     const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
 261     const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
 262     if (MI->getOperand(2).isUndef())
 263       // If the source register being inserted is undef, then this becomes a
 264       // KILL.
 265       BuildMI(*MBB, MI, MI->getDebugLoc(),
 266               TII.get(TargetInstrInfo::KILL), DstSubReg);
 267     else {
 268       bool Emitted = TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
 269       (void)Emitted;
 270       assert(Emitted && "Subreg and Dst must be of compatible register class");
 271     }
 272     MachineBasicBlock::iterator CopyMI = MI;
 273     --CopyMI;
 274
 275     // INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
 276     if (!MI->getOperand(1).isUndef())
 277       CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
 278
 279     // Transfer the kill/dead flags, if needed.
 280     if (MI->getOperand(0).isDead()) {
 281       TransferDeadFlag(MI, DstSubReg, TRI);
 282     } else {
 283       // Make sure the full DstReg is live after this replacement.
 284       CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
 285     }
 286
 287     // Make sure the inserted register gets killed
 288     if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef())
 289       TransferKillFlag(MI, InsReg, TRI);
 290   }
 291
 292   DEBUG({
 293       MachineBasicBlock::iterator dMI = MI;
 294       errs() << "subreg: " << *(--dMI) << "\n";
 295     });
 296
 297   MBB->erase(MI);
 298   return true;
 299 }
 300
 301 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
 302 /// copies.
 303 ///
 304 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
 305   DEBUG(errs() << "Machine Function\n"
 306                << "********** LOWERING SUBREG INSTRS **********\n"
 307                << "********** Function: "
 308                << MF.getFunction()->getName() << '\n');
 309
 310   bool MadeChange = false;
 311
 312   for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
 313        mbbi != mbbe; ++mbbi) {
 314     for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
 315          mi != me;) {
 316       MachineInstr *MI = mi++;
 317
 318       if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
 319         MadeChange |= LowerExtract(MI);
 320       } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
 321         MadeChange |= LowerInsert(MI);
 322       } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
 323         MadeChange |= LowerSubregToReg(MI);
 324       }
 325     }
 326   }
 327
 328   return MadeChange;
 329 }