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Move lowering of TLS_addr32 and TLS_addr64 to X86MCInstLower.
[llvm.git] / lib / Target / X86 / X86MCInstLower.cpp
blob3ca87ed877c73d9ddf52028d9db896915874da8b
1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "InstPrinter/X86ATTInstPrinter.h"
16 #include "X86MCInstLower.h"
17 #include "X86AsmPrinter.h"
18 #include "X86COFFMachineModuleInfo.h"
19 #include "X86MCAsmInfo.h"
20 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/Target/Mangler.h"
27 #include "llvm/Support/FormattedStream.h"
28 #include "llvm/ADT/SmallString.h"
29 #include "llvm/Type.h"
30 using namespace llvm;
31
32 X86MCInstLower::X86MCInstLower(Mangler *mang, const MachineFunction &mf,
33 X86AsmPrinter &asmprinter)
34 : Ctx(mf.getContext()), Mang(mang), MF(mf), TM(mf.getTarget()),
35 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
36
37 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
38 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
39 }
40
41
42 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
43 /// operand to an MCSymbol.
44 MCSymbol *X86MCInstLower::
45 GetSymbolFromOperand(const MachineOperand &MO) const {
46 assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference");
47
48 SmallString<128> Name;
49
50 if (!MO.isGlobal()) {
51 assert(MO.isSymbol());
52 Name += MAI.getGlobalPrefix();
53 Name += MO.getSymbolName();
54 } else {
55 const GlobalValue *GV = MO.getGlobal();
56 bool isImplicitlyPrivate = false;
57 if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
58 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
59 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
60 MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
61 isImplicitlyPrivate = true;
62
63 Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
64 }
65
66 // If the target flags on the operand changes the name of the symbol, do that
67 // before we return the symbol.
68 switch (MO.getTargetFlags()) {
69 default: break;
70 case X86II::MO_DLLIMPORT: {
71 // Handle dllimport linkage.
72 const char *Prefix = "__imp_";
73 Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
74 break;
75 }
76 case X86II::MO_DARWIN_NONLAZY:
77 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
78 Name += "$non_lazy_ptr";
79 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
80
81 MachineModuleInfoImpl::StubValueTy &StubSym =
82 getMachOMMI().getGVStubEntry(Sym);
83 if (StubSym.getPointer() == 0) {
84 assert(MO.isGlobal() && "Extern symbol not handled yet");
85 StubSym =
86 MachineModuleInfoImpl::
87 StubValueTy(Mang->getSymbol(MO.getGlobal()),
88 !MO.getGlobal()->hasInternalLinkage());
89 }
90 return Sym;
91 }
92 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
93 Name += "$non_lazy_ptr";
94 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
95 MachineModuleInfoImpl::StubValueTy &StubSym =
96 getMachOMMI().getHiddenGVStubEntry(Sym);
97 if (StubSym.getPointer() == 0) {
98 assert(MO.isGlobal() && "Extern symbol not handled yet");
99 StubSym =
100 MachineModuleInfoImpl::
101 StubValueTy(Mang->getSymbol(MO.getGlobal()),
102 !MO.getGlobal()->hasInternalLinkage());
103 }
104 return Sym;
105 }
106 case X86II::MO_DARWIN_STUB: {
107 Name += "$stub";
108 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
109 MachineModuleInfoImpl::StubValueTy &StubSym =
110 getMachOMMI().getFnStubEntry(Sym);
111 if (StubSym.getPointer())
112 return Sym;
113
114 if (MO.isGlobal()) {
115 StubSym =
116 MachineModuleInfoImpl::
117 StubValueTy(Mang->getSymbol(MO.getGlobal()),
118 !MO.getGlobal()->hasInternalLinkage());
119 } else {
120 Name.erase(Name.end()-5, Name.end());
121 StubSym =
122 MachineModuleInfoImpl::
123 StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
124 }
125 return Sym;
126 }
127 }
128
129 return Ctx.GetOrCreateSymbol(Name.str());
130 }
131
132 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
133 MCSymbol *Sym) const {
134 // FIXME: We would like an efficient form for this, so we don't have to do a
135 // lot of extra uniquing.
136 const MCExpr *Expr = 0;
137 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
138
139 switch (MO.getTargetFlags()) {
140 default: llvm_unreachable("Unknown target flag on GV operand");
141 case X86II::MO_NO_FLAG: // No flag.
142 // These affect the name of the symbol, not any suffix.
143 case X86II::MO_DARWIN_NONLAZY:
144 case X86II::MO_DLLIMPORT:
145 case X86II::MO_DARWIN_STUB:
146 break;
147
148 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
149 case X86II::MO_TLVP_PIC_BASE:
150 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
151 // Subtract the pic base.
152 Expr = MCBinaryExpr::CreateSub(Expr,
153 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
154 Ctx),
155 Ctx);
156 break;
157 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
158 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
159 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
160 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
161 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
162 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
163 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
164 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
165 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
166 case X86II::MO_PIC_BASE_OFFSET:
167 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
168 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
169 Expr = MCSymbolRefExpr::Create(Sym, Ctx);
170 // Subtract the pic base.
171 Expr = MCBinaryExpr::CreateSub(Expr,
172 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
173 Ctx);
174 if (MO.isJTI() && MAI.hasSetDirective()) {
175 // If .set directive is supported, use it to reduce the number of
176 // relocations the assembler will generate for differences between
177 // local labels. This is only safe when the symbols are in the same
178 // section so we are restricting it to jumptable references.
179 MCSymbol *Label = Ctx.CreateTempSymbol();
180 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
181 Expr = MCSymbolRefExpr::Create(Label, Ctx);
182 }
183 break;
184 }
185
186 if (Expr == 0)
187 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
188
189 if (!MO.isJTI() && MO.getOffset())
190 Expr = MCBinaryExpr::CreateAdd(Expr,
191 MCConstantExpr::Create(MO.getOffset(), Ctx),
192 Ctx);
193 return MCOperand::CreateExpr(Expr);
194 }
195
196
197
198 static void lower_subreg32(MCInst *MI, unsigned OpNo) {
199 // Convert registers in the addr mode according to subreg32.
200 unsigned Reg = MI->getOperand(OpNo).getReg();
201 if (Reg != 0)
202 MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
203 }
204
205 static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
206 // Convert registers in the addr mode according to subreg64.
207 for (unsigned i = 0; i != 4; ++i) {
208 if (!MI->getOperand(OpNo+i).isReg()) continue;
209
210 unsigned Reg = MI->getOperand(OpNo+i).getReg();
211 if (Reg == 0) continue;
212
213 MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
214 }
215 }
216
217 /// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8.
218 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
219 OutMI.setOpcode(NewOpc);
220 lower_subreg32(&OutMI, 0);
221 }
222 /// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
223 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
224 OutMI.setOpcode(NewOpc);
225 OutMI.addOperand(OutMI.getOperand(0));
226 OutMI.addOperand(OutMI.getOperand(0));
227 }
228
229 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
230 /// a short fixed-register form.
231 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
232 unsigned ImmOp = Inst.getNumOperands() - 1;
233 assert(Inst.getOperand(0).isReg() && Inst.getOperand(ImmOp).isImm() &&
234 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
235 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
236 Inst.getNumOperands() == 2) && "Unexpected instruction!");
237
238 // Check whether the destination register can be fixed.
239 unsigned Reg = Inst.getOperand(0).getReg();
240 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
241 return;
242
243 // If so, rewrite the instruction.
244 MCOperand Saved = Inst.getOperand(ImmOp);
245 Inst = MCInst();
246 Inst.setOpcode(Opcode);
247 Inst.addOperand(Saved);
248 }
249
250 /// \brief Simplify things like MOV32rm to MOV32o32a.
251 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
252 unsigned Opcode) {
253 // Don't make these simplifications in 64-bit mode; other assemblers don't
254 // perform them because they make the code larger.
255 if (Printer.getSubtarget().is64Bit())
256 return;
257
258 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
259 unsigned AddrBase = IsStore;
260 unsigned RegOp = IsStore ? 0 : 5;
261 unsigned AddrOp = AddrBase + 3;
262 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
263 Inst.getOperand(AddrBase + 0).isReg() && // base
264 Inst.getOperand(AddrBase + 1).isImm() && // scale
265 Inst.getOperand(AddrBase + 2).isReg() && // index register
266 (Inst.getOperand(AddrOp).isExpr() || // address
267 Inst.getOperand(AddrOp).isImm())&&
268 Inst.getOperand(AddrBase + 4).isReg() && // segment
269 "Unexpected instruction!");
270
271 // Check whether the destination register can be fixed.
272 unsigned Reg = Inst.getOperand(RegOp).getReg();
273 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
274 return;
275
276 // Check whether this is an absolute address.
277 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
278 // to do this here.
279 bool Absolute = true;
280 if (Inst.getOperand(AddrOp).isExpr()) {
281 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
282 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
283 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
284 Absolute = false;
285 }
286
287 if (Absolute &&
288 (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
289 Inst.getOperand(AddrBase + 2).getReg() != 0 ||
290 Inst.getOperand(AddrBase + 4).getReg() != 0 ||
291 Inst.getOperand(AddrBase + 1).getImm() != 1))
292 return;
293
294 // If so, rewrite the instruction.
295 MCOperand Saved = Inst.getOperand(AddrOp);
296 Inst = MCInst();
297 Inst.setOpcode(Opcode);
298 Inst.addOperand(Saved);
299 }
300
301 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
302 OutMI.setOpcode(MI->getOpcode());
303
304 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
305 const MachineOperand &MO = MI->getOperand(i);
306
307 MCOperand MCOp;
308 switch (MO.getType()) {
309 default:
310 MI->dump();
311 llvm_unreachable("unknown operand type");
312 case MachineOperand::MO_Register:
313 // Ignore all implicit register operands.
314 if (MO.isImplicit()) continue;
315 MCOp = MCOperand::CreateReg(MO.getReg());
316 break;
317 case MachineOperand::MO_Immediate:
318 MCOp = MCOperand::CreateImm(MO.getImm());
319 break;
320 case MachineOperand::MO_MachineBasicBlock:
321 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
322 MO.getMBB()->getSymbol(), Ctx));
323 break;
324 case MachineOperand::MO_GlobalAddress:
325 case MachineOperand::MO_ExternalSymbol:
326 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
327 break;
328 case MachineOperand::MO_JumpTableIndex:
329 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
330 break;
331 case MachineOperand::MO_ConstantPoolIndex:
332 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
333 break;
334 case MachineOperand::MO_BlockAddress:
335 MCOp = LowerSymbolOperand(MO,
336 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
337 break;
338 }
339
340 OutMI.addOperand(MCOp);
341 }
342
343 // Handle a few special cases to eliminate operand modifiers.
344 ReSimplify:
345 switch (OutMI.getOpcode()) {
346 case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
347 lower_lea64_32mem(&OutMI, 1);
348 // FALL THROUGH.
349 case X86::LEA64r:
350 case X86::LEA16r:
351 case X86::LEA32r:
352 // LEA should have a segment register, but it must be empty.
353 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
354 "Unexpected # of LEA operands");
355 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
356 "LEA has segment specified!");
357 break;
358 case X86::MOVZX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
359 case X86::MOVZX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
360 case X86::MOVSX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rr8); break;
361 case X86::MOVSX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rm8); break;
362 case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
363 case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
364 case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
365 case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
366 case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
367 case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
368 case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
369 case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break;
370 case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break;
371 case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break;
372 case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
373 case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
374 case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
375 case X86::FsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
376 case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
377 case X86::V_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
378 case X86::V_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::XORPDrr); break;
379 case X86::V_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
380 case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
381 case X86::AVX_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::VXORPSrr); break;
382 case X86::AVX_SET0PSY: LowerUnaryToTwoAddr(OutMI, X86::VXORPSYrr); break;
383 case X86::AVX_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::VXORPDrr); break;
384 case X86::AVX_SET0PDY: LowerUnaryToTwoAddr(OutMI, X86::VXORPDYrr); break;
385 case X86::AVX_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break;
386
387 case X86::MOV16r0:
388 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
389 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
390 break;
391 case X86::MOV64r0:
392 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
393 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
394 break;
395
396 // TAILJMPr64, [WIN]CALL64r, [WIN]CALL64pcrel32 - These instructions have
397 // register inputs modeled as normal uses instead of implicit uses. As such,
398 // truncate off all but the first operand (the callee). FIXME: Change isel.
399 case X86::TAILJMPr64:
400 case X86::CALL64r:
401 case X86::CALL64pcrel32:
402 case X86::WINCALL64r:
403 case X86::WINCALL64pcrel32: {
404 unsigned Opcode = OutMI.getOpcode();
405 MCOperand Saved = OutMI.getOperand(0);
406 OutMI = MCInst();
407 OutMI.setOpcode(Opcode);
408 OutMI.addOperand(Saved);
409 break;
410 }
411
412 case X86::EH_RETURN:
413 case X86::EH_RETURN64: {
414 OutMI = MCInst();
415 OutMI.setOpcode(X86::RET);
416 break;
417 }
418
419 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
420 case X86::TAILJMPr:
421 case X86::TAILJMPd:
422 case X86::TAILJMPd64: {
423 unsigned Opcode;
424 switch (OutMI.getOpcode()) {
425 default: assert(0 && "Invalid opcode");
426 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
427 case X86::TAILJMPd:
428 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
429 }
430
431 MCOperand Saved = OutMI.getOperand(0);
432 OutMI = MCInst();
433 OutMI.setOpcode(Opcode);
434 OutMI.addOperand(Saved);
435 break;
436 }
437
438 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
439 // this with an ugly goto in case the resultant OR uses EAX and needs the
440 // short form.
441 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
442 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
443 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
444 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
445 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
446 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
447 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
448 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
449 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
450
451 // The assembler backend wants to see branches in their small form and relax
452 // them to their large form. The JIT can only handle the large form because
453 // it does not do relaxation. For now, translate the large form to the
454 // small one here.
455 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
456 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
457 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
458 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
459 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
460 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
461 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
462 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
463 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
464 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
465 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
466 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
467 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
468 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
469 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
470 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
471 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
472
473 // We don't currently select the correct instruction form for instructions
474 // which have a short %eax, etc. form. Handle this by custom lowering, for
475 // now.
476 //
477 // Note, we are currently not handling the following instructions:
478 // MOV64ao8, MOV64o8a
479 // XCHG16ar, XCHG32ar, XCHG64ar
480 case X86::MOV8mr_NOREX:
481 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
482 case X86::MOV8rm_NOREX:
483 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
484 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
485 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
486 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
487 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
488
489 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
490 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
491 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
492 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
493 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
494 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
495 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
496 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
497 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
498 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
499 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
500 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
501 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
502 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
503 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
504 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
505 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
506 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
507 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
508 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
509 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
510 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
511 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
512 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
513 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
514 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
515 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
516 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
517 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
518 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
519 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
520 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
521 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
522 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
523 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
524 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
525 }
526 }
527
528 static void LowerTlsAddr(MCStreamer &OutStreamer,
529 X86MCInstLower &MCInstLowering,
530 const MachineInstr &MI) {
531 bool is64Bits = MI.getOpcode() == X86::TLS_addr64;
532 MCContext &context = OutStreamer.getContext();
533
534 if (is64Bits) {
535 MCInst prefix;
536 prefix.setOpcode(X86::DATA16_PREFIX);
537 OutStreamer.EmitInstruction(prefix);
538 }
539 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
540 const MCSymbolRefExpr *symRef =
541 MCSymbolRefExpr::Create(sym, MCSymbolRefExpr::VK_TLSGD, context);
542
543 MCInst LEA;
544 if (is64Bits) {
545 LEA.setOpcode(X86::LEA64r);
546 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
547 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
548 LEA.addOperand(MCOperand::CreateImm(1)); // scale
549 LEA.addOperand(MCOperand::CreateReg(0)); // index
550 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
551 LEA.addOperand(MCOperand::CreateReg(0)); // seg
552 } else {
553 LEA.setOpcode(X86::LEA32r);
554 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
555 LEA.addOperand(MCOperand::CreateReg(0)); // base
556 LEA.addOperand(MCOperand::CreateImm(1)); // scale
557 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
558 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
559 LEA.addOperand(MCOperand::CreateReg(0)); // seg
560 }
561 OutStreamer.EmitInstruction(LEA);
562
563 if (is64Bits) {
564 MCInst prefix;
565 prefix.setOpcode(X86::DATA16_PREFIX);
566 OutStreamer.EmitInstruction(prefix);
567 prefix.setOpcode(X86::DATA16_PREFIX);
568 OutStreamer.EmitInstruction(prefix);
569 prefix.setOpcode(X86::REX64_PREFIX);
570 OutStreamer.EmitInstruction(prefix);
571 }
572
573 MCInst call;
574 if (is64Bits)
575 call.setOpcode(X86::CALL64pcrel32);
576 else
577 call.setOpcode(X86::CALLpcrel32);
578 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
579 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
580 const MCSymbolRefExpr *tlsRef =
581 MCSymbolRefExpr::Create(tlsGetAddr,
582 MCSymbolRefExpr::VK_PLT,
583 context);
584
585 call.addOperand(MCOperand::CreateExpr(tlsRef));
586 OutStreamer.EmitInstruction(call);
587 }
588
589 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
590 X86MCInstLower MCInstLowering(Mang, *MF, *this);
591 switch (MI->getOpcode()) {
592 case TargetOpcode::DBG_VALUE:
593 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
594 std::string TmpStr;
595 raw_string_ostream OS(TmpStr);
596 PrintDebugValueComment(MI, OS);
597 OutStreamer.EmitRawText(StringRef(OS.str()));
598 }
599 return;
600
601 // Emit nothing here but a comment if we can.
602 case X86::Int_MemBarrier:
603 if (OutStreamer.hasRawTextSupport())
604 OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER"));
605 return;
606
607
608 case X86::EH_RETURN:
609 case X86::EH_RETURN64: {
610 // Lower these as normal, but add some comments.
611 unsigned Reg = MI->getOperand(0).getReg();
612 OutStreamer.AddComment(StringRef("eh_return, addr: %") +
613 X86ATTInstPrinter::getRegisterName(Reg));
614 break;
615 }
616 case X86::TAILJMPr:
617 case X86::TAILJMPd:
618 case X86::TAILJMPd64:
619 // Lower these as normal, but add some comments.
620 OutStreamer.AddComment("TAILCALL");
621 break;
622
623 case X86::TLS_addr32:
624 case X86::TLS_addr64:
625 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI);
626
627 case X86::MOVPC32r: {
628 MCInst TmpInst;
629 // This is a pseudo op for a two instruction sequence with a label, which
630 // looks like:
631 // call "L1$pb"
632 // "L1$pb":
633 // popl %esi
634
635 // Emit the call.
636 MCSymbol *PICBase = MF->getPICBaseSymbol();
637 TmpInst.setOpcode(X86::CALLpcrel32);
638 // FIXME: We would like an efficient form for this, so we don't have to do a
639 // lot of extra uniquing.
640 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
641 OutContext)));
642 OutStreamer.EmitInstruction(TmpInst);
643
644 // Emit the label.
645 OutStreamer.EmitLabel(PICBase);
646
647 // popl $reg
648 TmpInst.setOpcode(X86::POP32r);
649 TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
650 OutStreamer.EmitInstruction(TmpInst);
651 return;
652 }
653
654 case X86::ADD32ri: {
655 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
656 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
657 break;
658
659 // Okay, we have something like:
660 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
661
662 // For this, we want to print something like:
663 // MYGLOBAL + (. - PICBASE)
664 // However, we can't generate a ".", so just emit a new label here and refer
665 // to it.
666 MCSymbol *DotSym = OutContext.CreateTempSymbol();
667 OutStreamer.EmitLabel(DotSym);
668
669 // Now that we have emitted the label, lower the complex operand expression.
670 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
671
672 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
673 const MCExpr *PICBase =
674 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
675 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
676
677 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
678 DotExpr, OutContext);
679
680 MCInst TmpInst;
681 TmpInst.setOpcode(X86::ADD32ri);
682 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
683 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
684 TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
685 OutStreamer.EmitInstruction(TmpInst);
686 return;
687 }
688 }
689
690 MCInst TmpInst;
691 MCInstLowering.Lower(MI, TmpInst);
692 OutStreamer.EmitInstruction(TmpInst);
693 }
694
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