| blob | 67c655391d189a917aece17a10aaaf5749dba5dc |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
3 ; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
4 ; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
5 ; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
7 declare i4 @llvm.ssub.sat.i4(i4, i4)
8 declare i8 @llvm.ssub.sat.i8(i8, i8)
9 declare i16 @llvm.ssub.sat.i16(i16, i16)
10 declare i32 @llvm.ssub.sat.i32(i32, i32)
11 declare i64 @llvm.ssub.sat.i64(i64, i64)
13 define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
14 ; CHECK-T1-LABEL: func32:
15 ; CHECK-T1: @ %bb.0:
16 ; CHECK-T1-NEXT: .save {r4, lr}
17 ; CHECK-T1-NEXT: push {r4, lr}
18 ; CHECK-T1-NEXT: mov r3, r0
19 ; CHECK-T1-NEXT: muls r1, r2, r1
20 ; CHECK-T1-NEXT: movs r2, #1
21 ; CHECK-T1-NEXT: subs r0, r0, r1
22 ; CHECK-T1-NEXT: mov r4, r2
23 ; CHECK-T1-NEXT: bmi .LBB0_2
24 ; CHECK-T1-NEXT: @ %bb.1:
25 ; CHECK-T1-NEXT: movs r4, #0
26 ; CHECK-T1-NEXT: .LBB0_2:
27 ; CHECK-T1-NEXT: cmp r4, #0
28 ; CHECK-T1-NEXT: bne .LBB0_4
29 ; CHECK-T1-NEXT: @ %bb.3:
30 ; CHECK-T1-NEXT: lsls r2, r2, #31
31 ; CHECK-T1-NEXT: cmp r3, r1
32 ; CHECK-T1-NEXT: bvs .LBB0_5
33 ; CHECK-T1-NEXT: b .LBB0_6
34 ; CHECK-T1-NEXT: .LBB0_4:
35 ; CHECK-T1-NEXT: ldr r2, .LCPI0_0
36 ; CHECK-T1-NEXT: cmp r3, r1
37 ; CHECK-T1-NEXT: bvc .LBB0_6
38 ; CHECK-T1-NEXT: .LBB0_5:
39 ; CHECK-T1-NEXT: mov r0, r2
40 ; CHECK-T1-NEXT: .LBB0_6:
41 ; CHECK-T1-NEXT: pop {r4, pc}
42 ; CHECK-T1-NEXT: .p2align 2
43 ; CHECK-T1-NEXT: @ %bb.7:
44 ; CHECK-T1-NEXT: .LCPI0_0:
45 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
46 ;
47 ; CHECK-T2-LABEL: func32:
48 ; CHECK-T2: @ %bb.0:
49 ; CHECK-T2-NEXT: .save {r7, lr}
50 ; CHECK-T2-NEXT: push {r7, lr}
51 ; CHECK-T2-NEXT: mls r12, r1, r2, r0
52 ; CHECK-T2-NEXT: mov.w lr, #0
53 ; CHECK-T2-NEXT: mov.w r3, #-2147483648
54 ; CHECK-T2-NEXT: muls r1, r2, r1
55 ; CHECK-T2-NEXT: cmp.w r12, #0
56 ; CHECK-T2-NEXT: it mi
57 ; CHECK-T2-NEXT: movmi.w lr, #1
58 ; CHECK-T2-NEXT: cmp.w lr, #0
59 ; CHECK-T2-NEXT: it ne
60 ; CHECK-T2-NEXT: mvnne r3, #-2147483648
61 ; CHECK-T2-NEXT: cmp r0, r1
62 ; CHECK-T2-NEXT: it vc
63 ; CHECK-T2-NEXT: movvc r3, r12
64 ; CHECK-T2-NEXT: mov r0, r3
65 ; CHECK-T2-NEXT: pop {r7, pc}
66 ;
67 ; CHECK-ARM-LABEL: func32:
68 ; CHECK-ARM: @ %bb.0:
69 ; CHECK-ARM-NEXT: mls r3, r1, r2, r0
70 ; CHECK-ARM-NEXT: mul r12, r1, r2
71 ; CHECK-ARM-NEXT: mov r2, #0
72 ; CHECK-ARM-NEXT: mov r1, #-2147483648
73 ; CHECK-ARM-NEXT: cmp r3, #0
74 ; CHECK-ARM-NEXT: movwmi r2, #1
75 ; CHECK-ARM-NEXT: cmp r2, #0
76 ; CHECK-ARM-NEXT: mvnne r1, #-2147483648
77 ; CHECK-ARM-NEXT: cmp r0, r12
78 ; CHECK-ARM-NEXT: movvc r1, r3
79 ; CHECK-ARM-NEXT: mov r0, r1
80 ; CHECK-ARM-NEXT: bx lr
81 %a = mul i32 %y, %z
82 %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
83 ret i32 %tmp
84 }
86 define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
87 ; CHECK-T1-LABEL: func64:
88 ; CHECK-T1: @ %bb.0:
89 ; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
90 ; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
91 ; CHECK-T1-NEXT: .pad #4
92 ; CHECK-T1-NEXT: sub sp, #4
93 ; CHECK-T1-NEXT: ldr r5, [sp, #28]
94 ; CHECK-T1-NEXT: movs r2, #1
95 ; CHECK-T1-NEXT: movs r4, #0
96 ; CHECK-T1-NEXT: cmp r5, #0
97 ; CHECK-T1-NEXT: mov r3, r2
98 ; CHECK-T1-NEXT: bge .LBB1_2
99 ; CHECK-T1-NEXT: @ %bb.1:
100 ; CHECK-T1-NEXT: mov r3, r4
101 ; CHECK-T1-NEXT: .LBB1_2:
102 ; CHECK-T1-NEXT: cmp r1, #0
103 ; CHECK-T1-NEXT: mov r6, r2
104 ; CHECK-T1-NEXT: bge .LBB1_4
105 ; CHECK-T1-NEXT: @ %bb.3:
106 ; CHECK-T1-NEXT: mov r6, r4
107 ; CHECK-T1-NEXT: .LBB1_4:
108 ; CHECK-T1-NEXT: subs r3, r6, r3
109 ; CHECK-T1-NEXT: subs r7, r3, #1
110 ; CHECK-T1-NEXT: sbcs r3, r7
111 ; CHECK-T1-NEXT: ldr r7, [sp, #24]
112 ; CHECK-T1-NEXT: subs r0, r0, r7
113 ; CHECK-T1-NEXT: sbcs r1, r5
114 ; CHECK-T1-NEXT: cmp r1, #0
115 ; CHECK-T1-NEXT: mov r5, r2
116 ; CHECK-T1-NEXT: bge .LBB1_6
117 ; CHECK-T1-NEXT: @ %bb.5:
118 ; CHECK-T1-NEXT: mov r5, r4
119 ; CHECK-T1-NEXT: .LBB1_6:
120 ; CHECK-T1-NEXT: subs r4, r6, r5
121 ; CHECK-T1-NEXT: subs r5, r4, #1
122 ; CHECK-T1-NEXT: sbcs r4, r5
123 ; CHECK-T1-NEXT: ands r3, r4
124 ; CHECK-T1-NEXT: beq .LBB1_8
125 ; CHECK-T1-NEXT: @ %bb.7:
126 ; CHECK-T1-NEXT: asrs r0, r1, #31
127 ; CHECK-T1-NEXT: .LBB1_8:
128 ; CHECK-T1-NEXT: cmp r1, #0
129 ; CHECK-T1-NEXT: bmi .LBB1_10
130 ; CHECK-T1-NEXT: @ %bb.9:
131 ; CHECK-T1-NEXT: lsls r2, r2, #31
132 ; CHECK-T1-NEXT: cmp r3, #0
133 ; CHECK-T1-NEXT: beq .LBB1_11
134 ; CHECK-T1-NEXT: b .LBB1_12
135 ; CHECK-T1-NEXT: .LBB1_10:
136 ; CHECK-T1-NEXT: ldr r2, .LCPI1_0
137 ; CHECK-T1-NEXT: cmp r3, #0
138 ; CHECK-T1-NEXT: bne .LBB1_12
139 ; CHECK-T1-NEXT: .LBB1_11:
140 ; CHECK-T1-NEXT: mov r2, r1
141 ; CHECK-T1-NEXT: .LBB1_12:
142 ; CHECK-T1-NEXT: mov r1, r2
143 ; CHECK-T1-NEXT: add sp, #4
144 ; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
145 ; CHECK-T1-NEXT: .p2align 2
146 ; CHECK-T1-NEXT: @ %bb.13:
147 ; CHECK-T1-NEXT: .LCPI1_0:
148 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
149 ;
150 ; CHECK-T2-LABEL: func64:
151 ; CHECK-T2: @ %bb.0:
152 ; CHECK-T2-NEXT: .save {r4, lr}
153 ; CHECK-T2-NEXT: push {r4, lr}
154 ; CHECK-T2-NEXT: ldr.w r12, [sp, #12]
155 ; CHECK-T2-NEXT: movs r2, #0
156 ; CHECK-T2-NEXT: movs r3, #0
157 ; CHECK-T2-NEXT: ldr r4, [sp, #8]
158 ; CHECK-T2-NEXT: cmp.w r12, #-1
159 ; CHECK-T2-NEXT: it gt
160 ; CHECK-T2-NEXT: movgt r2, #1
161 ; CHECK-T2-NEXT: cmp.w r1, #-1
162 ; CHECK-T2-NEXT: it gt
163 ; CHECK-T2-NEXT: movgt r3, #1
164 ; CHECK-T2-NEXT: subs r2, r3, r2
165 ; CHECK-T2-NEXT: mov.w lr, #0
166 ; CHECK-T2-NEXT: it ne
167 ; CHECK-T2-NEXT: movne r2, #1
168 ; CHECK-T2-NEXT: subs r0, r0, r4
169 ; CHECK-T2-NEXT: sbc.w r4, r1, r12
170 ; CHECK-T2-NEXT: cmp.w r4, #-1
171 ; CHECK-T2-NEXT: it gt
172 ; CHECK-T2-NEXT: movgt.w lr, #1
173 ; CHECK-T2-NEXT: subs.w r1, r3, lr
174 ; CHECK-T2-NEXT: it ne
175 ; CHECK-T2-NEXT: movne r1, #1
176 ; CHECK-T2-NEXT: ands r2, r1
177 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
178 ; CHECK-T2-NEXT: it ne
179 ; CHECK-T2-NEXT: asrne r0, r4, #31
180 ; CHECK-T2-NEXT: cmp r4, #0
181 ; CHECK-T2-NEXT: it mi
182 ; CHECK-T2-NEXT: mvnmi r1, #-2147483648
183 ; CHECK-T2-NEXT: cmp r2, #0
184 ; CHECK-T2-NEXT: it eq
185 ; CHECK-T2-NEXT: moveq r1, r4
186 ; CHECK-T2-NEXT: pop {r4, pc}
187 ;
188 ; CHECK-ARM-LABEL: func64:
189 ; CHECK-ARM: @ %bb.0:
190 ; CHECK-ARM-NEXT: .save {r4, r5, r11, lr}
191 ; CHECK-ARM-NEXT: push {r4, r5, r11, lr}
192 ; CHECK-ARM-NEXT: ldr lr, [sp, #20]
193 ; CHECK-ARM-NEXT: cmn r1, #1
194 ; CHECK-ARM-NEXT: mov r3, #0
195 ; CHECK-ARM-NEXT: mov r4, #0
196 ; CHECK-ARM-NEXT: movwgt r3, #1
197 ; CHECK-ARM-NEXT: cmn lr, #1
198 ; CHECK-ARM-NEXT: movwgt r4, #1
199 ; CHECK-ARM-NEXT: ldr r12, [sp, #16]
200 ; CHECK-ARM-NEXT: subs r4, r3, r4
201 ; CHECK-ARM-NEXT: mov r5, #0
202 ; CHECK-ARM-NEXT: movwne r4, #1
203 ; CHECK-ARM-NEXT: subs r0, r0, r12
204 ; CHECK-ARM-NEXT: sbc r2, r1, lr
205 ; CHECK-ARM-NEXT: cmn r2, #1
206 ; CHECK-ARM-NEXT: movwgt r5, #1
207 ; CHECK-ARM-NEXT: subs r1, r3, r5
208 ; CHECK-ARM-NEXT: movwne r1, #1
209 ; CHECK-ARM-NEXT: ands r3, r4, r1
210 ; CHECK-ARM-NEXT: asrne r0, r2, #31
211 ; CHECK-ARM-NEXT: mov r1, #-2147483648
212 ; CHECK-ARM-NEXT: cmp r2, #0
213 ; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
214 ; CHECK-ARM-NEXT: cmp r3, #0
215 ; CHECK-ARM-NEXT: moveq r1, r2
216 ; CHECK-ARM-NEXT: pop {r4, r5, r11, pc}
217 %a = mul i64 %y, %z
218 %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
219 ret i64 %tmp
220 }
222 define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind {
223 ; CHECK-T1-LABEL: func16:
224 ; CHECK-T1: @ %bb.0:
225 ; CHECK-T1-NEXT: .save {r4, lr}
226 ; CHECK-T1-NEXT: push {r4, lr}
227 ; CHECK-T1-NEXT: muls r1, r2, r1
228 ; CHECK-T1-NEXT: lsls r1, r1, #16
229 ; CHECK-T1-NEXT: lsls r2, r0, #16
230 ; CHECK-T1-NEXT: movs r3, #1
231 ; CHECK-T1-NEXT: subs r0, r2, r1
232 ; CHECK-T1-NEXT: mov r4, r3
233 ; CHECK-T1-NEXT: bmi .LBB2_2
234 ; CHECK-T1-NEXT: @ %bb.1:
235 ; CHECK-T1-NEXT: movs r4, #0
236 ; CHECK-T1-NEXT: .LBB2_2:
237 ; CHECK-T1-NEXT: cmp r4, #0
238 ; CHECK-T1-NEXT: bne .LBB2_4
239 ; CHECK-T1-NEXT: @ %bb.3:
240 ; CHECK-T1-NEXT: lsls r3, r3, #31
241 ; CHECK-T1-NEXT: cmp r2, r1
242 ; CHECK-T1-NEXT: bvs .LBB2_5
243 ; CHECK-T1-NEXT: b .LBB2_6
244 ; CHECK-T1-NEXT: .LBB2_4:
245 ; CHECK-T1-NEXT: ldr r3, .LCPI2_0
246 ; CHECK-T1-NEXT: cmp r2, r1
247 ; CHECK-T1-NEXT: bvc .LBB2_6
248 ; CHECK-T1-NEXT: .LBB2_5:
249 ; CHECK-T1-NEXT: mov r0, r3
250 ; CHECK-T1-NEXT: .LBB2_6:
251 ; CHECK-T1-NEXT: asrs r0, r0, #16
252 ; CHECK-T1-NEXT: pop {r4, pc}
253 ; CHECK-T1-NEXT: .p2align 2
254 ; CHECK-T1-NEXT: @ %bb.7:
255 ; CHECK-T1-NEXT: .LCPI2_0:
256 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
257 ;
258 ; CHECK-T2-LABEL: func16:
259 ; CHECK-T2: @ %bb.0:
260 ; CHECK-T2-NEXT: mul r12, r1, r2
261 ; CHECK-T2-NEXT: lsls r0, r0, #16
262 ; CHECK-T2-NEXT: movs r3, #0
263 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
264 ; CHECK-T2-NEXT: sub.w r2, r0, r12, lsl #16
265 ; CHECK-T2-NEXT: cmp r2, #0
266 ; CHECK-T2-NEXT: it mi
267 ; CHECK-T2-NEXT: movmi r3, #1
268 ; CHECK-T2-NEXT: cmp r3, #0
269 ; CHECK-T2-NEXT: it ne
270 ; CHECK-T2-NEXT: mvnne r1, #-2147483648
271 ; CHECK-T2-NEXT: cmp.w r0, r12, lsl #16
272 ; CHECK-T2-NEXT: it vc
273 ; CHECK-T2-NEXT: movvc r1, r2
274 ; CHECK-T2-NEXT: asrs r0, r1, #16
275 ; CHECK-T2-NEXT: bx lr
276 ;
277 ; CHECK-ARM-LABEL: func16:
278 ; CHECK-ARM: @ %bb.0:
279 ; CHECK-ARM-NEXT: smulbb r12, r1, r2
280 ; CHECK-ARM-NEXT: lsl r0, r0, #16
281 ; CHECK-ARM-NEXT: mov r3, #0
282 ; CHECK-ARM-NEXT: mov r1, #-2147483648
283 ; CHECK-ARM-NEXT: sub r2, r0, r12, lsl #16
284 ; CHECK-ARM-NEXT: cmp r2, #0
285 ; CHECK-ARM-NEXT: movwmi r3, #1
286 ; CHECK-ARM-NEXT: cmp r3, #0
287 ; CHECK-ARM-NEXT: mvnne r1, #-2147483648
288 ; CHECK-ARM-NEXT: cmp r0, r12, lsl #16
289 ; CHECK-ARM-NEXT: movvc r1, r2
290 ; CHECK-ARM-NEXT: asr r0, r1, #16
291 ; CHECK-ARM-NEXT: bx lr
292 %a = mul i16 %y, %z
293 %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %a)
294 ret i16 %tmp
295 }
297 define signext i8 @func8(i8 signext %x, i8 signext %y, i8 signext %z) nounwind {
298 ; CHECK-T1-LABEL: func8:
299 ; CHECK-T1: @ %bb.0:
300 ; CHECK-T1-NEXT: .save {r4, lr}
301 ; CHECK-T1-NEXT: push {r4, lr}
302 ; CHECK-T1-NEXT: muls r1, r2, r1
303 ; CHECK-T1-NEXT: lsls r1, r1, #24
304 ; CHECK-T1-NEXT: lsls r2, r0, #24
305 ; CHECK-T1-NEXT: movs r3, #1
306 ; CHECK-T1-NEXT: subs r0, r2, r1
307 ; CHECK-T1-NEXT: mov r4, r3
308 ; CHECK-T1-NEXT: bmi .LBB3_2
309 ; CHECK-T1-NEXT: @ %bb.1:
310 ; CHECK-T1-NEXT: movs r4, #0
311 ; CHECK-T1-NEXT: .LBB3_2:
312 ; CHECK-T1-NEXT: cmp r4, #0
313 ; CHECK-T1-NEXT: bne .LBB3_4
314 ; CHECK-T1-NEXT: @ %bb.3:
315 ; CHECK-T1-NEXT: lsls r3, r3, #31
316 ; CHECK-T1-NEXT: cmp r2, r1
317 ; CHECK-T1-NEXT: bvs .LBB3_5
318 ; CHECK-T1-NEXT: b .LBB3_6
319 ; CHECK-T1-NEXT: .LBB3_4:
320 ; CHECK-T1-NEXT: ldr r3, .LCPI3_0
321 ; CHECK-T1-NEXT: cmp r2, r1
322 ; CHECK-T1-NEXT: bvc .LBB3_6
323 ; CHECK-T1-NEXT: .LBB3_5:
324 ; CHECK-T1-NEXT: mov r0, r3
325 ; CHECK-T1-NEXT: .LBB3_6:
326 ; CHECK-T1-NEXT: asrs r0, r0, #24
327 ; CHECK-T1-NEXT: pop {r4, pc}
328 ; CHECK-T1-NEXT: .p2align 2
329 ; CHECK-T1-NEXT: @ %bb.7:
330 ; CHECK-T1-NEXT: .LCPI3_0:
331 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
332 ;
333 ; CHECK-T2-LABEL: func8:
334 ; CHECK-T2: @ %bb.0:
335 ; CHECK-T2-NEXT: mul r12, r1, r2
336 ; CHECK-T2-NEXT: lsls r0, r0, #24
337 ; CHECK-T2-NEXT: movs r3, #0
338 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
339 ; CHECK-T2-NEXT: sub.w r2, r0, r12, lsl #24
340 ; CHECK-T2-NEXT: cmp r2, #0
341 ; CHECK-T2-NEXT: it mi
342 ; CHECK-T2-NEXT: movmi r3, #1
343 ; CHECK-T2-NEXT: cmp r3, #0
344 ; CHECK-T2-NEXT: it ne
345 ; CHECK-T2-NEXT: mvnne r1, #-2147483648
346 ; CHECK-T2-NEXT: cmp.w r0, r12, lsl #24
347 ; CHECK-T2-NEXT: it vc
348 ; CHECK-T2-NEXT: movvc r1, r2
349 ; CHECK-T2-NEXT: asrs r0, r1, #24
350 ; CHECK-T2-NEXT: bx lr
351 ;
352 ; CHECK-ARM-LABEL: func8:
353 ; CHECK-ARM: @ %bb.0:
354 ; CHECK-ARM-NEXT: smulbb r12, r1, r2
355 ; CHECK-ARM-NEXT: lsl r0, r0, #24
356 ; CHECK-ARM-NEXT: mov r3, #0
357 ; CHECK-ARM-NEXT: mov r1, #-2147483648
358 ; CHECK-ARM-NEXT: sub r2, r0, r12, lsl #24
359 ; CHECK-ARM-NEXT: cmp r2, #0
360 ; CHECK-ARM-NEXT: movwmi r3, #1
361 ; CHECK-ARM-NEXT: cmp r3, #0
362 ; CHECK-ARM-NEXT: mvnne r1, #-2147483648
363 ; CHECK-ARM-NEXT: cmp r0, r12, lsl #24
364 ; CHECK-ARM-NEXT: movvc r1, r2
365 ; CHECK-ARM-NEXT: asr r0, r1, #24
366 ; CHECK-ARM-NEXT: bx lr
367 %a = mul i8 %y, %z
368 %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %a)
369 ret i8 %tmp
370 }
372 define signext i4 @func4(i4 signext %x, i4 signext %y, i4 signext %z) nounwind {
373 ; CHECK-T1-LABEL: func4:
374 ; CHECK-T1: @ %bb.0:
375 ; CHECK-T1-NEXT: .save {r4, lr}
376 ; CHECK-T1-NEXT: push {r4, lr}
377 ; CHECK-T1-NEXT: muls r1, r2, r1
378 ; CHECK-T1-NEXT: lsls r1, r1, #28
379 ; CHECK-T1-NEXT: lsls r2, r0, #28
380 ; CHECK-T1-NEXT: movs r3, #1
381 ; CHECK-T1-NEXT: subs r0, r2, r1
382 ; CHECK-T1-NEXT: mov r4, r3
383 ; CHECK-T1-NEXT: bmi .LBB4_2
384 ; CHECK-T1-NEXT: @ %bb.1:
385 ; CHECK-T1-NEXT: movs r4, #0
386 ; CHECK-T1-NEXT: .LBB4_2:
387 ; CHECK-T1-NEXT: cmp r4, #0
388 ; CHECK-T1-NEXT: bne .LBB4_4
389 ; CHECK-T1-NEXT: @ %bb.3:
390 ; CHECK-T1-NEXT: lsls r3, r3, #31
391 ; CHECK-T1-NEXT: cmp r2, r1
392 ; CHECK-T1-NEXT: bvs .LBB4_5
393 ; CHECK-T1-NEXT: b .LBB4_6
394 ; CHECK-T1-NEXT: .LBB4_4:
395 ; CHECK-T1-NEXT: ldr r3, .LCPI4_0
396 ; CHECK-T1-NEXT: cmp r2, r1
397 ; CHECK-T1-NEXT: bvc .LBB4_6
398 ; CHECK-T1-NEXT: .LBB4_5:
399 ; CHECK-T1-NEXT: mov r0, r3
400 ; CHECK-T1-NEXT: .LBB4_6:
401 ; CHECK-T1-NEXT: asrs r0, r0, #28
402 ; CHECK-T1-NEXT: pop {r4, pc}
403 ; CHECK-T1-NEXT: .p2align 2
404 ; CHECK-T1-NEXT: @ %bb.7:
405 ; CHECK-T1-NEXT: .LCPI4_0:
406 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
407 ;
408 ; CHECK-T2-LABEL: func4:
409 ; CHECK-T2: @ %bb.0:
410 ; CHECK-T2-NEXT: mul r12, r1, r2
411 ; CHECK-T2-NEXT: lsls r0, r0, #28
412 ; CHECK-T2-NEXT: movs r3, #0
413 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
414 ; CHECK-T2-NEXT: sub.w r2, r0, r12, lsl #28
415 ; CHECK-T2-NEXT: cmp r2, #0
416 ; CHECK-T2-NEXT: it mi
417 ; CHECK-T2-NEXT: movmi r3, #1
418 ; CHECK-T2-NEXT: cmp r3, #0
419 ; CHECK-T2-NEXT: it ne
420 ; CHECK-T2-NEXT: mvnne r1, #-2147483648
421 ; CHECK-T2-NEXT: cmp.w r0, r12, lsl #28
422 ; CHECK-T2-NEXT: it vc
423 ; CHECK-T2-NEXT: movvc r1, r2
424 ; CHECK-T2-NEXT: asrs r0, r1, #28
425 ; CHECK-T2-NEXT: bx lr
426 ;
427 ; CHECK-ARM-LABEL: func4:
428 ; CHECK-ARM: @ %bb.0:
429 ; CHECK-ARM-NEXT: smulbb r12, r1, r2
430 ; CHECK-ARM-NEXT: lsl r0, r0, #28
431 ; CHECK-ARM-NEXT: mov r3, #0
432 ; CHECK-ARM-NEXT: mov r1, #-2147483648
433 ; CHECK-ARM-NEXT: sub r2, r0, r12, lsl #28
434 ; CHECK-ARM-NEXT: cmp r2, #0
435 ; CHECK-ARM-NEXT: movwmi r3, #1
436 ; CHECK-ARM-NEXT: cmp r3, #0
437 ; CHECK-ARM-NEXT: mvnne r1, #-2147483648
438 ; CHECK-ARM-NEXT: cmp r0, r12, lsl #28
439 ; CHECK-ARM-NEXT: movvc r1, r2
440 ; CHECK-ARM-NEXT: asr r0, r1, #28
441 ; CHECK-ARM-NEXT: bx lr
442 %a = mul i4 %y, %z
443 %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %a)
444 ret i4 %tmp
445 }