1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
4 define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) {
5 ; CHECK-LABEL: cmpeqz_v4i1:
6 ; CHECK: @ %bb.0: @ %entry
7 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
8 ; CHECK-NEXT: movw r1, #65535
10 ; CHECK-NEXT: vcmpt.i32 ne, q1, zr
11 ; CHECK-NEXT: vmrs r0, p0
12 ; CHECK-NEXT: eors r0, r1
13 ; CHECK-NEXT: vmsr p0, r0
14 ; CHECK-NEXT: vpsel q0, q0, q1
17 %c1 = icmp eq <4 x i32> %a, zeroinitializer
18 %c2 = icmp eq <4 x i32> %b, zeroinitializer
19 %o = or <4 x i1> %c1, %c2
20 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
24 define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) {
25 ; CHECK-LABEL: cmpnez_v4i1:
26 ; CHECK: @ %bb.0: @ %entry
27 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
28 ; CHECK-NEXT: movw r1, #65535
30 ; CHECK-NEXT: vcmpt.i32 eq, q1, zr
31 ; CHECK-NEXT: vmrs r0, p0
32 ; CHECK-NEXT: eors r0, r1
33 ; CHECK-NEXT: vmsr p0, r0
34 ; CHECK-NEXT: vpsel q0, q0, q1
37 %c1 = icmp eq <4 x i32> %a, zeroinitializer
38 %c2 = icmp ne <4 x i32> %b, zeroinitializer
39 %o = or <4 x i1> %c1, %c2
40 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
44 define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) {
45 ; CHECK-LABEL: cmpsltz_v4i1:
46 ; CHECK: @ %bb.0: @ %entry
47 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
48 ; CHECK-NEXT: movw r1, #65535
50 ; CHECK-NEXT: vcmpt.s32 ge, q1, zr
51 ; CHECK-NEXT: vmrs r0, p0
52 ; CHECK-NEXT: eors r0, r1
53 ; CHECK-NEXT: vmsr p0, r0
54 ; CHECK-NEXT: vpsel q0, q0, q1
57 %c1 = icmp eq <4 x i32> %a, zeroinitializer
58 %c2 = icmp slt <4 x i32> %b, zeroinitializer
59 %o = or <4 x i1> %c1, %c2
60 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
64 define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
65 ; CHECK-LABEL: cmpsgtz_v4i1:
66 ; CHECK: @ %bb.0: @ %entry
67 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
68 ; CHECK-NEXT: movw r1, #65535
70 ; CHECK-NEXT: vcmpt.s32 le, q1, zr
71 ; CHECK-NEXT: vmrs r0, p0
72 ; CHECK-NEXT: eors r0, r1
73 ; CHECK-NEXT: vmsr p0, r0
74 ; CHECK-NEXT: vpsel q0, q0, q1
77 %c1 = icmp eq <4 x i32> %a, zeroinitializer
78 %c2 = icmp sgt <4 x i32> %b, zeroinitializer
79 %o = or <4 x i1> %c1, %c2
80 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
84 define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) {
85 ; CHECK-LABEL: cmpslez_v4i1:
86 ; CHECK: @ %bb.0: @ %entry
87 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
88 ; CHECK-NEXT: movw r1, #65535
90 ; CHECK-NEXT: vcmpt.s32 gt, q1, zr
91 ; CHECK-NEXT: vmrs r0, p0
92 ; CHECK-NEXT: eors r0, r1
93 ; CHECK-NEXT: vmsr p0, r0
94 ; CHECK-NEXT: vpsel q0, q0, q1
97 %c1 = icmp eq <4 x i32> %a, zeroinitializer
98 %c2 = icmp sle <4 x i32> %b, zeroinitializer
99 %o = or <4 x i1> %c1, %c2
100 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
104 define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) {
105 ; CHECK-LABEL: cmpsgez_v4i1:
106 ; CHECK: @ %bb.0: @ %entry
107 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
108 ; CHECK-NEXT: movw r1, #65535
110 ; CHECK-NEXT: vcmpt.s32 lt, q1, zr
111 ; CHECK-NEXT: vmrs r0, p0
112 ; CHECK-NEXT: eors r0, r1
113 ; CHECK-NEXT: vmsr p0, r0
114 ; CHECK-NEXT: vpsel q0, q0, q1
117 %c1 = icmp eq <4 x i32> %a, zeroinitializer
118 %c2 = icmp sge <4 x i32> %b, zeroinitializer
119 %o = or <4 x i1> %c1, %c2
120 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
124 define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) {
125 ; CHECK-LABEL: cmpultz_v4i1:
126 ; CHECK: @ %bb.0: @ %entry
127 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
128 ; CHECK-NEXT: vpsel q0, q0, q1
131 %c1 = icmp eq <4 x i32> %a, zeroinitializer
132 %c2 = icmp ult <4 x i32> %b, zeroinitializer
133 %o = or <4 x i1> %c1, %c2
134 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
138 define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
139 ; CHECK-LABEL: cmpugtz_v4i1:
140 ; CHECK: @ %bb.0: @ %entry
141 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
142 ; CHECK-NEXT: movw r1, #65535
144 ; CHECK-NEXT: vcmpt.i32 eq, q1, zr
145 ; CHECK-NEXT: vmrs r0, p0
146 ; CHECK-NEXT: eors r0, r1
147 ; CHECK-NEXT: vmsr p0, r0
148 ; CHECK-NEXT: vpsel q0, q0, q1
151 %c1 = icmp eq <4 x i32> %a, zeroinitializer
152 %c2 = icmp ugt <4 x i32> %b, zeroinitializer
153 %o = or <4 x i1> %c1, %c2
154 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
158 define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
159 ; CHECK-LABEL: cmpulez_v4i1:
160 ; CHECK: @ %bb.0: @ %entry
161 ; CHECK-NEXT: vcmp.u32 cs, q1, zr
162 ; CHECK-NEXT: vmrs r0, p0
163 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
164 ; CHECK-NEXT: vmrs r1, p0
165 ; CHECK-NEXT: orrs r0, r1
166 ; CHECK-NEXT: vmsr p0, r0
167 ; CHECK-NEXT: vpsel q0, q0, q1
170 %c1 = icmp eq <4 x i32> %a, zeroinitializer
171 %c2 = icmp ule <4 x i32> %b, zeroinitializer
172 %o = or <4 x i1> %c1, %c2
173 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
177 define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) {
178 ; CHECK-LABEL: cmpugez_v4i1:
179 ; CHECK: @ %bb.0: @ %entry
182 %c1 = icmp eq <4 x i32> %a, zeroinitializer
183 %c2 = icmp uge <4 x i32> %b, zeroinitializer
184 %o = or <4 x i1> %c1, %c2
185 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
191 define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
192 ; CHECK-LABEL: cmpeq_v4i1:
193 ; CHECK: @ %bb.0: @ %entry
194 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
195 ; CHECK-NEXT: movw r1, #65535
197 ; CHECK-NEXT: vcmpt.i32 ne, q1, q2
198 ; CHECK-NEXT: vmrs r0, p0
199 ; CHECK-NEXT: eors r0, r1
200 ; CHECK-NEXT: vmsr p0, r0
201 ; CHECK-NEXT: vpsel q0, q0, q1
204 %c1 = icmp eq <4 x i32> %a, zeroinitializer
205 %c2 = icmp eq <4 x i32> %b, %c
206 %o = or <4 x i1> %c1, %c2
207 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
211 define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
212 ; CHECK-LABEL: cmpne_v4i1:
213 ; CHECK: @ %bb.0: @ %entry
214 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
215 ; CHECK-NEXT: movw r1, #65535
217 ; CHECK-NEXT: vcmpt.i32 eq, q1, q2
218 ; CHECK-NEXT: vmrs r0, p0
219 ; CHECK-NEXT: eors r0, r1
220 ; CHECK-NEXT: vmsr p0, r0
221 ; CHECK-NEXT: vpsel q0, q0, q1
224 %c1 = icmp eq <4 x i32> %a, zeroinitializer
225 %c2 = icmp ne <4 x i32> %b, %c
226 %o = or <4 x i1> %c1, %c2
227 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
231 define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
232 ; CHECK-LABEL: cmpslt_v4i1:
233 ; CHECK: @ %bb.0: @ %entry
234 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
235 ; CHECK-NEXT: movw r1, #65535
237 ; CHECK-NEXT: vcmpt.s32 le, q2, q1
238 ; CHECK-NEXT: vmrs r0, p0
239 ; CHECK-NEXT: eors r0, r1
240 ; CHECK-NEXT: vmsr p0, r0
241 ; CHECK-NEXT: vpsel q0, q0, q1
244 %c1 = icmp eq <4 x i32> %a, zeroinitializer
245 %c2 = icmp slt <4 x i32> %b, %c
246 %o = or <4 x i1> %c1, %c2
247 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
251 define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
252 ; CHECK-LABEL: cmpsgt_v4i1:
253 ; CHECK: @ %bb.0: @ %entry
254 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
255 ; CHECK-NEXT: movw r1, #65535
257 ; CHECK-NEXT: vcmpt.s32 le, q1, q2
258 ; CHECK-NEXT: vmrs r0, p0
259 ; CHECK-NEXT: eors r0, r1
260 ; CHECK-NEXT: vmsr p0, r0
261 ; CHECK-NEXT: vpsel q0, q0, q1
264 %c1 = icmp eq <4 x i32> %a, zeroinitializer
265 %c2 = icmp sgt <4 x i32> %b, %c
266 %o = or <4 x i1> %c1, %c2
267 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
271 define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
272 ; CHECK-LABEL: cmpsle_v4i1:
273 ; CHECK: @ %bb.0: @ %entry
274 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
275 ; CHECK-NEXT: movw r1, #65535
277 ; CHECK-NEXT: vcmpt.s32 lt, q2, q1
278 ; CHECK-NEXT: vmrs r0, p0
279 ; CHECK-NEXT: eors r0, r1
280 ; CHECK-NEXT: vmsr p0, r0
281 ; CHECK-NEXT: vpsel q0, q0, q1
284 %c1 = icmp eq <4 x i32> %a, zeroinitializer
285 %c2 = icmp sle <4 x i32> %b, %c
286 %o = or <4 x i1> %c1, %c2
287 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
291 define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
292 ; CHECK-LABEL: cmpsge_v4i1:
293 ; CHECK: @ %bb.0: @ %entry
294 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
295 ; CHECK-NEXT: movw r1, #65535
297 ; CHECK-NEXT: vcmpt.s32 lt, q1, q2
298 ; CHECK-NEXT: vmrs r0, p0
299 ; CHECK-NEXT: eors r0, r1
300 ; CHECK-NEXT: vmsr p0, r0
301 ; CHECK-NEXT: vpsel q0, q0, q1
304 %c1 = icmp eq <4 x i32> %a, zeroinitializer
305 %c2 = icmp sge <4 x i32> %b, %c
306 %o = or <4 x i1> %c1, %c2
307 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
311 define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
312 ; CHECK-LABEL: cmpult_v4i1:
313 ; CHECK: @ %bb.0: @ %entry
314 ; CHECK-NEXT: vcmp.u32 hi, q2, q1
315 ; CHECK-NEXT: vmrs r0, p0
316 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
317 ; CHECK-NEXT: vmrs r1, p0
318 ; CHECK-NEXT: orrs r0, r1
319 ; CHECK-NEXT: vmsr p0, r0
320 ; CHECK-NEXT: vpsel q0, q0, q1
323 %c1 = icmp eq <4 x i32> %a, zeroinitializer
324 %c2 = icmp ult <4 x i32> %b, %c
325 %o = or <4 x i1> %c1, %c2
326 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
330 define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
331 ; CHECK-LABEL: cmpugt_v4i1:
332 ; CHECK: @ %bb.0: @ %entry
333 ; CHECK-NEXT: vcmp.u32 hi, q1, q2
334 ; CHECK-NEXT: vmrs r0, p0
335 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
336 ; CHECK-NEXT: vmrs r1, p0
337 ; CHECK-NEXT: orrs r0, r1
338 ; CHECK-NEXT: vmsr p0, r0
339 ; CHECK-NEXT: vpsel q0, q0, q1
342 %c1 = icmp eq <4 x i32> %a, zeroinitializer
343 %c2 = icmp ugt <4 x i32> %b, %c
344 %o = or <4 x i1> %c1, %c2
345 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
349 define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
350 ; CHECK-LABEL: cmpule_v4i1:
351 ; CHECK: @ %bb.0: @ %entry
352 ; CHECK-NEXT: vcmp.u32 cs, q2, q1
353 ; CHECK-NEXT: vmrs r0, p0
354 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
355 ; CHECK-NEXT: vmrs r1, p0
356 ; CHECK-NEXT: orrs r0, r1
357 ; CHECK-NEXT: vmsr p0, r0
358 ; CHECK-NEXT: vpsel q0, q0, q1
361 %c1 = icmp eq <4 x i32> %a, zeroinitializer
362 %c2 = icmp ule <4 x i32> %b, %c
363 %o = or <4 x i1> %c1, %c2
364 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
368 define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
369 ; CHECK-LABEL: cmpuge_v4i1:
370 ; CHECK: @ %bb.0: @ %entry
371 ; CHECK-NEXT: vcmp.u32 cs, q1, q2
372 ; CHECK-NEXT: vmrs r0, p0
373 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
374 ; CHECK-NEXT: vmrs r1, p0
375 ; CHECK-NEXT: orrs r0, r1
376 ; CHECK-NEXT: vmsr p0, r0
377 ; CHECK-NEXT: vpsel q0, q0, q1
380 %c1 = icmp eq <4 x i32> %a, zeroinitializer
381 %c2 = icmp uge <4 x i32> %b, %c
382 %o = or <4 x i1> %c1, %c2
383 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
390 define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {
391 ; CHECK-LABEL: cmpeqz_v8i1:
392 ; CHECK: @ %bb.0: @ %entry
393 ; CHECK-NEXT: vcmp.i16 ne, q0, zr
394 ; CHECK-NEXT: movw r1, #65535
396 ; CHECK-NEXT: vcmpt.i16 ne, q1, zr
397 ; CHECK-NEXT: vmrs r0, p0
398 ; CHECK-NEXT: eors r0, r1
399 ; CHECK-NEXT: vmsr p0, r0
400 ; CHECK-NEXT: vpsel q0, q0, q1
403 %c1 = icmp eq <8 x i16> %a, zeroinitializer
404 %c2 = icmp eq <8 x i16> %b, zeroinitializer
405 %o = or <8 x i1> %c1, %c2
406 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
410 define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
411 ; CHECK-LABEL: cmpeq_v8i1:
412 ; CHECK: @ %bb.0: @ %entry
413 ; CHECK-NEXT: vcmp.i16 ne, q0, zr
414 ; CHECK-NEXT: movw r1, #65535
416 ; CHECK-NEXT: vcmpt.i16 ne, q1, q2
417 ; CHECK-NEXT: vmrs r0, p0
418 ; CHECK-NEXT: eors r0, r1
419 ; CHECK-NEXT: vmsr p0, r0
420 ; CHECK-NEXT: vpsel q0, q0, q1
423 %c1 = icmp eq <8 x i16> %a, zeroinitializer
424 %c2 = icmp eq <8 x i16> %b, %c
425 %o = or <8 x i1> %c1, %c2
426 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
431 define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {
432 ; CHECK-LABEL: cmpeqz_v16i1:
433 ; CHECK: @ %bb.0: @ %entry
434 ; CHECK-NEXT: vcmp.i8 ne, q0, zr
435 ; CHECK-NEXT: movw r1, #65535
437 ; CHECK-NEXT: vcmpt.i8 ne, q1, zr
438 ; CHECK-NEXT: vmrs r0, p0
439 ; CHECK-NEXT: eors r0, r1
440 ; CHECK-NEXT: vmsr p0, r0
441 ; CHECK-NEXT: vpsel q0, q0, q1
444 %c1 = icmp eq <16 x i8> %a, zeroinitializer
445 %c2 = icmp eq <16 x i8> %b, zeroinitializer
446 %o = or <16 x i1> %c1, %c2
447 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
451 define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
452 ; CHECK-LABEL: cmpeq_v16i1:
453 ; CHECK: @ %bb.0: @ %entry
454 ; CHECK-NEXT: vcmp.i8 ne, q0, zr
455 ; CHECK-NEXT: movw r1, #65535
457 ; CHECK-NEXT: vcmpt.i8 ne, q1, q2
458 ; CHECK-NEXT: vmrs r0, p0
459 ; CHECK-NEXT: eors r0, r1
460 ; CHECK-NEXT: vmsr p0, r0
461 ; CHECK-NEXT: vpsel q0, q0, q1
464 %c1 = icmp eq <16 x i8> %a, zeroinitializer
465 %c2 = icmp eq <16 x i8> %b, %c
466 %o = or <16 x i1> %c1, %c2
467 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
472 define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
473 ; CHECK-LABEL: cmpeqz_v2i1:
474 ; CHECK: @ %bb.0: @ %entry
475 ; CHECK-NEXT: vmov r0, s5
476 ; CHECK-NEXT: vmov r1, s4
477 ; CHECK-NEXT: orrs r0, r1
478 ; CHECK-NEXT: vmov r1, s6
479 ; CHECK-NEXT: clz r0, r0
480 ; CHECK-NEXT: lsrs r0, r0, #5
482 ; CHECK-NEXT: movne.w r0, #-1
483 ; CHECK-NEXT: vmov.32 q2[0], r0
484 ; CHECK-NEXT: vmov.32 q2[1], r0
485 ; CHECK-NEXT: vmov r0, s7
486 ; CHECK-NEXT: orrs r0, r1
487 ; CHECK-NEXT: vmov r1, s0
488 ; CHECK-NEXT: clz r0, r0
489 ; CHECK-NEXT: lsrs r0, r0, #5
491 ; CHECK-NEXT: movne.w r0, #-1
492 ; CHECK-NEXT: vmov.32 q2[2], r0
493 ; CHECK-NEXT: vmov.32 q2[3], r0
494 ; CHECK-NEXT: vmov r0, s1
495 ; CHECK-NEXT: orrs r0, r1
496 ; CHECK-NEXT: vmov r1, s2
497 ; CHECK-NEXT: clz r0, r0
498 ; CHECK-NEXT: lsrs r0, r0, #5
500 ; CHECK-NEXT: movne.w r0, #-1
501 ; CHECK-NEXT: vmov.32 q3[0], r0
502 ; CHECK-NEXT: vmov.32 q3[1], r0
503 ; CHECK-NEXT: vmov r0, s3
504 ; CHECK-NEXT: orrs r0, r1
505 ; CHECK-NEXT: clz r0, r0
506 ; CHECK-NEXT: lsrs r0, r0, #5
508 ; CHECK-NEXT: movne.w r0, #-1
509 ; CHECK-NEXT: vmov.32 q3[2], r0
510 ; CHECK-NEXT: vmov.32 q3[3], r0
511 ; CHECK-NEXT: vorr q2, q3, q2
512 ; CHECK-NEXT: vbic q1, q1, q2
513 ; CHECK-NEXT: vand q0, q0, q2
514 ; CHECK-NEXT: vorr q0, q0, q1
517 %c1 = icmp eq <2 x i64> %a, zeroinitializer
518 %c2 = icmp eq <2 x i64> %b, zeroinitializer
519 %o = or <2 x i1> %c1, %c2
520 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
524 define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
525 ; CHECK-LABEL: cmpeq_v2i1:
526 ; CHECK: @ %bb.0: @ %entry
527 ; CHECK-NEXT: vmov r0, s9
528 ; CHECK-NEXT: vmov r1, s5
529 ; CHECK-NEXT: vmov r2, s4
530 ; CHECK-NEXT: eors r0, r1
531 ; CHECK-NEXT: vmov r1, s8
532 ; CHECK-NEXT: eors r1, r2
533 ; CHECK-NEXT: vmov r2, s6
534 ; CHECK-NEXT: orrs r0, r1
535 ; CHECK-NEXT: vmov r1, s7
536 ; CHECK-NEXT: clz r0, r0
537 ; CHECK-NEXT: lsrs r0, r0, #5
539 ; CHECK-NEXT: movne.w r0, #-1
540 ; CHECK-NEXT: vmov.32 q3[0], r0
541 ; CHECK-NEXT: vmov.32 q3[1], r0
542 ; CHECK-NEXT: vmov r0, s11
543 ; CHECK-NEXT: eors r0, r1
544 ; CHECK-NEXT: vmov r1, s10
545 ; CHECK-NEXT: eors r1, r2
546 ; CHECK-NEXT: orrs r0, r1
547 ; CHECK-NEXT: vmov r1, s0
548 ; CHECK-NEXT: clz r0, r0
549 ; CHECK-NEXT: lsrs r0, r0, #5
551 ; CHECK-NEXT: movne.w r0, #-1
552 ; CHECK-NEXT: vmov.32 q3[2], r0
553 ; CHECK-NEXT: vmov.32 q3[3], r0
554 ; CHECK-NEXT: vmov r0, s1
555 ; CHECK-NEXT: orrs r0, r1
556 ; CHECK-NEXT: vmov r1, s2
557 ; CHECK-NEXT: clz r0, r0
558 ; CHECK-NEXT: lsrs r0, r0, #5
560 ; CHECK-NEXT: movne.w r0, #-1
561 ; CHECK-NEXT: vmov.32 q2[0], r0
562 ; CHECK-NEXT: vmov.32 q2[1], r0
563 ; CHECK-NEXT: vmov r0, s3
564 ; CHECK-NEXT: orrs r0, r1
565 ; CHECK-NEXT: clz r0, r0
566 ; CHECK-NEXT: lsrs r0, r0, #5
568 ; CHECK-NEXT: movne.w r0, #-1
569 ; CHECK-NEXT: vmov.32 q2[2], r0
570 ; CHECK-NEXT: vmov.32 q2[3], r0
571 ; CHECK-NEXT: vorr q2, q2, q3
572 ; CHECK-NEXT: vbic q1, q1, q2
573 ; CHECK-NEXT: vand q0, q0, q2
574 ; CHECK-NEXT: vorr q0, q0, q1
577 %c1 = icmp eq <2 x i64> %a, zeroinitializer
578 %c2 = icmp eq <2 x i64> %b, %c
579 %o = or <2 x i1> %c1, %c2
580 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b