1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
4 define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) {
5 ; CHECK-LABEL: cmpeqz_v4i1:
6 ; CHECK: @ %bb.0: @ %entry
7 ; CHECK-NEXT: vorr q2, q0, q1
8 ; CHECK-NEXT: vcmp.i32 eq, q2, zr
9 ; CHECK-NEXT: vpsel q0, q0, q1
12 %c1 = icmp eq <4 x i32> %a, zeroinitializer
13 %c2 = icmp eq <4 x i32> %b, zeroinitializer
14 %o = and <4 x i1> %c1, %c2
15 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
19 define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) {
20 ; CHECK-LABEL: cmpnez_v4i1:
21 ; CHECK: @ %bb.0: @ %entry
22 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
24 ; CHECK-NEXT: vcmpt.i32 ne, q1, zr
25 ; CHECK-NEXT: vpsel q0, q0, q1
28 %c1 = icmp eq <4 x i32> %a, zeroinitializer
29 %c2 = icmp ne <4 x i32> %b, zeroinitializer
30 %o = and <4 x i1> %c1, %c2
31 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
35 define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) {
36 ; CHECK-LABEL: cmpsltz_v4i1:
37 ; CHECK: @ %bb.0: @ %entry
38 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
40 ; CHECK-NEXT: vcmpt.s32 lt, q1, zr
41 ; CHECK-NEXT: vpsel q0, q0, q1
44 %c1 = icmp eq <4 x i32> %a, zeroinitializer
45 %c2 = icmp slt <4 x i32> %b, zeroinitializer
46 %o = and <4 x i1> %c1, %c2
47 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
51 define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
52 ; CHECK-LABEL: cmpsgtz_v4i1:
53 ; CHECK: @ %bb.0: @ %entry
54 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
56 ; CHECK-NEXT: vcmpt.s32 gt, q1, zr
57 ; CHECK-NEXT: vpsel q0, q0, q1
60 %c1 = icmp eq <4 x i32> %a, zeroinitializer
61 %c2 = icmp sgt <4 x i32> %b, zeroinitializer
62 %o = and <4 x i1> %c1, %c2
63 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
67 define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) {
68 ; CHECK-LABEL: cmpslez_v4i1:
69 ; CHECK: @ %bb.0: @ %entry
70 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
72 ; CHECK-NEXT: vcmpt.s32 le, q1, zr
73 ; CHECK-NEXT: vpsel q0, q0, q1
76 %c1 = icmp eq <4 x i32> %a, zeroinitializer
77 %c2 = icmp sle <4 x i32> %b, zeroinitializer
78 %o = and <4 x i1> %c1, %c2
79 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
83 define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) {
84 ; CHECK-LABEL: cmpsgez_v4i1:
85 ; CHECK: @ %bb.0: @ %entry
86 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
88 ; CHECK-NEXT: vcmpt.s32 ge, q1, zr
89 ; CHECK-NEXT: vpsel q0, q0, q1
92 %c1 = icmp eq <4 x i32> %a, zeroinitializer
93 %c2 = icmp sge <4 x i32> %b, zeroinitializer
94 %o = and <4 x i1> %c1, %c2
95 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
99 define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) {
100 ; CHECK-LABEL: cmpultz_v4i1:
101 ; CHECK: @ %bb.0: @ %entry
102 ; CHECK-NEXT: vmov q0, q1
105 %c1 = icmp eq <4 x i32> %a, zeroinitializer
106 %c2 = icmp ult <4 x i32> %b, zeroinitializer
107 %o = and <4 x i1> %c1, %c2
108 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
112 define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
113 ; CHECK-LABEL: cmpugtz_v4i1:
114 ; CHECK: @ %bb.0: @ %entry
115 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
117 ; CHECK-NEXT: vcmpt.i32 ne, q1, zr
118 ; CHECK-NEXT: vpsel q0, q0, q1
121 %c1 = icmp eq <4 x i32> %a, zeroinitializer
122 %c2 = icmp ugt <4 x i32> %b, zeroinitializer
123 %o = and <4 x i1> %c1, %c2
124 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
128 define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
129 ; CHECK-LABEL: cmpulez_v4i1:
130 ; CHECK: @ %bb.0: @ %entry
131 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
132 ; CHECK-NEXT: vmov.i32 q2, #0x0
134 ; CHECK-NEXT: vcmpt.u32 cs, q2, q1
135 ; CHECK-NEXT: vpsel q0, q0, q1
138 %c1 = icmp eq <4 x i32> %a, zeroinitializer
139 %c2 = icmp ule <4 x i32> %b, zeroinitializer
140 %o = and <4 x i1> %c1, %c2
141 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
145 define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) {
146 ; CHECK-LABEL: cmpugez_v4i1:
147 ; CHECK: @ %bb.0: @ %entry
148 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
149 ; CHECK-NEXT: vpsel q0, q0, q1
152 %c1 = icmp eq <4 x i32> %a, zeroinitializer
153 %c2 = icmp uge <4 x i32> %b, zeroinitializer
154 %o = and <4 x i1> %c1, %c2
155 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
161 define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
162 ; CHECK-LABEL: cmpeq_v4i1:
163 ; CHECK: @ %bb.0: @ %entry
164 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
166 ; CHECK-NEXT: vcmpt.i32 eq, q1, q2
167 ; CHECK-NEXT: vpsel q0, q0, q1
170 %c1 = icmp eq <4 x i32> %a, zeroinitializer
171 %c2 = icmp eq <4 x i32> %b, %c
172 %o = and <4 x i1> %c1, %c2
173 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
177 define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
178 ; CHECK-LABEL: cmpne_v4i1:
179 ; CHECK: @ %bb.0: @ %entry
180 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
182 ; CHECK-NEXT: vcmpt.i32 ne, q1, q2
183 ; CHECK-NEXT: vpsel q0, q0, q1
186 %c1 = icmp eq <4 x i32> %a, zeroinitializer
187 %c2 = icmp ne <4 x i32> %b, %c
188 %o = and <4 x i1> %c1, %c2
189 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
193 define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
194 ; CHECK-LABEL: cmpslt_v4i1:
195 ; CHECK: @ %bb.0: @ %entry
196 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
198 ; CHECK-NEXT: vcmpt.s32 gt, q2, q1
199 ; CHECK-NEXT: vpsel q0, q0, q1
202 %c1 = icmp eq <4 x i32> %a, zeroinitializer
203 %c2 = icmp slt <4 x i32> %b, %c
204 %o = and <4 x i1> %c1, %c2
205 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
209 define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
210 ; CHECK-LABEL: cmpsgt_v4i1:
211 ; CHECK: @ %bb.0: @ %entry
212 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
214 ; CHECK-NEXT: vcmpt.s32 gt, q1, q2
215 ; CHECK-NEXT: vpsel q0, q0, q1
218 %c1 = icmp eq <4 x i32> %a, zeroinitializer
219 %c2 = icmp sgt <4 x i32> %b, %c
220 %o = and <4 x i1> %c1, %c2
221 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
225 define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
226 ; CHECK-LABEL: cmpsle_v4i1:
227 ; CHECK: @ %bb.0: @ %entry
228 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
230 ; CHECK-NEXT: vcmpt.s32 ge, q2, q1
231 ; CHECK-NEXT: vpsel q0, q0, q1
234 %c1 = icmp eq <4 x i32> %a, zeroinitializer
235 %c2 = icmp sle <4 x i32> %b, %c
236 %o = and <4 x i1> %c1, %c2
237 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
241 define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
242 ; CHECK-LABEL: cmpsge_v4i1:
243 ; CHECK: @ %bb.0: @ %entry
244 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
246 ; CHECK-NEXT: vcmpt.s32 ge, q1, q2
247 ; CHECK-NEXT: vpsel q0, q0, q1
250 %c1 = icmp eq <4 x i32> %a, zeroinitializer
251 %c2 = icmp sge <4 x i32> %b, %c
252 %o = and <4 x i1> %c1, %c2
253 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
257 define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
258 ; CHECK-LABEL: cmpult_v4i1:
259 ; CHECK: @ %bb.0: @ %entry
260 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
262 ; CHECK-NEXT: vcmpt.u32 hi, q2, q1
263 ; CHECK-NEXT: vpsel q0, q0, q1
266 %c1 = icmp eq <4 x i32> %a, zeroinitializer
267 %c2 = icmp ult <4 x i32> %b, %c
268 %o = and <4 x i1> %c1, %c2
269 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
273 define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
274 ; CHECK-LABEL: cmpugt_v4i1:
275 ; CHECK: @ %bb.0: @ %entry
276 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
278 ; CHECK-NEXT: vcmpt.u32 hi, q1, q2
279 ; CHECK-NEXT: vpsel q0, q0, q1
282 %c1 = icmp eq <4 x i32> %a, zeroinitializer
283 %c2 = icmp ugt <4 x i32> %b, %c
284 %o = and <4 x i1> %c1, %c2
285 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
289 define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
290 ; CHECK-LABEL: cmpule_v4i1:
291 ; CHECK: @ %bb.0: @ %entry
292 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
294 ; CHECK-NEXT: vcmpt.u32 cs, q2, q1
295 ; CHECK-NEXT: vpsel q0, q0, q1
298 %c1 = icmp eq <4 x i32> %a, zeroinitializer
299 %c2 = icmp ule <4 x i32> %b, %c
300 %o = and <4 x i1> %c1, %c2
301 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
305 define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
306 ; CHECK-LABEL: cmpuge_v4i1:
307 ; CHECK: @ %bb.0: @ %entry
308 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
310 ; CHECK-NEXT: vcmpt.u32 cs, q1, q2
311 ; CHECK-NEXT: vpsel q0, q0, q1
314 %c1 = icmp eq <4 x i32> %a, zeroinitializer
315 %c2 = icmp uge <4 x i32> %b, %c
316 %o = and <4 x i1> %c1, %c2
317 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
324 define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {
325 ; CHECK-LABEL: cmpeqz_v8i1:
326 ; CHECK: @ %bb.0: @ %entry
327 ; CHECK-NEXT: vorr q2, q0, q1
328 ; CHECK-NEXT: vcmp.i16 eq, q2, zr
329 ; CHECK-NEXT: vpsel q0, q0, q1
332 %c1 = icmp eq <8 x i16> %a, zeroinitializer
333 %c2 = icmp eq <8 x i16> %b, zeroinitializer
334 %o = and <8 x i1> %c1, %c2
335 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
339 define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
340 ; CHECK-LABEL: cmpeq_v8i1:
341 ; CHECK: @ %bb.0: @ %entry
342 ; CHECK-NEXT: vcmp.i16 eq, q0, zr
344 ; CHECK-NEXT: vcmpt.i16 eq, q1, q2
345 ; CHECK-NEXT: vpsel q0, q0, q1
348 %c1 = icmp eq <8 x i16> %a, zeroinitializer
349 %c2 = icmp eq <8 x i16> %b, %c
350 %o = and <8 x i1> %c1, %c2
351 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
356 define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {
357 ; CHECK-LABEL: cmpeqz_v16i1:
358 ; CHECK: @ %bb.0: @ %entry
359 ; CHECK-NEXT: vorr q2, q0, q1
360 ; CHECK-NEXT: vcmp.i8 eq, q2, zr
361 ; CHECK-NEXT: vpsel q0, q0, q1
364 %c1 = icmp eq <16 x i8> %a, zeroinitializer
365 %c2 = icmp eq <16 x i8> %b, zeroinitializer
366 %o = and <16 x i1> %c1, %c2
367 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
371 define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
372 ; CHECK-LABEL: cmpeq_v16i1:
373 ; CHECK: @ %bb.0: @ %entry
374 ; CHECK-NEXT: vcmp.i8 eq, q0, zr
376 ; CHECK-NEXT: vcmpt.i8 eq, q1, q2
377 ; CHECK-NEXT: vpsel q0, q0, q1
380 %c1 = icmp eq <16 x i8> %a, zeroinitializer
381 %c2 = icmp eq <16 x i8> %b, %c
382 %o = and <16 x i1> %c1, %c2
383 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
388 define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
389 ; CHECK-LABEL: cmpeqz_v2i1:
390 ; CHECK: @ %bb.0: @ %entry
391 ; CHECK-NEXT: vorr q2, q0, q1
392 ; CHECK-NEXT: vmov r0, s9
393 ; CHECK-NEXT: vmov r1, s8
394 ; CHECK-NEXT: orrs r0, r1
395 ; CHECK-NEXT: vmov r1, s10
396 ; CHECK-NEXT: clz r0, r0
397 ; CHECK-NEXT: lsrs r0, r0, #5
399 ; CHECK-NEXT: movne.w r0, #-1
400 ; CHECK-NEXT: vmov.32 q3[0], r0
401 ; CHECK-NEXT: vmov.32 q3[1], r0
402 ; CHECK-NEXT: vmov r0, s11
403 ; CHECK-NEXT: orrs r0, r1
404 ; CHECK-NEXT: clz r0, r0
405 ; CHECK-NEXT: lsrs r0, r0, #5
407 ; CHECK-NEXT: movne.w r0, #-1
408 ; CHECK-NEXT: vmov.32 q3[2], r0
409 ; CHECK-NEXT: vmov.32 q3[3], r0
410 ; CHECK-NEXT: vbic q1, q1, q3
411 ; CHECK-NEXT: vand q0, q0, q3
412 ; CHECK-NEXT: vorr q0, q0, q1
415 %c1 = icmp eq <2 x i64> %a, zeroinitializer
416 %c2 = icmp eq <2 x i64> %b, zeroinitializer
417 %o = and <2 x i1> %c1, %c2
418 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
422 define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
423 ; CHECK-LABEL: cmpeq_v2i1:
424 ; CHECK: @ %bb.0: @ %entry
425 ; CHECK-NEXT: vmov r0, s9
426 ; CHECK-NEXT: vmov r1, s5
427 ; CHECK-NEXT: vmov r2, s4
428 ; CHECK-NEXT: eors r0, r1
429 ; CHECK-NEXT: vmov r1, s8
430 ; CHECK-NEXT: eors r1, r2
431 ; CHECK-NEXT: vmov r2, s6
432 ; CHECK-NEXT: orrs r0, r1
433 ; CHECK-NEXT: vmov r1, s7
434 ; CHECK-NEXT: clz r0, r0
435 ; CHECK-NEXT: lsrs r0, r0, #5
437 ; CHECK-NEXT: movne.w r0, #-1
438 ; CHECK-NEXT: vmov.32 q3[0], r0
439 ; CHECK-NEXT: vmov.32 q3[1], r0
440 ; CHECK-NEXT: vmov r0, s11
441 ; CHECK-NEXT: eors r0, r1
442 ; CHECK-NEXT: vmov r1, s10
443 ; CHECK-NEXT: eors r1, r2
444 ; CHECK-NEXT: orrs r0, r1
445 ; CHECK-NEXT: vmov r1, s0
446 ; CHECK-NEXT: clz r0, r0
447 ; CHECK-NEXT: lsrs r0, r0, #5
449 ; CHECK-NEXT: movne.w r0, #-1
450 ; CHECK-NEXT: vmov.32 q3[2], r0
451 ; CHECK-NEXT: vmov.32 q3[3], r0
452 ; CHECK-NEXT: vmov r0, s1
453 ; CHECK-NEXT: orrs r0, r1
454 ; CHECK-NEXT: vmov r1, s2
455 ; CHECK-NEXT: clz r0, r0
456 ; CHECK-NEXT: lsrs r0, r0, #5
458 ; CHECK-NEXT: movne.w r0, #-1
459 ; CHECK-NEXT: vmov.32 q2[0], r0
460 ; CHECK-NEXT: vmov.32 q2[1], r0
461 ; CHECK-NEXT: vmov r0, s3
462 ; CHECK-NEXT: orrs r0, r1
463 ; CHECK-NEXT: clz r0, r0
464 ; CHECK-NEXT: lsrs r0, r0, #5
466 ; CHECK-NEXT: movne.w r0, #-1
467 ; CHECK-NEXT: vmov.32 q2[2], r0
468 ; CHECK-NEXT: vmov.32 q2[3], r0
469 ; CHECK-NEXT: vand q2, q2, q3
470 ; CHECK-NEXT: vbic q1, q1, q2
471 ; CHECK-NEXT: vand q0, q0, q2
472 ; CHECK-NEXT: vorr q0, q0, q1
475 %c1 = icmp eq <2 x i64> %a, zeroinitializer
476 %c2 = icmp eq <2 x i64> %b, %c
477 %o = and <2 x i1> %c1, %c2
478 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b