[ARM] Correct register for narrowing and widening MVE loads and stores.
[llvm-core.git] / docs / AMDGPU / gfx9_data_buf_atomic128.rst
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8 .. _amdgpu_synid9_data_buf_atomic128:
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11 ===========================
13 Input data for an atomic instruction.
15 Optionally may serve as an output data:
17 * If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
19 *Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
21 *Operands:* :ref:`v<amdgpu_synid_v>`