[ARM] Correct register for narrowing and widening MVE loads and stores.
[llvm-core.git] / docs / AMDGPU / gfx8_sdst64_0.rst
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8 .. _amdgpu_synid8_sdst64_0:
10 sdst
11 ===========================
13 Instruction output.
15 *Size:* 2 dwords.
17 *Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`