[ARM] Correct register for narrowing and widening MVE loads and stores.
[llvm-core.git] / docs / AMDGPU / gfx7_sdst32_2.rst
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8 .. _amdgpu_synid7_sdst32_2:
10 sdst
11 ===========================
13 Instruction output.
15 *Size:* 1 dword.
17 *Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`trap<amdgpu_synid_trap>`