[ARM] Correct register for narrowing and widening MVE loads and stores.
[llvm-core.git] / docs / AMDGPU / gfx7_dst_buf_64.rst
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8 .. _amdgpu_synid7_dst_buf_64:
10 vdst
11 ===========================
13 Instruction output: data read from a memory buffer.
15 *Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
17 *Operands:* :ref:`v<amdgpu_synid_v>`