[ARM] Correct register for narrowing and widening MVE loads and stores.
[llvm-core.git] / docs / AMDGPU / gfx10_vdst32_0.rst
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8 .. _amdgpu_synid10_vdst32_0:
10 vdst
11 ===========================
13 Instruction output.
15 *Size:* 1 dword.
17 *Operands:* :ref:`v<amdgpu_synid_v>`