[ARM] Correct register for narrowing and widening MVE loads and stores.
[llvm-core.git] / docs / AMDGPU / gfx10_data_smem_atomic64.rst
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8 .. _amdgpu_synid10_data_smem_atomic64:
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11 ===========================
13 Input data for an atomic instruction.
15 Optionally may serve as an output data:
17 * If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
19 *Size:* 2 dwords.
21 *Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`