[AArch64] Check the expansion of BITREVERSE in regression test
[llvm-core.git] / lib / CodeGen / RegisterCoalescer.h
blob04067a1427af2e72d24f9ac11c635735770251c9
1 //===-- RegisterCoalescer.h - Register Coalescing Interface -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the abstract interface for register coalescers,
11 // allowing them to interact with and query register allocators.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_CODEGEN_REGISTERCOALESCER_H
16 #define LLVM_LIB_CODEGEN_REGISTERCOALESCER_H
18 namespace llvm {
20 class MachineInstr;
21 class TargetRegisterInfo;
22 class TargetRegisterClass;
23 class TargetInstrInfo;
25 /// A helper class for register coalescers. When deciding if
26 /// two registers can be coalesced, CoalescerPair can determine if a copy
27 /// instruction would become an identity copy after coalescing.
28 class CoalescerPair {
29 const TargetRegisterInfo &TRI;
31 /// The register that will be left after coalescing. It can be a
32 /// virtual or physical register.
33 unsigned DstReg;
35 /// The virtual register that will be coalesced into dstReg.
36 unsigned SrcReg;
38 /// The sub-register index of the old DstReg in the new coalesced register.
39 unsigned DstIdx;
41 /// The sub-register index of the old SrcReg in the new coalesced register.
42 unsigned SrcIdx;
44 /// True when the original copy was a partial subregister copy.
45 bool Partial;
47 /// True when both regs are virtual and newRC is constrained.
48 bool CrossClass;
50 /// True when DstReg and SrcReg are reversed from the original
51 /// copy instruction.
52 bool Flipped;
54 /// The register class of the coalesced register, or NULL if DstReg
55 /// is a physreg. This register class may be a super-register of both
56 /// SrcReg and DstReg.
57 const TargetRegisterClass *NewRC;
59 public:
60 CoalescerPair(const TargetRegisterInfo &tri)
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
62 Partial(false), CrossClass(false), Flipped(false), NewRC(nullptr) {}
64 /// Create a CoalescerPair representing a virtreg-to-physreg copy.
65 /// No need to call setRegisters().
66 CoalescerPair(unsigned VirtReg, unsigned PhysReg,
67 const TargetRegisterInfo &tri)
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
69 Partial(false), CrossClass(false), Flipped(false), NewRC(nullptr) {}
71 /// Set registers to match the copy instruction MI. Return
72 /// false if MI is not a coalescable copy instruction.
73 bool setRegisters(const MachineInstr*);
75 /// Swap SrcReg and DstReg. Return false if swapping is impossible
76 /// because DstReg is a physical register, or SubIdx is set.
77 bool flip();
79 /// Return true if MI is a copy instruction that will become
80 /// an identity copy after coalescing.
81 bool isCoalescable(const MachineInstr*) const;
83 /// Return true if DstReg is a physical register.
84 bool isPhys() const { return !NewRC; }
86 /// Return true if the original copy instruction did not copy
87 /// the full register, but was a subreg operation.
88 bool isPartial() const { return Partial; }
90 /// Return true if DstReg is virtual and NewRC is a smaller
91 /// register class than DstReg's.
92 bool isCrossClass() const { return CrossClass; }
94 /// Return true when getSrcReg is the register being defined by
95 /// the original copy instruction.
96 bool isFlipped() const { return Flipped; }
98 /// Return the register (virtual or physical) that will remain
99 /// after coalescing.
100 unsigned getDstReg() const { return DstReg; }
102 /// Return the virtual register that will be coalesced away.
103 unsigned getSrcReg() const { return SrcReg; }
105 /// Return the subregister index that DstReg will be coalesced into, or 0.
106 unsigned getDstIdx() const { return DstIdx; }
108 /// Return the subregister index that SrcReg will be coalesced into, or 0.
109 unsigned getSrcIdx() const { return SrcIdx; }
111 /// Return the register class of the coalesced register.
112 const TargetRegisterClass *getNewRC() const { return NewRC; }
114 } // End llvm namespace
116 #endif