1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/ADT/FoldingSet.h"
16 #include "llvm/ADT/Hashing.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DebugInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/InlineAsm.h"
28 #include "llvm/IR/LLVMContext.h"
29 #include "llvm/IR/Metadata.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/IR/ModuleSlotTracker.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/IR/Value.h"
34 #include "llvm/MC/MCInstrDesc.h"
35 #include "llvm/MC/MCSymbol.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
44 #include "llvm/Target/TargetSubtargetInfo.h"
47 static cl::opt
<bool> PrintWholeRegMask(
48 "print-whole-regmask",
49 cl::desc("Print the full contents of regmask operands in IR dumps"),
50 cl::init(true), cl::Hidden
);
52 //===----------------------------------------------------------------------===//
53 // MachineOperand Implementation
54 //===----------------------------------------------------------------------===//
56 void MachineOperand::setReg(unsigned Reg
) {
57 if (getReg() == Reg
) return; // No change.
59 // Otherwise, we have to change the register. If this operand is embedded
60 // into a machine function, we need to update the old and new register's
62 if (MachineInstr
*MI
= getParent())
63 if (MachineBasicBlock
*MBB
= MI
->getParent())
64 if (MachineFunction
*MF
= MBB
->getParent()) {
65 MachineRegisterInfo
&MRI
= MF
->getRegInfo();
66 MRI
.removeRegOperandFromUseList(this);
67 SmallContents
.RegNo
= Reg
;
68 MRI
.addRegOperandToUseList(this);
72 // Otherwise, just change the register, no problem. :)
73 SmallContents
.RegNo
= Reg
;
76 void MachineOperand::substVirtReg(unsigned Reg
, unsigned SubIdx
,
77 const TargetRegisterInfo
&TRI
) {
78 assert(TargetRegisterInfo::isVirtualRegister(Reg
));
79 if (SubIdx
&& getSubReg())
80 SubIdx
= TRI
.composeSubRegIndices(SubIdx
, getSubReg());
86 void MachineOperand::substPhysReg(unsigned Reg
, const TargetRegisterInfo
&TRI
) {
87 assert(TargetRegisterInfo::isPhysicalRegister(Reg
));
89 Reg
= TRI
.getSubReg(Reg
, getSubReg());
90 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
91 // That won't happen in legal code.
97 /// Change a def to a use, or a use to a def.
98 void MachineOperand::setIsDef(bool Val
) {
99 assert(isReg() && "Wrong MachineOperand accessor");
100 assert((!Val
|| !isDebug()) && "Marking a debug operation as def");
103 // MRI may keep uses and defs in different list positions.
104 if (MachineInstr
*MI
= getParent())
105 if (MachineBasicBlock
*MBB
= MI
->getParent())
106 if (MachineFunction
*MF
= MBB
->getParent()) {
107 MachineRegisterInfo
&MRI
= MF
->getRegInfo();
108 MRI
.removeRegOperandFromUseList(this);
110 MRI
.addRegOperandToUseList(this);
116 // If this operand is currently a register operand, and if this is in a
117 // function, deregister the operand from the register's use/def list.
118 void MachineOperand::removeRegFromUses() {
119 if (!isReg() || !isOnRegUseList())
122 if (MachineInstr
*MI
= getParent()) {
123 if (MachineBasicBlock
*MBB
= MI
->getParent()) {
124 if (MachineFunction
*MF
= MBB
->getParent())
125 MF
->getRegInfo().removeRegOperandFromUseList(this);
130 /// ChangeToImmediate - Replace this operand with a new immediate operand of
131 /// the specified value. If an operand is known to be an immediate already,
132 /// the setImm method should be used.
133 void MachineOperand::ChangeToImmediate(int64_t ImmVal
) {
134 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
138 OpKind
= MO_Immediate
;
139 Contents
.ImmVal
= ImmVal
;
142 void MachineOperand::ChangeToFPImmediate(const ConstantFP
*FPImm
) {
143 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
147 OpKind
= MO_FPImmediate
;
148 Contents
.CFP
= FPImm
;
151 void MachineOperand::ChangeToES(const char *SymName
, unsigned char TargetFlags
) {
152 assert((!isReg() || !isTied()) &&
153 "Cannot change a tied operand into an external symbol");
157 OpKind
= MO_ExternalSymbol
;
158 Contents
.OffsetedInfo
.Val
.SymbolName
= SymName
;
159 setOffset(0); // Offset is always 0.
160 setTargetFlags(TargetFlags
);
163 void MachineOperand::ChangeToMCSymbol(MCSymbol
*Sym
) {
164 assert((!isReg() || !isTied()) &&
165 "Cannot change a tied operand into an MCSymbol");
169 OpKind
= MO_MCSymbol
;
173 /// ChangeToRegister - Replace this operand with a new register operand of
174 /// the specified value. If an operand is known to be an register already,
175 /// the setReg method should be used.
176 void MachineOperand::ChangeToRegister(unsigned Reg
, bool isDef
, bool isImp
,
177 bool isKill
, bool isDead
, bool isUndef
,
179 MachineRegisterInfo
*RegInfo
= nullptr;
180 if (MachineInstr
*MI
= getParent())
181 if (MachineBasicBlock
*MBB
= MI
->getParent())
182 if (MachineFunction
*MF
= MBB
->getParent())
183 RegInfo
= &MF
->getRegInfo();
184 // If this operand is already a register operand, remove it from the
185 // register's use/def lists.
186 bool WasReg
= isReg();
187 if (RegInfo
&& WasReg
)
188 RegInfo
->removeRegOperandFromUseList(this);
190 // Change this to a register and set the reg#.
191 OpKind
= MO_Register
;
192 SmallContents
.RegNo
= Reg
;
193 SubReg_TargetFlags
= 0;
199 IsInternalRead
= false;
200 IsEarlyClobber
= false;
202 // Ensure isOnRegUseList() returns false.
203 Contents
.Reg
.Prev
= nullptr;
204 // Preserve the tie when the operand was already a register.
208 // If this operand is embedded in a function, add the operand to the
209 // register's use/def list.
211 RegInfo
->addRegOperandToUseList(this);
214 /// isIdenticalTo - Return true if this operand is identical to the specified
215 /// operand. Note that this should stay in sync with the hash_value overload
217 bool MachineOperand::isIdenticalTo(const MachineOperand
&Other
) const {
218 if (getType() != Other
.getType() ||
219 getTargetFlags() != Other
.getTargetFlags())
223 case MachineOperand::MO_Register
:
224 return getReg() == Other
.getReg() && isDef() == Other
.isDef() &&
225 getSubReg() == Other
.getSubReg();
226 case MachineOperand::MO_Immediate
:
227 return getImm() == Other
.getImm();
228 case MachineOperand::MO_CImmediate
:
229 return getCImm() == Other
.getCImm();
230 case MachineOperand::MO_FPImmediate
:
231 return getFPImm() == Other
.getFPImm();
232 case MachineOperand::MO_MachineBasicBlock
:
233 return getMBB() == Other
.getMBB();
234 case MachineOperand::MO_FrameIndex
:
235 return getIndex() == Other
.getIndex();
236 case MachineOperand::MO_ConstantPoolIndex
:
237 case MachineOperand::MO_TargetIndex
:
238 return getIndex() == Other
.getIndex() && getOffset() == Other
.getOffset();
239 case MachineOperand::MO_JumpTableIndex
:
240 return getIndex() == Other
.getIndex();
241 case MachineOperand::MO_GlobalAddress
:
242 return getGlobal() == Other
.getGlobal() && getOffset() == Other
.getOffset();
243 case MachineOperand::MO_ExternalSymbol
:
244 return !strcmp(getSymbolName(), Other
.getSymbolName()) &&
245 getOffset() == Other
.getOffset();
246 case MachineOperand::MO_BlockAddress
:
247 return getBlockAddress() == Other
.getBlockAddress() &&
248 getOffset() == Other
.getOffset();
249 case MachineOperand::MO_RegisterMask
:
250 case MachineOperand::MO_RegisterLiveOut
:
251 return getRegMask() == Other
.getRegMask();
252 case MachineOperand::MO_MCSymbol
:
253 return getMCSymbol() == Other
.getMCSymbol();
254 case MachineOperand::MO_CFIIndex
:
255 return getCFIIndex() == Other
.getCFIIndex();
256 case MachineOperand::MO_Metadata
:
257 return getMetadata() == Other
.getMetadata();
259 llvm_unreachable("Invalid machine operand type");
262 // Note: this must stay exactly in sync with isIdenticalTo above.
263 hash_code
llvm::hash_value(const MachineOperand
&MO
) {
264 switch (MO
.getType()) {
265 case MachineOperand::MO_Register
:
266 // Register operands don't have target flags.
267 return hash_combine(MO
.getType(), MO
.getReg(), MO
.getSubReg(), MO
.isDef());
268 case MachineOperand::MO_Immediate
:
269 return hash_combine(MO
.getType(), MO
.getTargetFlags(), MO
.getImm());
270 case MachineOperand::MO_CImmediate
:
271 return hash_combine(MO
.getType(), MO
.getTargetFlags(), MO
.getCImm());
272 case MachineOperand::MO_FPImmediate
:
273 return hash_combine(MO
.getType(), MO
.getTargetFlags(), MO
.getFPImm());
274 case MachineOperand::MO_MachineBasicBlock
:
275 return hash_combine(MO
.getType(), MO
.getTargetFlags(), MO
.getMBB());
276 case MachineOperand::MO_FrameIndex
:
277 return hash_combine(MO
.getType(), MO
.getTargetFlags(), MO
.getIndex());
278 case MachineOperand::MO_ConstantPoolIndex
:
279 case MachineOperand::MO_TargetIndex
:
280 return hash_combine(MO
.getType(), MO
.getTargetFlags(), MO
.getIndex(),
282 case MachineOperand::MO_JumpTableIndex
:
283 return hash_combine(MO
.getType(), MO
.getTargetFlags(), MO
.getIndex());
284 case MachineOperand::MO_ExternalSymbol
:
285 return hash_combine(MO
.getType(), MO
.getTargetFlags(), MO
.getOffset(),
287 case MachineOperand::MO_GlobalAddress
:
288 return hash_combine(MO
.getType(), MO
.getTargetFlags(), MO
.getGlobal(),
290 case MachineOperand::MO_BlockAddress
:
291 return hash_combine(MO
.getType(), MO
.getTargetFlags(),
292 MO
.getBlockAddress(), MO
.getOffset());
293 case MachineOperand::MO_RegisterMask
:
294 case MachineOperand::MO_RegisterLiveOut
:
295 return hash_combine(MO
.getType(), MO
.getTargetFlags(), MO
.getRegMask());
296 case MachineOperand::MO_Metadata
:
297 return hash_combine(MO
.getType(), MO
.getTargetFlags(), MO
.getMetadata());
298 case MachineOperand::MO_MCSymbol
:
299 return hash_combine(MO
.getType(), MO
.getTargetFlags(), MO
.getMCSymbol());
300 case MachineOperand::MO_CFIIndex
:
301 return hash_combine(MO
.getType(), MO
.getTargetFlags(), MO
.getCFIIndex());
303 llvm_unreachable("Invalid machine operand type");
306 void MachineOperand::print(raw_ostream
&OS
,
307 const TargetRegisterInfo
*TRI
) const {
308 ModuleSlotTracker
DummyMST(nullptr);
309 print(OS
, DummyMST
, TRI
);
312 void MachineOperand::print(raw_ostream
&OS
, ModuleSlotTracker
&MST
,
313 const TargetRegisterInfo
*TRI
) const {
315 case MachineOperand::MO_Register
:
316 OS
<< PrintReg(getReg(), TRI
, getSubReg());
318 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
319 isInternalRead() || isEarlyClobber() || isTied()) {
321 bool NeedComma
= false;
323 if (NeedComma
) OS
<< ',';
324 if (isEarlyClobber())
325 OS
<< "earlyclobber,";
330 // <def,read-undef> only makes sense when getSubReg() is set.
331 // Don't clutter the output otherwise.
332 if (isUndef() && getSubReg())
334 } else if (isImplicit()) {
340 if (NeedComma
) OS
<< ',';
345 if (NeedComma
) OS
<< ',';
349 if (isUndef() && isUse()) {
350 if (NeedComma
) OS
<< ',';
354 if (isInternalRead()) {
355 if (NeedComma
) OS
<< ',';
360 if (NeedComma
) OS
<< ',';
363 OS
<< unsigned(TiedTo
- 1);
368 case MachineOperand::MO_Immediate
:
371 case MachineOperand::MO_CImmediate
:
372 getCImm()->getValue().print(OS
, false);
374 case MachineOperand::MO_FPImmediate
:
375 if (getFPImm()->getType()->isFloatTy())
376 OS
<< getFPImm()->getValueAPF().convertToFloat();
378 OS
<< getFPImm()->getValueAPF().convertToDouble();
380 case MachineOperand::MO_MachineBasicBlock
:
381 OS
<< "<BB#" << getMBB()->getNumber() << ">";
383 case MachineOperand::MO_FrameIndex
:
384 OS
<< "<fi#" << getIndex() << '>';
386 case MachineOperand::MO_ConstantPoolIndex
:
387 OS
<< "<cp#" << getIndex();
388 if (getOffset()) OS
<< "+" << getOffset();
391 case MachineOperand::MO_TargetIndex
:
392 OS
<< "<ti#" << getIndex();
393 if (getOffset()) OS
<< "+" << getOffset();
396 case MachineOperand::MO_JumpTableIndex
:
397 OS
<< "<jt#" << getIndex() << '>';
399 case MachineOperand::MO_GlobalAddress
:
401 getGlobal()->printAsOperand(OS
, /*PrintType=*/false, MST
);
402 if (getOffset()) OS
<< "+" << getOffset();
405 case MachineOperand::MO_ExternalSymbol
:
406 OS
<< "<es:" << getSymbolName();
407 if (getOffset()) OS
<< "+" << getOffset();
410 case MachineOperand::MO_BlockAddress
:
412 getBlockAddress()->printAsOperand(OS
, /*PrintType=*/false, MST
);
413 if (getOffset()) OS
<< "+" << getOffset();
416 case MachineOperand::MO_RegisterMask
: {
417 unsigned NumRegsInMask
= 0;
418 unsigned NumRegsEmitted
= 0;
420 for (unsigned i
= 0; i
< TRI
->getNumRegs(); ++i
) {
421 unsigned MaskWord
= i
/ 32;
422 unsigned MaskBit
= i
% 32;
423 if (getRegMask()[MaskWord
] & (1 << MaskBit
)) {
424 if (PrintWholeRegMask
|| NumRegsEmitted
<= 10) {
425 OS
<< " " << PrintReg(i
, TRI
);
431 if (NumRegsEmitted
!= NumRegsInMask
)
432 OS
<< " and " << (NumRegsInMask
- NumRegsEmitted
) << " more...";
436 case MachineOperand::MO_RegisterLiveOut
:
437 OS
<< "<regliveout>";
439 case MachineOperand::MO_Metadata
:
441 getMetadata()->printAsOperand(OS
, MST
);
444 case MachineOperand::MO_MCSymbol
:
445 OS
<< "<MCSym=" << *getMCSymbol() << '>';
447 case MachineOperand::MO_CFIIndex
:
448 OS
<< "<call frame instruction>";
452 if (unsigned TF
= getTargetFlags())
453 OS
<< "[TF=" << TF
<< ']';
456 //===----------------------------------------------------------------------===//
457 // MachineMemOperand Implementation
458 //===----------------------------------------------------------------------===//
460 /// getAddrSpace - Return the LLVM IR address space number that this pointer
462 unsigned MachinePointerInfo::getAddrSpace() const {
463 if (V
.isNull() || V
.is
<const PseudoSourceValue
*>()) return 0;
464 return cast
<PointerType
>(V
.get
<const Value
*>()->getType())->getAddressSpace();
467 /// getConstantPool - Return a MachinePointerInfo record that refers to the
469 MachinePointerInfo
MachinePointerInfo::getConstantPool(MachineFunction
&MF
) {
470 return MachinePointerInfo(MF
.getPSVManager().getConstantPool());
473 /// getFixedStack - Return a MachinePointerInfo record that refers to the
474 /// the specified FrameIndex.
475 MachinePointerInfo
MachinePointerInfo::getFixedStack(MachineFunction
&MF
,
476 int FI
, int64_t Offset
) {
477 return MachinePointerInfo(MF
.getPSVManager().getFixedStack(FI
), Offset
);
480 MachinePointerInfo
MachinePointerInfo::getJumpTable(MachineFunction
&MF
) {
481 return MachinePointerInfo(MF
.getPSVManager().getJumpTable());
484 MachinePointerInfo
MachinePointerInfo::getGOT(MachineFunction
&MF
) {
485 return MachinePointerInfo(MF
.getPSVManager().getGOT());
488 MachinePointerInfo
MachinePointerInfo::getStack(MachineFunction
&MF
,
490 return MachinePointerInfo(MF
.getPSVManager().getStack(), Offset
);
493 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo
, unsigned f
,
494 uint64_t s
, unsigned int a
,
495 const AAMDNodes
&AAInfo
,
496 const MDNode
*Ranges
)
497 : PtrInfo(ptrinfo
), Size(s
),
498 Flags((f
& ((1 << MOMaxBits
) - 1)) | ((Log2_32(a
) + 1) << MOMaxBits
)),
499 AAInfo(AAInfo
), Ranges(Ranges
) {
500 assert((PtrInfo
.V
.isNull() || PtrInfo
.V
.is
<const PseudoSourceValue
*>() ||
501 isa
<PointerType
>(PtrInfo
.V
.get
<const Value
*>()->getType())) &&
502 "invalid pointer value");
503 assert(getBaseAlignment() == a
&& "Alignment is not a power of 2!");
504 assert((isLoad() || isStore()) && "Not a load/store!");
507 /// Profile - Gather unique data for the object.
509 void MachineMemOperand::Profile(FoldingSetNodeID
&ID
) const {
510 ID
.AddInteger(getOffset());
512 ID
.AddPointer(getOpaqueValue());
513 ID
.AddInteger(Flags
);
516 void MachineMemOperand::refineAlignment(const MachineMemOperand
*MMO
) {
517 // The Value and Offset may differ due to CSE. But the flags and size
518 // should be the same.
519 assert(MMO
->getFlags() == getFlags() && "Flags mismatch!");
520 assert(MMO
->getSize() == getSize() && "Size mismatch!");
522 if (MMO
->getBaseAlignment() >= getBaseAlignment()) {
523 // Update the alignment value.
524 Flags
= (Flags
& ((1 << MOMaxBits
) - 1)) |
525 ((Log2_32(MMO
->getBaseAlignment()) + 1) << MOMaxBits
);
526 // Also update the base and offset, because the new alignment may
527 // not be applicable with the old ones.
528 PtrInfo
= MMO
->PtrInfo
;
532 /// getAlignment - Return the minimum known alignment in bytes of the
533 /// actual memory reference.
534 uint64_t MachineMemOperand::getAlignment() const {
535 return MinAlign(getBaseAlignment(), getOffset());
538 void MachineMemOperand::print(raw_ostream
&OS
) const {
539 ModuleSlotTracker
DummyMST(nullptr);
542 void MachineMemOperand::print(raw_ostream
&OS
, ModuleSlotTracker
&MST
) const {
543 assert((isLoad() || isStore()) &&
544 "SV has to be a load, store or both.");
555 // Print the address information.
557 if (const Value
*V
= getValue())
558 V
->printAsOperand(OS
, /*PrintType=*/false, MST
);
559 else if (const PseudoSourceValue
*PSV
= getPseudoValue())
560 PSV
->printCustom(OS
);
564 unsigned AS
= getAddrSpace();
566 OS
<< "(addrspace=" << AS
<< ')';
568 // If the alignment of the memory reference itself differs from the alignment
569 // of the base pointer, print the base alignment explicitly, next to the base
571 if (getBaseAlignment() != getAlignment())
572 OS
<< "(align=" << getBaseAlignment() << ")";
574 if (getOffset() != 0)
575 OS
<< "+" << getOffset();
578 // Print the alignment of the reference.
579 if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
580 OS
<< "(align=" << getAlignment() << ")";
583 if (const MDNode
*TBAAInfo
= getAAInfo().TBAA
) {
585 if (TBAAInfo
->getNumOperands() > 0)
586 TBAAInfo
->getOperand(0)->printAsOperand(OS
, MST
);
592 // Print AA scope info.
593 if (const MDNode
*ScopeInfo
= getAAInfo().Scope
) {
594 OS
<< "(alias.scope=";
595 if (ScopeInfo
->getNumOperands() > 0)
596 for (unsigned i
= 0, ie
= ScopeInfo
->getNumOperands(); i
!= ie
; ++i
) {
597 ScopeInfo
->getOperand(i
)->printAsOperand(OS
, MST
);
606 // Print AA noalias scope info.
607 if (const MDNode
*NoAliasInfo
= getAAInfo().NoAlias
) {
609 if (NoAliasInfo
->getNumOperands() > 0)
610 for (unsigned i
= 0, ie
= NoAliasInfo
->getNumOperands(); i
!= ie
; ++i
) {
611 NoAliasInfo
->getOperand(i
)->printAsOperand(OS
, MST
);
620 // Print nontemporal info.
622 OS
<< "(nontemporal)";
628 //===----------------------------------------------------------------------===//
629 // MachineInstr Implementation
630 //===----------------------------------------------------------------------===//
632 void MachineInstr::addImplicitDefUseOperands(MachineFunction
&MF
) {
633 if (MCID
->ImplicitDefs
)
634 for (const uint16_t *ImpDefs
= MCID
->getImplicitDefs(); *ImpDefs
; ++ImpDefs
)
635 addOperand(MF
, MachineOperand::CreateReg(*ImpDefs
, true, true));
636 if (MCID
->ImplicitUses
)
637 for (const uint16_t *ImpUses
= MCID
->getImplicitUses(); *ImpUses
; ++ImpUses
)
638 addOperand(MF
, MachineOperand::CreateReg(*ImpUses
, false, true));
641 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
642 /// implicit operands. It reserves space for the number of operands specified by
644 MachineInstr::MachineInstr(MachineFunction
&MF
, const MCInstrDesc
&tid
,
645 DebugLoc dl
, bool NoImp
)
646 : MCID(&tid
), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0),
647 AsmPrinterFlags(0), NumMemRefs(0), MemRefs(nullptr),
648 debugLoc(std::move(dl
)) {
649 assert(debugLoc
.hasTrivialDestructor() && "Expected trivial destructor");
651 // Reserve space for the expected number of operands.
652 if (unsigned NumOps
= MCID
->getNumOperands() +
653 MCID
->getNumImplicitDefs() + MCID
->getNumImplicitUses()) {
654 CapOperands
= OperandCapacity::get(NumOps
);
655 Operands
= MF
.allocateOperandArray(CapOperands
);
659 addImplicitDefUseOperands(MF
);
662 /// MachineInstr ctor - Copies MachineInstr arg exactly
664 MachineInstr::MachineInstr(MachineFunction
&MF
, const MachineInstr
&MI
)
665 : MCID(&MI
.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
666 Flags(0), AsmPrinterFlags(0),
667 NumMemRefs(MI
.NumMemRefs
), MemRefs(MI
.MemRefs
),
668 debugLoc(MI
.getDebugLoc()) {
669 assert(debugLoc
.hasTrivialDestructor() && "Expected trivial destructor");
671 CapOperands
= OperandCapacity::get(MI
.getNumOperands());
672 Operands
= MF
.allocateOperandArray(CapOperands
);
675 for (const MachineOperand
&MO
: MI
.operands())
678 // Copy all the sensible flags.
682 /// getRegInfo - If this instruction is embedded into a MachineFunction,
683 /// return the MachineRegisterInfo object for the current function, otherwise
685 MachineRegisterInfo
*MachineInstr::getRegInfo() {
686 if (MachineBasicBlock
*MBB
= getParent())
687 return &MBB
->getParent()->getRegInfo();
691 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
692 /// this instruction from their respective use lists. This requires that the
693 /// operands already be on their use lists.
694 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo
&MRI
) {
695 for (MachineOperand
&MO
: operands())
697 MRI
.removeRegOperandFromUseList(&MO
);
700 /// AddRegOperandsToUseLists - Add all of the register operands in
701 /// this instruction from their respective use lists. This requires that the
702 /// operands not be on their use lists yet.
703 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo
&MRI
) {
704 for (MachineOperand
&MO
: operands())
706 MRI
.addRegOperandToUseList(&MO
);
709 void MachineInstr::addOperand(const MachineOperand
&Op
) {
710 MachineBasicBlock
*MBB
= getParent();
711 assert(MBB
&& "Use MachineInstrBuilder to add operands to dangling instrs");
712 MachineFunction
*MF
= MBB
->getParent();
713 assert(MF
&& "Use MachineInstrBuilder to add operands to dangling instrs");
717 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
718 /// ranges. If MRI is non-null also update use-def chains.
719 static void moveOperands(MachineOperand
*Dst
, MachineOperand
*Src
,
720 unsigned NumOps
, MachineRegisterInfo
*MRI
) {
722 return MRI
->moveOperands(Dst
, Src
, NumOps
);
724 // MachineOperand is a trivially copyable type so we can just use memmove.
725 std::memmove(Dst
, Src
, NumOps
* sizeof(MachineOperand
));
728 /// addOperand - Add the specified operand to the instruction. If it is an
729 /// implicit operand, it is added to the end of the operand list. If it is
730 /// an explicit operand it is added at the end of the explicit operand list
731 /// (before the first implicit operand).
732 void MachineInstr::addOperand(MachineFunction
&MF
, const MachineOperand
&Op
) {
733 assert(MCID
&& "Cannot add operands before providing an instr descriptor");
735 // Check if we're adding one of our existing operands.
736 if (&Op
>= Operands
&& &Op
< Operands
+ NumOperands
) {
737 // This is unusual: MI->addOperand(MI->getOperand(i)).
738 // If adding Op requires reallocating or moving existing operands around,
739 // the Op reference could go stale. Support it by copying Op.
740 MachineOperand
CopyOp(Op
);
741 return addOperand(MF
, CopyOp
);
744 // Find the insert location for the new operand. Implicit registers go at
745 // the end, everything else goes before the implicit regs.
747 // FIXME: Allow mixed explicit and implicit operands on inline asm.
748 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
749 // implicit-defs, but they must not be moved around. See the FIXME in
751 unsigned OpNo
= getNumOperands();
752 bool isImpReg
= Op
.isReg() && Op
.isImplicit();
753 if (!isImpReg
&& !isInlineAsm()) {
754 while (OpNo
&& Operands
[OpNo
-1].isReg() && Operands
[OpNo
-1].isImplicit()) {
756 assert(!Operands
[OpNo
].isTied() && "Cannot move tied operands");
761 bool isMetaDataOp
= Op
.getType() == MachineOperand::MO_Metadata
;
762 // OpNo now points as the desired insertion point. Unless this is a variadic
763 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
764 // RegMask operands go between the explicit and implicit operands.
765 assert((isImpReg
|| Op
.isRegMask() || MCID
->isVariadic() ||
766 OpNo
< MCID
->getNumOperands() || isMetaDataOp
) &&
767 "Trying to add an operand to a machine instr that is already done!");
770 MachineRegisterInfo
*MRI
= getRegInfo();
772 // Determine if the Operands array needs to be reallocated.
773 // Save the old capacity and operand array.
774 OperandCapacity OldCap
= CapOperands
;
775 MachineOperand
*OldOperands
= Operands
;
776 if (!OldOperands
|| OldCap
.getSize() == getNumOperands()) {
777 CapOperands
= OldOperands
? OldCap
.getNext() : OldCap
.get(1);
778 Operands
= MF
.allocateOperandArray(CapOperands
);
779 // Move the operands before the insertion point.
781 moveOperands(Operands
, OldOperands
, OpNo
, MRI
);
784 // Move the operands following the insertion point.
785 if (OpNo
!= NumOperands
)
786 moveOperands(Operands
+ OpNo
+ 1, OldOperands
+ OpNo
, NumOperands
- OpNo
,
790 // Deallocate the old operand array.
791 if (OldOperands
!= Operands
&& OldOperands
)
792 MF
.deallocateOperandArray(OldCap
, OldOperands
);
794 // Copy Op into place. It still needs to be inserted into the MRI use lists.
795 MachineOperand
*NewMO
= new (Operands
+ OpNo
) MachineOperand(Op
);
796 NewMO
->ParentMI
= this;
798 // When adding a register operand, tell MRI about it.
799 if (NewMO
->isReg()) {
800 // Ensure isOnRegUseList() returns false, regardless of Op's status.
801 NewMO
->Contents
.Reg
.Prev
= nullptr;
802 // Ignore existing ties. This is not a property that can be copied.
804 // Add the new operand to MRI, but only for instructions in an MBB.
806 MRI
->addRegOperandToUseList(NewMO
);
807 // The MCID operand information isn't accurate until we start adding
808 // explicit operands. The implicit operands are added first, then the
809 // explicits are inserted before them.
811 // Tie uses to defs as indicated in MCInstrDesc.
812 if (NewMO
->isUse()) {
813 int DefIdx
= MCID
->getOperandConstraint(OpNo
, MCOI::TIED_TO
);
815 tieOperands(DefIdx
, OpNo
);
817 // If the register operand is flagged as early, mark the operand as such.
818 if (MCID
->getOperandConstraint(OpNo
, MCOI::EARLY_CLOBBER
) != -1)
819 NewMO
->setIsEarlyClobber(true);
824 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
825 /// fewer operand than it started with.
827 void MachineInstr::RemoveOperand(unsigned OpNo
) {
828 assert(OpNo
< getNumOperands() && "Invalid operand number");
829 untieRegOperand(OpNo
);
832 // Moving tied operands would break the ties.
833 for (unsigned i
= OpNo
+ 1, e
= getNumOperands(); i
!= e
; ++i
)
834 if (Operands
[i
].isReg())
835 assert(!Operands
[i
].isTied() && "Cannot move tied operands");
838 MachineRegisterInfo
*MRI
= getRegInfo();
839 if (MRI
&& Operands
[OpNo
].isReg())
840 MRI
->removeRegOperandFromUseList(Operands
+ OpNo
);
842 // Don't call the MachineOperand destructor. A lot of this code depends on
843 // MachineOperand having a trivial destructor anyway, and adding a call here
844 // wouldn't make it 'destructor-correct'.
846 if (unsigned N
= NumOperands
- 1 - OpNo
)
847 moveOperands(Operands
+ OpNo
, Operands
+ OpNo
+ 1, N
, MRI
);
851 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
852 /// This function should be used only occasionally. The setMemRefs function
853 /// is the primary method for setting up a MachineInstr's MemRefs list.
854 void MachineInstr::addMemOperand(MachineFunction
&MF
,
855 MachineMemOperand
*MO
) {
856 mmo_iterator OldMemRefs
= MemRefs
;
857 unsigned OldNumMemRefs
= NumMemRefs
;
859 unsigned NewNum
= NumMemRefs
+ 1;
860 mmo_iterator NewMemRefs
= MF
.allocateMemRefsArray(NewNum
);
862 std::copy(OldMemRefs
, OldMemRefs
+ OldNumMemRefs
, NewMemRefs
);
863 NewMemRefs
[NewNum
- 1] = MO
;
864 setMemRefs(NewMemRefs
, NewMemRefs
+ NewNum
);
867 bool MachineInstr::hasPropertyInBundle(unsigned Mask
, QueryType Type
) const {
868 assert(!isBundledWithPred() && "Must be called on bundle header");
869 for (MachineBasicBlock::const_instr_iterator MII
= getIterator();; ++MII
) {
870 if (MII
->getDesc().getFlags() & Mask
) {
871 if (Type
== AnyInBundle
)
874 if (Type
== AllInBundle
&& !MII
->isBundle())
877 // This was the last instruction in the bundle.
878 if (!MII
->isBundledWithSucc())
879 return Type
== AllInBundle
;
883 bool MachineInstr::isIdenticalTo(const MachineInstr
*Other
,
884 MICheckType Check
) const {
885 // If opcodes or number of operands are not the same then the two
886 // instructions are obviously not identical.
887 if (Other
->getOpcode() != getOpcode() ||
888 Other
->getNumOperands() != getNumOperands())
892 // Both instructions are bundles, compare MIs inside the bundle.
893 MachineBasicBlock::const_instr_iterator I1
= getIterator();
894 MachineBasicBlock::const_instr_iterator E1
= getParent()->instr_end();
895 MachineBasicBlock::const_instr_iterator I2
= Other
->getIterator();
896 MachineBasicBlock::const_instr_iterator E2
= Other
->getParent()->instr_end();
897 while (++I1
!= E1
&& I1
->isInsideBundle()) {
899 if (I2
== E2
|| !I2
->isInsideBundle() || !I1
->isIdenticalTo(&*I2
, Check
))
904 // Check operands to make sure they match.
905 for (unsigned i
= 0, e
= getNumOperands(); i
!= e
; ++i
) {
906 const MachineOperand
&MO
= getOperand(i
);
907 const MachineOperand
&OMO
= Other
->getOperand(i
);
909 if (!MO
.isIdenticalTo(OMO
))
914 // Clients may or may not want to ignore defs when testing for equality.
915 // For example, machine CSE pass only cares about finding common
916 // subexpressions, so it's safe to ignore virtual register defs.
918 if (Check
== IgnoreDefs
)
920 else if (Check
== IgnoreVRegDefs
) {
921 if (TargetRegisterInfo::isPhysicalRegister(MO
.getReg()) ||
922 TargetRegisterInfo::isPhysicalRegister(OMO
.getReg()))
923 if (MO
.getReg() != OMO
.getReg())
926 if (!MO
.isIdenticalTo(OMO
))
928 if (Check
== CheckKillDead
&& MO
.isDead() != OMO
.isDead())
932 if (!MO
.isIdenticalTo(OMO
))
934 if (Check
== CheckKillDead
&& MO
.isKill() != OMO
.isKill())
938 // If DebugLoc does not match then two dbg.values are not identical.
940 if (getDebugLoc() && Other
->getDebugLoc() &&
941 getDebugLoc() != Other
->getDebugLoc())
946 MachineInstr
*MachineInstr::removeFromParent() {
947 assert(getParent() && "Not embedded in a basic block!");
948 return getParent()->remove(this);
951 MachineInstr
*MachineInstr::removeFromBundle() {
952 assert(getParent() && "Not embedded in a basic block!");
953 return getParent()->remove_instr(this);
956 void MachineInstr::eraseFromParent() {
957 assert(getParent() && "Not embedded in a basic block!");
958 getParent()->erase(this);
961 void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
962 assert(getParent() && "Not embedded in a basic block!");
963 MachineBasicBlock
*MBB
= getParent();
964 MachineFunction
*MF
= MBB
->getParent();
965 assert(MF
&& "Not embedded in a function!");
967 MachineInstr
*MI
= (MachineInstr
*)this;
968 MachineRegisterInfo
&MRI
= MF
->getRegInfo();
970 for (const MachineOperand
&MO
: MI
->operands()) {
971 if (!MO
.isReg() || !MO
.isDef())
973 unsigned Reg
= MO
.getReg();
974 if (!TargetRegisterInfo::isVirtualRegister(Reg
))
976 MRI
.markUsesInDebugValueAsUndef(Reg
);
978 MI
->eraseFromParent();
981 void MachineInstr::eraseFromBundle() {
982 assert(getParent() && "Not embedded in a basic block!");
983 getParent()->erase_instr(this);
986 /// getNumExplicitOperands - Returns the number of non-implicit operands.
988 unsigned MachineInstr::getNumExplicitOperands() const {
989 unsigned NumOperands
= MCID
->getNumOperands();
990 if (!MCID
->isVariadic())
993 for (unsigned i
= NumOperands
, e
= getNumOperands(); i
!= e
; ++i
) {
994 const MachineOperand
&MO
= getOperand(i
);
995 if (!MO
.isReg() || !MO
.isImplicit())
1001 void MachineInstr::bundleWithPred() {
1002 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
1003 setFlag(BundledPred
);
1004 MachineBasicBlock::instr_iterator Pred
= getIterator();
1006 assert(!Pred
->isBundledWithSucc() && "Inconsistent bundle flags");
1007 Pred
->setFlag(BundledSucc
);
1010 void MachineInstr::bundleWithSucc() {
1011 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
1012 setFlag(BundledSucc
);
1013 MachineBasicBlock::instr_iterator Succ
= getIterator();
1015 assert(!Succ
->isBundledWithPred() && "Inconsistent bundle flags");
1016 Succ
->setFlag(BundledPred
);
1019 void MachineInstr::unbundleFromPred() {
1020 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
1021 clearFlag(BundledPred
);
1022 MachineBasicBlock::instr_iterator Pred
= getIterator();
1024 assert(Pred
->isBundledWithSucc() && "Inconsistent bundle flags");
1025 Pred
->clearFlag(BundledSucc
);
1028 void MachineInstr::unbundleFromSucc() {
1029 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
1030 clearFlag(BundledSucc
);
1031 MachineBasicBlock::instr_iterator Succ
= getIterator();
1033 assert(Succ
->isBundledWithPred() && "Inconsistent bundle flags");
1034 Succ
->clearFlag(BundledPred
);
1037 bool MachineInstr::isStackAligningInlineAsm() const {
1038 if (isInlineAsm()) {
1039 unsigned ExtraInfo
= getOperand(InlineAsm::MIOp_ExtraInfo
).getImm();
1040 if (ExtraInfo
& InlineAsm::Extra_IsAlignStack
)
1046 InlineAsm::AsmDialect
MachineInstr::getInlineAsmDialect() const {
1047 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
1048 unsigned ExtraInfo
= getOperand(InlineAsm::MIOp_ExtraInfo
).getImm();
1049 return InlineAsm::AsmDialect((ExtraInfo
& InlineAsm::Extra_AsmDialect
) != 0);
1052 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx
,
1053 unsigned *GroupNo
) const {
1054 assert(isInlineAsm() && "Expected an inline asm instruction");
1055 assert(OpIdx
< getNumOperands() && "OpIdx out of range");
1057 // Ignore queries about the initial operands.
1058 if (OpIdx
< InlineAsm::MIOp_FirstOperand
)
1063 for (unsigned i
= InlineAsm::MIOp_FirstOperand
, e
= getNumOperands(); i
< e
;
1065 const MachineOperand
&FlagMO
= getOperand(i
);
1066 // If we reach the implicit register operands, stop looking.
1067 if (!FlagMO
.isImm())
1069 NumOps
= 1 + InlineAsm::getNumOperandRegisters(FlagMO
.getImm());
1070 if (i
+ NumOps
> OpIdx
) {
1080 const TargetRegisterClass
*
1081 MachineInstr::getRegClassConstraint(unsigned OpIdx
,
1082 const TargetInstrInfo
*TII
,
1083 const TargetRegisterInfo
*TRI
) const {
1084 assert(getParent() && "Can't have an MBB reference here!");
1085 assert(getParent()->getParent() && "Can't have an MF reference here!");
1086 const MachineFunction
&MF
= *getParent()->getParent();
1088 // Most opcodes have fixed constraints in their MCInstrDesc.
1090 return TII
->getRegClass(getDesc(), OpIdx
, TRI
, MF
);
1092 if (!getOperand(OpIdx
).isReg())
1095 // For tied uses on inline asm, get the constraint from the def.
1097 if (getOperand(OpIdx
).isUse() && isRegTiedToDefOperand(OpIdx
, &DefIdx
))
1100 // Inline asm stores register class constraints in the flag word.
1101 int FlagIdx
= findInlineAsmFlagIdx(OpIdx
);
1105 unsigned Flag
= getOperand(FlagIdx
).getImm();
1107 if (InlineAsm::hasRegClassConstraint(Flag
, RCID
))
1108 return TRI
->getRegClass(RCID
);
1110 // Assume that all registers in a memory operand are pointers.
1111 if (InlineAsm::getKind(Flag
) == InlineAsm::Kind_Mem
)
1112 return TRI
->getPointerRegClass(MF
);
1117 const TargetRegisterClass
*MachineInstr::getRegClassConstraintEffectForVReg(
1118 unsigned Reg
, const TargetRegisterClass
*CurRC
, const TargetInstrInfo
*TII
,
1119 const TargetRegisterInfo
*TRI
, bool ExploreBundle
) const {
1120 // Check every operands inside the bundle if we have
1123 for (ConstMIBundleOperands
OpndIt(this); OpndIt
.isValid() && CurRC
;
1125 CurRC
= OpndIt
->getParent()->getRegClassConstraintEffectForVRegImpl(
1126 OpndIt
.getOperandNo(), Reg
, CurRC
, TII
, TRI
);
1128 // Otherwise, just check the current operands.
1129 for (unsigned i
= 0, e
= NumOperands
; i
< e
&& CurRC
; ++i
)
1130 CurRC
= getRegClassConstraintEffectForVRegImpl(i
, Reg
, CurRC
, TII
, TRI
);
1134 const TargetRegisterClass
*MachineInstr::getRegClassConstraintEffectForVRegImpl(
1135 unsigned OpIdx
, unsigned Reg
, const TargetRegisterClass
*CurRC
,
1136 const TargetInstrInfo
*TII
, const TargetRegisterInfo
*TRI
) const {
1137 assert(CurRC
&& "Invalid initial register class");
1138 // Check if Reg is constrained by some of its use/def from MI.
1139 const MachineOperand
&MO
= getOperand(OpIdx
);
1140 if (!MO
.isReg() || MO
.getReg() != Reg
)
1142 // If yes, accumulate the constraints through the operand.
1143 return getRegClassConstraintEffect(OpIdx
, CurRC
, TII
, TRI
);
1146 const TargetRegisterClass
*MachineInstr::getRegClassConstraintEffect(
1147 unsigned OpIdx
, const TargetRegisterClass
*CurRC
,
1148 const TargetInstrInfo
*TII
, const TargetRegisterInfo
*TRI
) const {
1149 const TargetRegisterClass
*OpRC
= getRegClassConstraint(OpIdx
, TII
, TRI
);
1150 const MachineOperand
&MO
= getOperand(OpIdx
);
1151 assert(MO
.isReg() &&
1152 "Cannot get register constraints for non-register operand");
1153 assert(CurRC
&& "Invalid initial register class");
1154 if (unsigned SubIdx
= MO
.getSubReg()) {
1156 CurRC
= TRI
->getMatchingSuperRegClass(CurRC
, OpRC
, SubIdx
);
1158 CurRC
= TRI
->getSubClassWithSubReg(CurRC
, SubIdx
);
1160 CurRC
= TRI
->getCommonSubClass(CurRC
, OpRC
);
1164 /// Return the number of instructions inside the MI bundle, not counting the
1165 /// header instruction.
1166 unsigned MachineInstr::getBundleSize() const {
1167 MachineBasicBlock::const_instr_iterator I
= getIterator();
1169 while (I
->isBundledWithSucc())
1174 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1175 /// the specific register or -1 if it is not found. It further tightens
1176 /// the search criteria to a use that kills the register if isKill is true.
1177 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg
, bool isKill
,
1178 const TargetRegisterInfo
*TRI
) const {
1179 for (unsigned i
= 0, e
= getNumOperands(); i
!= e
; ++i
) {
1180 const MachineOperand
&MO
= getOperand(i
);
1181 if (!MO
.isReg() || !MO
.isUse())
1183 unsigned MOReg
= MO
.getReg();
1188 TargetRegisterInfo::isPhysicalRegister(MOReg
) &&
1189 TargetRegisterInfo::isPhysicalRegister(Reg
) &&
1190 TRI
->isSubRegister(MOReg
, Reg
)))
1191 if (!isKill
|| MO
.isKill())
1197 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1198 /// indicating if this instruction reads or writes Reg. This also considers
1199 /// partial defines.
1200 std::pair
<bool,bool>
1201 MachineInstr::readsWritesVirtualRegister(unsigned Reg
,
1202 SmallVectorImpl
<unsigned> *Ops
) const {
1203 bool PartDef
= false; // Partial redefine.
1204 bool FullDef
= false; // Full define.
1207 for (unsigned i
= 0, e
= getNumOperands(); i
!= e
; ++i
) {
1208 const MachineOperand
&MO
= getOperand(i
);
1209 if (!MO
.isReg() || MO
.getReg() != Reg
)
1214 Use
|= !MO
.isUndef();
1215 else if (MO
.getSubReg() && !MO
.isUndef())
1216 // A partial <def,undef> doesn't count as reading the register.
1221 // A partial redefine uses Reg unless there is also a full define.
1222 return std::make_pair(Use
|| (PartDef
&& !FullDef
), PartDef
|| FullDef
);
1225 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1226 /// the specified register or -1 if it is not found. If isDead is true, defs
1227 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1228 /// also checks if there is a def of a super-register.
1230 MachineInstr::findRegisterDefOperandIdx(unsigned Reg
, bool isDead
, bool Overlap
,
1231 const TargetRegisterInfo
*TRI
) const {
1232 bool isPhys
= TargetRegisterInfo::isPhysicalRegister(Reg
);
1233 for (unsigned i
= 0, e
= getNumOperands(); i
!= e
; ++i
) {
1234 const MachineOperand
&MO
= getOperand(i
);
1235 // Accept regmask operands when Overlap is set.
1236 // Ignore them when looking for a specific def operand (Overlap == false).
1237 if (isPhys
&& Overlap
&& MO
.isRegMask() && MO
.clobbersPhysReg(Reg
))
1239 if (!MO
.isReg() || !MO
.isDef())
1241 unsigned MOReg
= MO
.getReg();
1242 bool Found
= (MOReg
== Reg
);
1243 if (!Found
&& TRI
&& isPhys
&&
1244 TargetRegisterInfo::isPhysicalRegister(MOReg
)) {
1246 Found
= TRI
->regsOverlap(MOReg
, Reg
);
1248 Found
= TRI
->isSubRegister(MOReg
, Reg
);
1250 if (Found
&& (!isDead
|| MO
.isDead()))
1256 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1257 /// operand list that is used to represent the predicate. It returns -1 if
1259 int MachineInstr::findFirstPredOperandIdx() const {
1260 // Don't call MCID.findFirstPredOperandIdx() because this variant
1261 // is sometimes called on an instruction that's not yet complete, and
1262 // so the number of operands is less than the MCID indicates. In
1263 // particular, the PTX target does this.
1264 const MCInstrDesc
&MCID
= getDesc();
1265 if (MCID
.isPredicable()) {
1266 for (unsigned i
= 0, e
= getNumOperands(); i
!= e
; ++i
)
1267 if (MCID
.OpInfo
[i
].isPredicate())
1274 // MachineOperand::TiedTo is 4 bits wide.
1275 const unsigned TiedMax
= 15;
1277 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1279 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1280 /// field. TiedTo can have these values:
1282 /// 0: Operand is not tied to anything.
1283 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1284 /// TiedMax: Tied to an operand >= TiedMax-1.
1286 /// The tied def must be one of the first TiedMax operands on a normal
1287 /// instruction. INLINEASM instructions allow more tied defs.
1289 void MachineInstr::tieOperands(unsigned DefIdx
, unsigned UseIdx
) {
1290 MachineOperand
&DefMO
= getOperand(DefIdx
);
1291 MachineOperand
&UseMO
= getOperand(UseIdx
);
1292 assert(DefMO
.isDef() && "DefIdx must be a def operand");
1293 assert(UseMO
.isUse() && "UseIdx must be a use operand");
1294 assert(!DefMO
.isTied() && "Def is already tied to another use");
1295 assert(!UseMO
.isTied() && "Use is already tied to another def");
1297 if (DefIdx
< TiedMax
)
1298 UseMO
.TiedTo
= DefIdx
+ 1;
1300 // Inline asm can use the group descriptors to find tied operands, but on
1301 // normal instruction, the tied def must be within the first TiedMax
1303 assert(isInlineAsm() && "DefIdx out of range");
1304 UseMO
.TiedTo
= TiedMax
;
1307 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1308 DefMO
.TiedTo
= std::min(UseIdx
+ 1, TiedMax
);
1311 /// Given the index of a tied register operand, find the operand it is tied to.
1312 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1313 /// which must exist.
1314 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx
) const {
1315 const MachineOperand
&MO
= getOperand(OpIdx
);
1316 assert(MO
.isTied() && "Operand isn't tied");
1318 // Normally TiedTo is in range.
1319 if (MO
.TiedTo
< TiedMax
)
1320 return MO
.TiedTo
- 1;
1322 // Uses on normal instructions can be out of range.
1323 if (!isInlineAsm()) {
1324 // Normal tied defs must be in the 0..TiedMax-1 range.
1327 // MO is a def. Search for the tied use.
1328 for (unsigned i
= TiedMax
- 1, e
= getNumOperands(); i
!= e
; ++i
) {
1329 const MachineOperand
&UseMO
= getOperand(i
);
1330 if (UseMO
.isReg() && UseMO
.isUse() && UseMO
.TiedTo
== OpIdx
+ 1)
1333 llvm_unreachable("Can't find tied use");
1336 // Now deal with inline asm by parsing the operand group descriptor flags.
1337 // Find the beginning of each operand group.
1338 SmallVector
<unsigned, 8> GroupIdx
;
1339 unsigned OpIdxGroup
= ~0u;
1341 for (unsigned i
= InlineAsm::MIOp_FirstOperand
, e
= getNumOperands(); i
< e
;
1343 const MachineOperand
&FlagMO
= getOperand(i
);
1344 assert(FlagMO
.isImm() && "Invalid tied operand on inline asm");
1345 unsigned CurGroup
= GroupIdx
.size();
1346 GroupIdx
.push_back(i
);
1347 NumOps
= 1 + InlineAsm::getNumOperandRegisters(FlagMO
.getImm());
1348 // OpIdx belongs to this operand group.
1349 if (OpIdx
> i
&& OpIdx
< i
+ NumOps
)
1350 OpIdxGroup
= CurGroup
;
1352 if (!InlineAsm::isUseOperandTiedToDef(FlagMO
.getImm(), TiedGroup
))
1354 // Operands in this group are tied to operands in TiedGroup which must be
1355 // earlier. Find the number of operands between the two groups.
1356 unsigned Delta
= i
- GroupIdx
[TiedGroup
];
1358 // OpIdx is a use tied to TiedGroup.
1359 if (OpIdxGroup
== CurGroup
)
1360 return OpIdx
- Delta
;
1362 // OpIdx is a def tied to this use group.
1363 if (OpIdxGroup
== TiedGroup
)
1364 return OpIdx
+ Delta
;
1366 llvm_unreachable("Invalid tied operand on inline asm");
1369 /// clearKillInfo - Clears kill flags on all operands.
1371 void MachineInstr::clearKillInfo() {
1372 for (MachineOperand
&MO
: operands()) {
1373 if (MO
.isReg() && MO
.isUse())
1374 MO
.setIsKill(false);
1378 void MachineInstr::substituteRegister(unsigned FromReg
,
1381 const TargetRegisterInfo
&RegInfo
) {
1382 if (TargetRegisterInfo::isPhysicalRegister(ToReg
)) {
1384 ToReg
= RegInfo
.getSubReg(ToReg
, SubIdx
);
1385 for (MachineOperand
&MO
: operands()) {
1386 if (!MO
.isReg() || MO
.getReg() != FromReg
)
1388 MO
.substPhysReg(ToReg
, RegInfo
);
1391 for (MachineOperand
&MO
: operands()) {
1392 if (!MO
.isReg() || MO
.getReg() != FromReg
)
1394 MO
.substVirtReg(ToReg
, SubIdx
, RegInfo
);
1399 /// isSafeToMove - Return true if it is safe to move this instruction. If
1400 /// SawStore is set to true, it means that there is a store (or call) between
1401 /// the instruction's location and its intended destination.
1402 bool MachineInstr::isSafeToMove(AliasAnalysis
*AA
, bool &SawStore
) const {
1403 // Ignore stuff that we obviously can't move.
1405 // Treat volatile loads as stores. This is not strictly necessary for
1406 // volatiles, but it is required for atomic loads. It is not allowed to move
1407 // a load across an atomic load with Ordering > Monotonic.
1408 if (mayStore() || isCall() ||
1409 (mayLoad() && hasOrderedMemoryRef())) {
1414 if (isPosition() || isDebugValue() || isTerminator() ||
1415 hasUnmodeledSideEffects())
1418 // See if this instruction does a load. If so, we have to guarantee that the
1419 // loaded value doesn't change between the load and the its intended
1420 // destination. The check for isInvariantLoad gives the targe the chance to
1421 // classify the load as always returning a constant, e.g. a constant pool
1423 if (mayLoad() && !isInvariantLoad(AA
))
1424 // Otherwise, this is a real load. If there is a store between the load and
1425 // end of block, we can't move it.
1431 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1432 /// or volatile memory reference, or if the information describing the memory
1433 /// reference is not available. Return false if it is known to have no ordered
1434 /// memory references.
1435 bool MachineInstr::hasOrderedMemoryRef() const {
1436 // An instruction known never to access memory won't have a volatile access.
1440 !hasUnmodeledSideEffects())
1443 // Otherwise, if the instruction has no memory reference information,
1444 // conservatively assume it wasn't preserved.
1445 if (memoperands_empty())
1448 // Check the memory reference information for ordered references.
1449 for (mmo_iterator I
= memoperands_begin(), E
= memoperands_end(); I
!= E
; ++I
)
1450 if (!(*I
)->isUnordered())
1456 /// isInvariantLoad - Return true if this instruction is loading from a
1457 /// location whose value is invariant across the function. For example,
1458 /// loading a value from the constant pool or from the argument area
1459 /// of a function if it does not change. This should only return true of
1460 /// *all* loads the instruction does are invariant (if it does multiple loads).
1461 bool MachineInstr::isInvariantLoad(AliasAnalysis
*AA
) const {
1462 // If the instruction doesn't load at all, it isn't an invariant load.
1466 // If the instruction has lost its memoperands, conservatively assume that
1467 // it may not be an invariant load.
1468 if (memoperands_empty())
1471 const MachineFrameInfo
*MFI
= getParent()->getParent()->getFrameInfo();
1473 for (mmo_iterator I
= memoperands_begin(),
1474 E
= memoperands_end(); I
!= E
; ++I
) {
1475 if ((*I
)->isVolatile()) return false;
1476 if ((*I
)->isStore()) return false;
1477 if ((*I
)->isInvariant()) return true;
1480 // A load from a constant PseudoSourceValue is invariant.
1481 if (const PseudoSourceValue
*PSV
= (*I
)->getPseudoValue())
1482 if (PSV
->isConstant(MFI
))
1485 if (const Value
*V
= (*I
)->getValue()) {
1486 // If we have an AliasAnalysis, ask it whether the memory is constant.
1488 AA
->pointsToConstantMemory(
1489 MemoryLocation(V
, (*I
)->getSize(), (*I
)->getAAInfo())))
1493 // Otherwise assume conservatively.
1497 // Everything checks out.
1501 /// isConstantValuePHI - If the specified instruction is a PHI that always
1502 /// merges together the same virtual register, return the register, otherwise
1504 unsigned MachineInstr::isConstantValuePHI() const {
1507 assert(getNumOperands() >= 3 &&
1508 "It's illegal to have a PHI without source operands");
1510 unsigned Reg
= getOperand(1).getReg();
1511 for (unsigned i
= 3, e
= getNumOperands(); i
< e
; i
+= 2)
1512 if (getOperand(i
).getReg() != Reg
)
1517 bool MachineInstr::hasUnmodeledSideEffects() const {
1518 if (hasProperty(MCID::UnmodeledSideEffects
))
1520 if (isInlineAsm()) {
1521 unsigned ExtraInfo
= getOperand(InlineAsm::MIOp_ExtraInfo
).getImm();
1522 if (ExtraInfo
& InlineAsm::Extra_HasSideEffects
)
1529 bool MachineInstr::isLoadFoldBarrier() const {
1530 return mayStore() || isCall() || hasUnmodeledSideEffects();
1533 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1535 bool MachineInstr::allDefsAreDead() const {
1536 for (const MachineOperand
&MO
: operands()) {
1537 if (!MO
.isReg() || MO
.isUse())
1545 /// copyImplicitOps - Copy implicit register operands from specified
1546 /// instruction to this instruction.
1547 void MachineInstr::copyImplicitOps(MachineFunction
&MF
,
1548 const MachineInstr
*MI
) {
1549 for (unsigned i
= MI
->getDesc().getNumOperands(), e
= MI
->getNumOperands();
1551 const MachineOperand
&MO
= MI
->getOperand(i
);
1552 if ((MO
.isReg() && MO
.isImplicit()) || MO
.isRegMask())
1557 void MachineInstr::dump() const {
1558 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1559 dbgs() << " " << *this;
1563 void MachineInstr::print(raw_ostream
&OS
, bool SkipOpers
) const {
1564 const Module
*M
= nullptr;
1565 if (const MachineBasicBlock
*MBB
= getParent())
1566 if (const MachineFunction
*MF
= MBB
->getParent())
1567 M
= MF
->getFunction()->getParent();
1569 ModuleSlotTracker
MST(M
);
1570 print(OS
, MST
, SkipOpers
);
1573 void MachineInstr::print(raw_ostream
&OS
, ModuleSlotTracker
&MST
,
1574 bool SkipOpers
) const {
1575 // We can be a bit tidier if we know the MachineFunction.
1576 const MachineFunction
*MF
= nullptr;
1577 const TargetRegisterInfo
*TRI
= nullptr;
1578 const MachineRegisterInfo
*MRI
= nullptr;
1579 const TargetInstrInfo
*TII
= nullptr;
1580 if (const MachineBasicBlock
*MBB
= getParent()) {
1581 MF
= MBB
->getParent();
1583 MRI
= &MF
->getRegInfo();
1584 TRI
= MF
->getSubtarget().getRegisterInfo();
1585 TII
= MF
->getSubtarget().getInstrInfo();
1589 // Save a list of virtual registers.
1590 SmallVector
<unsigned, 8> VirtRegs
;
1592 // Print explicitly defined operands on the left of an assignment syntax.
1593 unsigned StartOp
= 0, e
= getNumOperands();
1594 for (; StartOp
< e
&& getOperand(StartOp
).isReg() &&
1595 getOperand(StartOp
).isDef() &&
1596 !getOperand(StartOp
).isImplicit();
1598 if (StartOp
!= 0) OS
<< ", ";
1599 getOperand(StartOp
).print(OS
, MST
, TRI
);
1600 unsigned Reg
= getOperand(StartOp
).getReg();
1601 if (TargetRegisterInfo::isVirtualRegister(Reg
))
1602 VirtRegs
.push_back(Reg
);
1608 // Print the opcode name.
1610 OS
<< TII
->getName(getOpcode());
1617 // Print the rest of the operands.
1618 bool OmittedAnyCallClobbers
= false;
1619 bool FirstOp
= true;
1620 unsigned AsmDescOp
= ~0u;
1621 unsigned AsmOpCount
= 0;
1623 if (isInlineAsm() && e
>= InlineAsm::MIOp_FirstOperand
) {
1624 // Print asm string.
1626 getOperand(InlineAsm::MIOp_AsmString
).print(OS
, MST
, TRI
);
1628 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1629 unsigned ExtraInfo
= getOperand(InlineAsm::MIOp_ExtraInfo
).getImm();
1630 if (ExtraInfo
& InlineAsm::Extra_HasSideEffects
)
1631 OS
<< " [sideeffect]";
1632 if (ExtraInfo
& InlineAsm::Extra_MayLoad
)
1634 if (ExtraInfo
& InlineAsm::Extra_MayStore
)
1635 OS
<< " [maystore]";
1636 if (ExtraInfo
& InlineAsm::Extra_IsAlignStack
)
1637 OS
<< " [alignstack]";
1638 if (getInlineAsmDialect() == InlineAsm::AD_ATT
)
1639 OS
<< " [attdialect]";
1640 if (getInlineAsmDialect() == InlineAsm::AD_Intel
)
1641 OS
<< " [inteldialect]";
1643 StartOp
= AsmDescOp
= InlineAsm::MIOp_FirstOperand
;
1647 for (unsigned i
= StartOp
, e
= getNumOperands(); i
!= e
; ++i
) {
1648 const MachineOperand
&MO
= getOperand(i
);
1650 if (MO
.isReg() && TargetRegisterInfo::isVirtualRegister(MO
.getReg()))
1651 VirtRegs
.push_back(MO
.getReg());
1653 // Omit call-clobbered registers which aren't used anywhere. This makes
1654 // call instructions much less noisy on targets where calls clobber lots
1655 // of registers. Don't rely on MO.isDead() because we may be called before
1656 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1657 if (MRI
&& isCall() &&
1658 MO
.isReg() && MO
.isImplicit() && MO
.isDef()) {
1659 unsigned Reg
= MO
.getReg();
1660 if (TargetRegisterInfo::isPhysicalRegister(Reg
)) {
1661 if (MRI
->use_empty(Reg
)) {
1662 bool HasAliasLive
= false;
1663 for (MCRegAliasIterator
AI(Reg
, TRI
, true); AI
.isValid(); ++AI
) {
1664 unsigned AliasReg
= *AI
;
1665 if (!MRI
->use_empty(AliasReg
)) {
1666 HasAliasLive
= true;
1670 if (!HasAliasLive
) {
1671 OmittedAnyCallClobbers
= true;
1678 if (FirstOp
) FirstOp
= false; else OS
<< ",";
1680 if (i
< getDesc().NumOperands
) {
1681 const MCOperandInfo
&MCOI
= getDesc().OpInfo
[i
];
1682 if (MCOI
.isPredicate())
1684 if (MCOI
.isOptionalDef())
1687 if (isDebugValue() && MO
.isMetadata()) {
1688 // Pretty print DBG_VALUE instructions.
1689 auto *DIV
= dyn_cast
<DILocalVariable
>(MO
.getMetadata());
1690 if (DIV
&& !DIV
->getName().empty())
1691 OS
<< "!\"" << DIV
->getName() << '\"';
1693 MO
.print(OS
, MST
, TRI
);
1694 } else if (TRI
&& (isInsertSubreg() || isRegSequence()) && MO
.isImm()) {
1695 OS
<< TRI
->getSubRegIndexName(MO
.getImm());
1696 } else if (i
== AsmDescOp
&& MO
.isImm()) {
1697 // Pretty print the inline asm operand descriptor.
1698 OS
<< '$' << AsmOpCount
++;
1699 unsigned Flag
= MO
.getImm();
1700 switch (InlineAsm::getKind(Flag
)) {
1701 case InlineAsm::Kind_RegUse
: OS
<< ":[reguse"; break;
1702 case InlineAsm::Kind_RegDef
: OS
<< ":[regdef"; break;
1703 case InlineAsm::Kind_RegDefEarlyClobber
: OS
<< ":[regdef-ec"; break;
1704 case InlineAsm::Kind_Clobber
: OS
<< ":[clobber"; break;
1705 case InlineAsm::Kind_Imm
: OS
<< ":[imm"; break;
1706 case InlineAsm::Kind_Mem
: OS
<< ":[mem"; break;
1707 default: OS
<< ":[??" << InlineAsm::getKind(Flag
); break;
1711 if (InlineAsm::hasRegClassConstraint(Flag
, RCID
)) {
1713 OS
<< ':' << TRI
->getRegClassName(TRI
->getRegClass(RCID
));
1715 OS
<< ":RC" << RCID
;
1718 unsigned TiedTo
= 0;
1719 if (InlineAsm::isUseOperandTiedToDef(Flag
, TiedTo
))
1720 OS
<< " tiedto:$" << TiedTo
;
1724 // Compute the index of the next operand descriptor.
1725 AsmDescOp
+= 1 + InlineAsm::getNumOperandRegisters(Flag
);
1727 MO
.print(OS
, MST
, TRI
);
1730 // Briefly indicate whether any call clobbers were omitted.
1731 if (OmittedAnyCallClobbers
) {
1732 if (!FirstOp
) OS
<< ",";
1736 bool HaveSemi
= false;
1737 const unsigned PrintableFlags
= FrameSetup
| FrameDestroy
;
1738 if (Flags
& PrintableFlags
) {
1739 if (!HaveSemi
) OS
<< ";"; HaveSemi
= true;
1742 if (Flags
& FrameSetup
)
1745 if (Flags
& FrameDestroy
)
1746 OS
<< "FrameDestroy";
1749 if (!memoperands_empty()) {
1750 if (!HaveSemi
) OS
<< ";"; HaveSemi
= true;
1753 for (mmo_iterator i
= memoperands_begin(), e
= memoperands_end();
1755 (*i
)->print(OS
, MST
);
1756 if (std::next(i
) != e
)
1761 // Print the regclass of any virtual registers encountered.
1762 if (MRI
&& !VirtRegs
.empty()) {
1763 if (!HaveSemi
) OS
<< ";"; HaveSemi
= true;
1764 for (unsigned i
= 0; i
!= VirtRegs
.size(); ++i
) {
1765 const TargetRegisterClass
*RC
= MRI
->getRegClass(VirtRegs
[i
]);
1766 OS
<< " " << TRI
->getRegClassName(RC
)
1767 << ':' << PrintReg(VirtRegs
[i
]);
1768 for (unsigned j
= i
+1; j
!= VirtRegs
.size();) {
1769 if (MRI
->getRegClass(VirtRegs
[j
]) != RC
) {
1773 if (VirtRegs
[i
] != VirtRegs
[j
])
1774 OS
<< "," << PrintReg(VirtRegs
[j
]);
1775 VirtRegs
.erase(VirtRegs
.begin()+j
);
1780 // Print debug location information.
1781 if (isDebugValue() && getOperand(e
- 2).isMetadata()) {
1782 if (!HaveSemi
) OS
<< ";";
1783 auto *DV
= cast
<DILocalVariable
>(getOperand(e
- 2).getMetadata());
1784 OS
<< " line no:" << DV
->getLine();
1785 if (auto *InlinedAt
= debugLoc
->getInlinedAt()) {
1786 DebugLoc
InlinedAtDL(InlinedAt
);
1787 if (InlinedAtDL
&& MF
) {
1788 OS
<< " inlined @[ ";
1789 InlinedAtDL
.print(OS
);
1793 if (isIndirectDebugValue())
1795 } else if (debugLoc
&& MF
) {
1796 if (!HaveSemi
) OS
<< ";";
1804 bool MachineInstr::addRegisterKilled(unsigned IncomingReg
,
1805 const TargetRegisterInfo
*RegInfo
,
1806 bool AddIfNotFound
) {
1807 bool isPhysReg
= TargetRegisterInfo::isPhysicalRegister(IncomingReg
);
1808 bool hasAliases
= isPhysReg
&&
1809 MCRegAliasIterator(IncomingReg
, RegInfo
, false).isValid();
1811 SmallVector
<unsigned,4> DeadOps
;
1812 for (unsigned i
= 0, e
= getNumOperands(); i
!= e
; ++i
) {
1813 MachineOperand
&MO
= getOperand(i
);
1814 if (!MO
.isReg() || !MO
.isUse() || MO
.isUndef())
1816 unsigned Reg
= MO
.getReg();
1820 if (Reg
== IncomingReg
) {
1823 // The register is already marked kill.
1825 if (isPhysReg
&& isRegTiedToDefOperand(i
))
1826 // Two-address uses of physregs must not be marked kill.
1831 } else if (hasAliases
&& MO
.isKill() &&
1832 TargetRegisterInfo::isPhysicalRegister(Reg
)) {
1833 // A super-register kill already exists.
1834 if (RegInfo
->isSuperRegister(IncomingReg
, Reg
))
1836 if (RegInfo
->isSubRegister(IncomingReg
, Reg
))
1837 DeadOps
.push_back(i
);
1841 // Trim unneeded kill operands.
1842 while (!DeadOps
.empty()) {
1843 unsigned OpIdx
= DeadOps
.back();
1844 if (getOperand(OpIdx
).isImplicit())
1845 RemoveOperand(OpIdx
);
1847 getOperand(OpIdx
).setIsKill(false);
1851 // If not found, this means an alias of one of the operands is killed. Add a
1852 // new implicit operand if required.
1853 if (!Found
&& AddIfNotFound
) {
1854 addOperand(MachineOperand::CreateReg(IncomingReg
,
1863 void MachineInstr::clearRegisterKills(unsigned Reg
,
1864 const TargetRegisterInfo
*RegInfo
) {
1865 if (!TargetRegisterInfo::isPhysicalRegister(Reg
))
1867 for (MachineOperand
&MO
: operands()) {
1868 if (!MO
.isReg() || !MO
.isUse() || !MO
.isKill())
1870 unsigned OpReg
= MO
.getReg();
1871 if (OpReg
== Reg
|| (RegInfo
&& RegInfo
->isSuperRegister(Reg
, OpReg
)))
1872 MO
.setIsKill(false);
1876 bool MachineInstr::addRegisterDead(unsigned Reg
,
1877 const TargetRegisterInfo
*RegInfo
,
1878 bool AddIfNotFound
) {
1879 bool isPhysReg
= TargetRegisterInfo::isPhysicalRegister(Reg
);
1880 bool hasAliases
= isPhysReg
&&
1881 MCRegAliasIterator(Reg
, RegInfo
, false).isValid();
1883 SmallVector
<unsigned,4> DeadOps
;
1884 for (unsigned i
= 0, e
= getNumOperands(); i
!= e
; ++i
) {
1885 MachineOperand
&MO
= getOperand(i
);
1886 if (!MO
.isReg() || !MO
.isDef())
1888 unsigned MOReg
= MO
.getReg();
1895 } else if (hasAliases
&& MO
.isDead() &&
1896 TargetRegisterInfo::isPhysicalRegister(MOReg
)) {
1897 // There exists a super-register that's marked dead.
1898 if (RegInfo
->isSuperRegister(Reg
, MOReg
))
1900 if (RegInfo
->isSubRegister(Reg
, MOReg
))
1901 DeadOps
.push_back(i
);
1905 // Trim unneeded dead operands.
1906 while (!DeadOps
.empty()) {
1907 unsigned OpIdx
= DeadOps
.back();
1908 if (getOperand(OpIdx
).isImplicit())
1909 RemoveOperand(OpIdx
);
1911 getOperand(OpIdx
).setIsDead(false);
1915 // If not found, this means an alias of one of the operands is dead. Add a
1916 // new implicit operand if required.
1917 if (Found
|| !AddIfNotFound
)
1920 addOperand(MachineOperand::CreateReg(Reg
,
1928 void MachineInstr::clearRegisterDeads(unsigned Reg
) {
1929 for (MachineOperand
&MO
: operands()) {
1930 if (!MO
.isReg() || !MO
.isDef() || MO
.getReg() != Reg
)
1932 MO
.setIsDead(false);
1936 void MachineInstr::setRegisterDefReadUndef(unsigned Reg
, bool IsUndef
) {
1937 for (MachineOperand
&MO
: operands()) {
1938 if (!MO
.isReg() || !MO
.isDef() || MO
.getReg() != Reg
|| MO
.getSubReg() == 0)
1940 MO
.setIsUndef(IsUndef
);
1944 void MachineInstr::addRegisterDefined(unsigned Reg
,
1945 const TargetRegisterInfo
*RegInfo
) {
1946 if (TargetRegisterInfo::isPhysicalRegister(Reg
)) {
1947 MachineOperand
*MO
= findRegisterDefOperand(Reg
, false, RegInfo
);
1951 for (const MachineOperand
&MO
: operands()) {
1952 if (MO
.isReg() && MO
.getReg() == Reg
&& MO
.isDef() &&
1953 MO
.getSubReg() == 0)
1957 addOperand(MachineOperand::CreateReg(Reg
,
1962 void MachineInstr::setPhysRegsDeadExcept(ArrayRef
<unsigned> UsedRegs
,
1963 const TargetRegisterInfo
&TRI
) {
1964 bool HasRegMask
= false;
1965 for (MachineOperand
&MO
: operands()) {
1966 if (MO
.isRegMask()) {
1970 if (!MO
.isReg() || !MO
.isDef()) continue;
1971 unsigned Reg
= MO
.getReg();
1972 if (!TargetRegisterInfo::isPhysicalRegister(Reg
)) continue;
1973 // If there are no uses, including partial uses, the def is dead.
1974 if (std::none_of(UsedRegs
.begin(), UsedRegs
.end(),
1975 [&](unsigned Use
) { return TRI
.regsOverlap(Use
, Reg
); }))
1979 // This is a call with a register mask operand.
1980 // Mask clobbers are always dead, so add defs for the non-dead defines.
1982 for (ArrayRef
<unsigned>::iterator I
= UsedRegs
.begin(), E
= UsedRegs
.end();
1984 addRegisterDefined(*I
, &TRI
);
1988 MachineInstrExpressionTrait::getHashValue(const MachineInstr
* const &MI
) {
1989 // Build up a buffer of hash code components.
1990 SmallVector
<size_t, 8> HashComponents
;
1991 HashComponents
.reserve(MI
->getNumOperands() + 1);
1992 HashComponents
.push_back(MI
->getOpcode());
1993 for (const MachineOperand
&MO
: MI
->operands()) {
1994 if (MO
.isReg() && MO
.isDef() &&
1995 TargetRegisterInfo::isVirtualRegister(MO
.getReg()))
1996 continue; // Skip virtual register defs.
1998 HashComponents
.push_back(hash_value(MO
));
2000 return hash_combine_range(HashComponents
.begin(), HashComponents
.end());
2003 void MachineInstr::emitError(StringRef Msg
) const {
2004 // Find the source location cookie.
2005 unsigned LocCookie
= 0;
2006 const MDNode
*LocMD
= nullptr;
2007 for (unsigned i
= getNumOperands(); i
!= 0; --i
) {
2008 if (getOperand(i
-1).isMetadata() &&
2009 (LocMD
= getOperand(i
-1).getMetadata()) &&
2010 LocMD
->getNumOperands() != 0) {
2011 if (const ConstantInt
*CI
=
2012 mdconst::dyn_extract
<ConstantInt
>(LocMD
->getOperand(0))) {
2013 LocCookie
= CI
->getZExtValue();
2019 if (const MachineBasicBlock
*MBB
= getParent())
2020 if (const MachineFunction
*MF
= MBB
->getParent())
2021 return MF
->getMMI().getModule()->getContext().emitError(LocCookie
, Msg
);
2022 report_fatal_error(Msg
);