lib/CodeGen/DFAPacketizer.cpp

   1 //=- llvm/CodeGen/DFAPacketizer.cpp - DFA Packetizer for VLIW -*- C++ -*-=====//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This class implements a deterministic finite automaton (DFA) based
  10 // packetizing mechanism for VLIW architectures. It provides APIs to
  11 // determine whether there exists a legal mapping of instructions to
  12 // functional unit assignments in a packet. The DFA is auto-generated from
  13 // the target's Schedule.td file.
  14 //
  15 // A DFA consists of 3 major elements: states, inputs, and transitions. For
  16 // the packetizing mechanism, the input is the set of instruction classes for
  17 // a target. The state models all possible combinations of functional unit
  18 // consumption for a given set of instructions in a packet. A transition
  19 // models the addition of an instruction to a packet. In the DFA constructed
  20 // by this class, if an instruction can be added to a packet, then a valid
  21 // transition exists from the corresponding state. Invalid transitions
  22 // indicate that the instruction cannot be added to the current packet.
  23 //
  24 //===----------------------------------------------------------------------===//
  25
  26 #include "llvm/CodeGen/DFAPacketizer.h"
  27 #include "llvm/CodeGen/MachineInstr.h"
  28 #include "llvm/CodeGen/MachineInstrBundle.h"
  29 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
  30 #include "llvm/MC/MCInstrItineraries.h"
  31 #include "llvm/Target/TargetInstrInfo.h"
  32 using namespace llvm;
  33
  34 DFAPacketizer::DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2],
  35                              const unsigned *SET):
  36   InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
  37   DFAStateEntryTable(SET) {}
  38
  39
  40 //
  41 // ReadTable - Read the DFA transition table and update CachedTable.
  42 //
  43 // Format of the transition tables:
  44 // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
  45 //                           transitions
  46 // DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable
  47 //                         for the ith state
  48 //
  49 void DFAPacketizer::ReadTable(unsigned int state) {
  50   unsigned ThisState = DFAStateEntryTable[state];
  51   unsigned NextStateInTable = DFAStateEntryTable[state+1];
  52   // Early exit in case CachedTable has already contains this
  53   // state's transitions.
  54   if (CachedTable.count(UnsignPair(state,
  55                                    DFAStateInputTable[ThisState][0])))
  56     return;
  57
  58   for (unsigned i = ThisState; i < NextStateInTable; i++)
  59     CachedTable[UnsignPair(state, DFAStateInputTable[i][0])] =
  60       DFAStateInputTable[i][1];
  61 }
  62
  63
  64 // canReserveResources - Check if the resources occupied by a MCInstrDesc
  65 // are available in the current state.
  66 bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) {
  67   unsigned InsnClass = MID->getSchedClass();
  68   const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
  69   unsigned FuncUnits = IS->getUnits();
  70   UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
  71   ReadTable(CurrentState);
  72   return (CachedTable.count(StateTrans) != 0);
  73 }
  74
  75
  76 // reserveResources - Reserve the resources occupied by a MCInstrDesc and
  77 // change the current state to reflect that change.
  78 void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
  79   unsigned InsnClass = MID->getSchedClass();
  80   const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
  81   unsigned FuncUnits = IS->getUnits();
  82   UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
  83   ReadTable(CurrentState);
  84   assert(CachedTable.count(StateTrans) != 0);
  85   CurrentState = CachedTable[StateTrans];
  86 }
  87
  88
  89 // canReserveResources - Check if the resources occupied by a machine
  90 // instruction are available in the current state.
  91 bool DFAPacketizer::canReserveResources(llvm::MachineInstr *MI) {
  92   const llvm::MCInstrDesc &MID = MI->getDesc();
  93   return canReserveResources(&MID);
  94 }
  95
  96 // reserveResources - Reserve the resources occupied by a machine
  97 // instruction and change the current state to reflect that change.
  98 void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) {
  99   const llvm::MCInstrDesc &MID = MI->getDesc();
 100   reserveResources(&MID);
 101 }
 102
 103 namespace llvm {
 104 // DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides
 105 // Schedule method to build the dependence graph.
 106 class DefaultVLIWScheduler : public ScheduleDAGInstrs {
 107 public:
 108   DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI);
 109   // Schedule - Actual scheduling work.
 110   void schedule() override;
 111 };
 112 }
 113
 114 DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF,
 115                                            MachineLoopInfo &MLI)
 116     : ScheduleDAGInstrs(MF, &MLI) {
 117   CanHandleTerminators = true;
 118 }
 119
 120 void DefaultVLIWScheduler::schedule() {
 121   // Build the scheduling graph.
 122   buildSchedGraph(nullptr);
 123 }
 124
 125 // VLIWPacketizerList Ctor
 126 VLIWPacketizerList::VLIWPacketizerList(MachineFunction &MF,
 127                                        MachineLoopInfo &MLI)
 128     : MF(MF) {
 129   TII = MF.getSubtarget().getInstrInfo();
 130   ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget());
 131   VLIWScheduler = new DefaultVLIWScheduler(MF, MLI);
 132 }
 133
 134 // VLIWPacketizerList Dtor
 135 VLIWPacketizerList::~VLIWPacketizerList() {
 136   if (VLIWScheduler)
 137     delete VLIWScheduler;
 138
 139   if (ResourceTracker)
 140     delete ResourceTracker;
 141 }
 142
 143 // endPacket - End the current packet, bundle packet instructions and reset
 144 // DFA state.
 145 void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
 146                                          MachineInstr *MI) {
 147   if (CurrentPacketMIs.size() > 1) {
 148     MachineInstr *MIFirst = CurrentPacketMIs.front();
 149     finalizeBundle(*MBB, MIFirst->getIterator(), MI->getIterator());
 150   }
 151   CurrentPacketMIs.clear();
 152   ResourceTracker->clearResources();
 153 }
 154
 155 // PacketizeMIs - Bundle machine instructions into packets.
 156 void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
 157                                       MachineBasicBlock::iterator BeginItr,
 158                                       MachineBasicBlock::iterator EndItr) {
 159   assert(VLIWScheduler && "VLIW Scheduler is not initialized!");
 160   VLIWScheduler->startBlock(MBB);
 161   VLIWScheduler->enterRegion(MBB, BeginItr, EndItr,
 162                              std::distance(BeginItr, EndItr));
 163   VLIWScheduler->schedule();
 164
 165   // Generate MI -> SU map.
 166   MIToSUnit.clear();
 167   for (unsigned i = 0, e = VLIWScheduler->SUnits.size(); i != e; ++i) {
 168     SUnit *SU = &VLIWScheduler->SUnits[i];
 169     MIToSUnit[SU->getInstr()] = SU;
 170   }
 171
 172   // The main packetizer loop.
 173   for (; BeginItr != EndItr; ++BeginItr) {
 174     MachineInstr *MI = BeginItr;
 175
 176     this->initPacketizerState();
 177
 178     // End the current packet if needed.
 179     if (this->isSoloInstruction(MI)) {
 180       endPacket(MBB, MI);
 181       continue;
 182     }
 183
 184     // Ignore pseudo instructions.
 185     if (this->ignorePseudoInstruction(MI, MBB))
 186       continue;
 187
 188     SUnit *SUI = MIToSUnit[MI];
 189     assert(SUI && "Missing SUnit Info!");
 190
 191     // Ask DFA if machine resource is available for MI.
 192     bool ResourceAvail = ResourceTracker->canReserveResources(MI);
 193     if (ResourceAvail) {
 194       // Dependency check for MI with instructions in CurrentPacketMIs.
 195       for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
 196            VE = CurrentPacketMIs.end(); VI != VE; ++VI) {
 197         MachineInstr *MJ = *VI;
 198         SUnit *SUJ = MIToSUnit[MJ];
 199         assert(SUJ && "Missing SUnit Info!");
 200
 201         // Is it legal to packetize SUI and SUJ together.
 202         if (!this->isLegalToPacketizeTogether(SUI, SUJ)) {
 203           // Allow packetization if dependency can be pruned.
 204           if (!this->isLegalToPruneDependencies(SUI, SUJ)) {
 205             // End the packet if dependency cannot be pruned.
 206             endPacket(MBB, MI);
 207             break;
 208           } // !isLegalToPruneDependencies.
 209         } // !isLegalToPacketizeTogether.
 210       } // For all instructions in CurrentPacketMIs.
 211     } else {
 212       // End the packet if resource is not available.
 213       endPacket(MBB, MI);
 214     }
 215
 216     // Add MI to the current packet.
 217     BeginItr = this->addToPacket(MI);
 218   } // For all instructions in BB.
 219
 220   // End any packet left behind.
 221   endPacket(MBB, EndItr);
 222   VLIWScheduler->exitRegion();
 223   VLIWScheduler->finishBlock();
 224 }