utils/TableGen/X86EVEX2VEXTablesEmitter.cpp

   1 //===- utils/TableGen/X86EVEX2VEXTablesEmitter.cpp - X86 backend-*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// This tablegen backend is responsible for emitting the X86 backend EVEX2VEX
  10 /// compression tables.
  11 ///
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "CodeGenTarget.h"
  15 #include "llvm/TableGen/Error.h"
  16 #include "llvm/TableGen/TableGenBackend.h"
  17
  18 using namespace llvm;
  19
  20 namespace {
  21
  22 class X86EVEX2VEXTablesEmitter {
  23   RecordKeeper &Records;
  24   CodeGenTarget Target;
  25
  26   // Hold all non-masked & non-broadcasted EVEX encoded instructions
  27   std::vector<const CodeGenInstruction *> EVEXInsts;
  28   // Hold all VEX encoded instructions. Divided into groups with same opcodes
  29   // to make the search more efficient
  30   std::map<uint64_t, std::vector<const CodeGenInstruction *>> VEXInsts;
  31
  32   typedef std::pair<const CodeGenInstruction *, const CodeGenInstruction *> Entry;
  33
  34   // Represent both compress tables
  35   std::vector<Entry> EVEX2VEX128;
  36   std::vector<Entry> EVEX2VEX256;
  37
  38 public:
  39   X86EVEX2VEXTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {}
  40
  41   // run - Output X86 EVEX2VEX tables.
  42   void run(raw_ostream &OS);
  43
  44 private:
  45   // Prints the given table as a C++ array of type
  46   // X86EvexToVexCompressTableEntry
  47   void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
  48 };
  49
  50 void X86EVEX2VEXTablesEmitter::printTable(const std::vector<Entry> &Table,
  51                                           raw_ostream &OS) {
  52   StringRef Size = (Table == EVEX2VEX128) ? "128" : "256";
  53
  54   OS << "// X86 EVEX encoded instructions that have a VEX " << Size
  55      << " encoding\n"
  56      << "// (table format: <EVEX opcode, VEX-" << Size << " opcode>).\n"
  57      << "static const X86EvexToVexCompressTableEntry X86EvexToVex" << Size
  58      << "CompressTable[] = {\n"
  59      << "  // EVEX scalar with corresponding VEX.\n";
  60
  61   // Print all entries added to the table
  62   for (auto Pair : Table) {
  63     OS << "  { X86::" << Pair.first->TheDef->getName()
  64        << ", X86::" << Pair.second->TheDef->getName() << " },\n";
  65   }
  66
  67   OS << "};\n\n";
  68 }
  69
  70 // Return true if the 2 BitsInits are equal
  71 // Calculates the integer value residing BitsInit object
  72 static inline uint64_t getValueFromBitsInit(const BitsInit *B) {
  73   uint64_t Value = 0;
  74   for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
  75     if (BitInit *Bit = dyn_cast<BitInit>(B->getBit(i)))
  76       Value |= uint64_t(Bit->getValue()) << i;
  77     else
  78       PrintFatalError("Invalid VectSize bit");
  79   }
  80   return Value;
  81 }
  82
  83 // Function object - Operator() returns true if the given VEX instruction
  84 // matches the EVEX instruction of this object.
  85 class IsMatch {
  86   const CodeGenInstruction *EVEXInst;
  87
  88 public:
  89   IsMatch(const CodeGenInstruction *EVEXInst) : EVEXInst(EVEXInst) {}
  90
  91   bool operator()(const CodeGenInstruction *VEXInst) {
  92     Record *RecE = EVEXInst->TheDef;
  93     Record *RecV = VEXInst->TheDef;
  94     bool EVEX_W = RecE->getValueAsBit("HasVEX_W");
  95     bool VEX_W  = RecV->getValueAsBit("HasVEX_W");
  96     bool VEX_WIG  = RecV->getValueAsBit("IgnoresVEX_W");
  97     bool EVEX_WIG = RecE->getValueAsBit("IgnoresVEX_W");
  98     bool EVEX_W1_VEX_W0 = RecE->getValueAsBit("EVEX_W1_VEX_W0");
  99
 100     if (RecV->getValueAsDef("OpEnc")->getName().str() != "EncVEX" ||
 101         RecV->getValueAsBit("isCodeGenOnly") != RecE->getValueAsBit("isCodeGenOnly") ||
 102         // VEX/EVEX fields
 103         RecV->getValueAsDef("OpPrefix") != RecE->getValueAsDef("OpPrefix") ||
 104         RecV->getValueAsDef("OpMap") != RecE->getValueAsDef("OpMap") ||
 105         RecV->getValueAsBit("hasVEX_4V") != RecE->getValueAsBit("hasVEX_4V") ||
 106         RecV->getValueAsBit("hasEVEX_L2") != RecE->getValueAsBit("hasEVEX_L2") ||
 107         RecV->getValueAsBit("hasVEX_L") != RecE->getValueAsBit("hasVEX_L") ||
 108         // Match is allowed if either is VEX_WIG, or they match, or EVEX
 109         // is VEX_W1X and VEX is VEX_W0.
 110         (!(VEX_WIG || (!EVEX_WIG && EVEX_W == VEX_W) ||
 111            (EVEX_W1_VEX_W0 && EVEX_W && !VEX_W))) ||
 112         // Instruction's format
 113         RecV->getValueAsDef("Form") != RecE->getValueAsDef("Form"))
 114       return false;
 115
 116     // This is needed for instructions with intrinsic version (_Int).
 117     // Where the only difference is the size of the operands.
 118     // For example: VUCOMISDZrm and Int_VUCOMISDrm
 119     // Also for instructions that their EVEX version was upgraded to work with
 120     // k-registers. For example VPCMPEQBrm (xmm output register) and
 121     // VPCMPEQBZ128rm (k register output register).
 122     for (unsigned i = 0, e = EVEXInst->Operands.size(); i < e; i++) {
 123       Record *OpRec1 = EVEXInst->Operands[i].Rec;
 124       Record *OpRec2 = VEXInst->Operands[i].Rec;
 125
 126       if (OpRec1 == OpRec2)
 127         continue;
 128
 129       if (isRegisterOperand(OpRec1) && isRegisterOperand(OpRec2)) {
 130         if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
 131           return false;
 132       } else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
 133         return false;
 134       } else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
 135         if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type")) {
 136           return false;
 137         }
 138       } else
 139         return false;
 140     }
 141
 142     return true;
 143   }
 144
 145 private:
 146   static inline bool isRegisterOperand(const Record *Rec) {
 147     return Rec->isSubClassOf("RegisterClass") ||
 148            Rec->isSubClassOf("RegisterOperand");
 149   }
 150
 151   static inline bool isMemoryOperand(const Record *Rec) {
 152     return Rec->isSubClassOf("Operand") &&
 153            Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
 154   }
 155
 156   static inline bool isImmediateOperand(const Record *Rec) {
 157     return Rec->isSubClassOf("Operand") &&
 158            Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
 159   }
 160
 161   static inline unsigned int getRegOperandSize(const Record *RegRec) {
 162     if (RegRec->isSubClassOf("RegisterClass"))
 163       return RegRec->getValueAsInt("Alignment");
 164     if (RegRec->isSubClassOf("RegisterOperand"))
 165       return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment");
 166
 167     llvm_unreachable("Register operand's size not known!");
 168   }
 169 };
 170
 171 void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
 172   emitSourceFileHeader("X86 EVEX2VEX tables", OS);
 173
 174   ArrayRef<const CodeGenInstruction *> NumberedInstructions =
 175       Target.getInstructionsByEnumValue();
 176
 177   for (const CodeGenInstruction *Inst : NumberedInstructions) {
 178     // Filter non-X86 instructions.
 179     if (!Inst->TheDef->isSubClassOf("X86Inst"))
 180       continue;
 181
 182     // Add VEX encoded instructions to one of VEXInsts vectors according to
 183     // it's opcode.
 184     if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncVEX") {
 185       uint64_t Opcode = getValueFromBitsInit(Inst->TheDef->
 186                                              getValueAsBitsInit("Opcode"));
 187       VEXInsts[Opcode].push_back(Inst);
 188     }
 189     // Add relevant EVEX encoded instructions to EVEXInsts
 190     else if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncEVEX" &&
 191              !Inst->TheDef->getValueAsBit("hasEVEX_K") &&
 192              !Inst->TheDef->getValueAsBit("hasEVEX_B") &&
 193              !Inst->TheDef->getValueAsBit("hasEVEX_L2") &&
 194              !Inst->TheDef->getValueAsBit("notEVEX2VEXConvertible"))
 195       EVEXInsts.push_back(Inst);
 196   }
 197
 198   for (const CodeGenInstruction *EVEXInst : EVEXInsts) {
 199     uint64_t Opcode = getValueFromBitsInit(EVEXInst->TheDef->
 200                                            getValueAsBitsInit("Opcode"));
 201     // For each EVEX instruction look for a VEX match in the appropriate vector
 202     // (instructions with the same opcode) using function object IsMatch.
 203     // Allow EVEX2VEXOverride to explicitly specify a match.
 204     const CodeGenInstruction *VEXInst = nullptr;
 205     if (!EVEXInst->TheDef->isValueUnset("EVEX2VEXOverride")) {
 206       StringRef AltInstStr =
 207         EVEXInst->TheDef->getValueAsString("EVEX2VEXOverride");
 208       Record *AltInstRec = Records.getDef(AltInstStr);
 209       assert(AltInstRec && "EVEX2VEXOverride instruction not found!");
 210       VEXInst = &Target.getInstruction(AltInstRec);
 211     } else {
 212       auto Match = llvm::find_if(VEXInsts[Opcode], IsMatch(EVEXInst));
 213       if (Match != VEXInsts[Opcode].end())
 214         VEXInst = *Match;
 215     }
 216
 217     if (!VEXInst)
 218       continue;
 219
 220     // In case a match is found add new entry to the appropriate table
 221     if (EVEXInst->TheDef->getValueAsBit("hasVEX_L"))
 222       EVEX2VEX256.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,1}
 223     else
 224       EVEX2VEX128.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,0}
 225   }
 226
 227   // Print both tables
 228   printTable(EVEX2VEX128, OS);
 229   printTable(EVEX2VEX256, OS);
 230 }
 231 }
 232
 233 namespace llvm {
 234 void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS) {
 235   X86EVEX2VEXTablesEmitter(RK).run(OS);
 236 }
 237 }