Merge tag 'io_uring-6.11-20240802' of git://git.kernel.dk/linux
[linux.git] / drivers / pwm / pwm-stmpe.c
blobbb91062d5f1da1ec9a311e3340415fe8618ee8cc
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2016 Linaro Ltd.
5 * Author: Linus Walleij <linus.walleij@linaro.org>
6 */
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/err.h>
11 #include <linux/mfd/stmpe.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/pwm.h>
16 #include <linux/slab.h>
18 #define STMPE24XX_PWMCS 0x30
19 #define PWMCS_EN_PWM0 BIT(0)
20 #define PWMCS_EN_PWM1 BIT(1)
21 #define PWMCS_EN_PWM2 BIT(2)
22 #define STMPE24XX_PWMIC0 0x38
23 #define STMPE24XX_PWMIC1 0x39
24 #define STMPE24XX_PWMIC2 0x3a
26 #define STMPE_PWM_24XX_PINBASE 21
28 struct stmpe_pwm {
29 struct stmpe *stmpe;
30 u8 last_duty;
33 static inline struct stmpe_pwm *to_stmpe_pwm(struct pwm_chip *chip)
35 return pwmchip_get_drvdata(chip);
38 static int stmpe_24xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
40 struct stmpe_pwm *stmpe_pwm = to_stmpe_pwm(chip);
41 u8 value;
42 int ret;
44 ret = stmpe_reg_read(stmpe_pwm->stmpe, STMPE24XX_PWMCS);
45 if (ret < 0) {
46 dev_dbg(pwmchip_parent(chip), "error reading PWM#%u control\n",
47 pwm->hwpwm);
48 return ret;
51 value = ret | BIT(pwm->hwpwm);
53 ret = stmpe_reg_write(stmpe_pwm->stmpe, STMPE24XX_PWMCS, value);
54 if (ret) {
55 dev_dbg(pwmchip_parent(chip), "error writing PWM#%u control\n",
56 pwm->hwpwm);
57 return ret;
60 return 0;
63 static int stmpe_24xx_pwm_disable(struct pwm_chip *chip,
64 struct pwm_device *pwm)
66 struct stmpe_pwm *stmpe_pwm = to_stmpe_pwm(chip);
67 u8 value;
68 int ret;
70 ret = stmpe_reg_read(stmpe_pwm->stmpe, STMPE24XX_PWMCS);
71 if (ret < 0) {
72 dev_dbg(pwmchip_parent(chip), "error reading PWM#%u control\n",
73 pwm->hwpwm);
74 return ret;
77 value = ret & ~BIT(pwm->hwpwm);
79 ret = stmpe_reg_write(stmpe_pwm->stmpe, STMPE24XX_PWMCS, value);
80 if (ret)
81 dev_dbg(pwmchip_parent(chip), "error writing PWM#%u control\n",
82 pwm->hwpwm);
83 return ret;
86 /* STMPE 24xx PWM instructions */
87 #define SMAX 0x007f
88 #define SMIN 0x00ff
89 #define GTS 0x0000
90 #define LOAD BIT(14) /* Only available on 2403 */
91 #define RAMPUP 0x0000
92 #define RAMPDOWN BIT(7)
93 #define PRESCALE_512 BIT(14)
94 #define STEPTIME_1 BIT(8)
95 #define BRANCH (BIT(15) | BIT(13))
97 static int stmpe_24xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
98 int duty_ns, int period_ns)
100 struct stmpe_pwm *stmpe_pwm = to_stmpe_pwm(chip);
101 unsigned int i, pin;
102 u16 program[3] = {
103 SMAX,
104 GTS,
105 GTS,
107 u8 offset;
108 int ret;
110 /* Make sure we are disabled */
111 if (pwm_is_enabled(pwm)) {
112 ret = stmpe_24xx_pwm_disable(chip, pwm);
113 if (ret)
114 return ret;
115 } else {
116 /* Connect the PWM to the pin */
117 pin = pwm->hwpwm;
119 /* On STMPE2401 and 2403 pins 21,22,23 are used */
120 if (stmpe_pwm->stmpe->partnum == STMPE2401 ||
121 stmpe_pwm->stmpe->partnum == STMPE2403)
122 pin += STMPE_PWM_24XX_PINBASE;
124 ret = stmpe_set_altfunc(stmpe_pwm->stmpe, BIT(pin),
125 STMPE_BLOCK_PWM);
126 if (ret) {
127 dev_err(pwmchip_parent(chip), "unable to connect PWM#%u to pin\n",
128 pwm->hwpwm);
129 return ret;
133 /* STMPE24XX */
134 switch (pwm->hwpwm) {
135 case 0:
136 offset = STMPE24XX_PWMIC0;
137 break;
139 case 1:
140 offset = STMPE24XX_PWMIC1;
141 break;
143 case 2:
144 offset = STMPE24XX_PWMIC2;
145 break;
147 default:
148 /* Should not happen as npwm is 3 */
149 return -ENODEV;
152 dev_dbg(pwmchip_parent(chip), "PWM#%u: config duty %d ns, period %d ns\n",
153 pwm->hwpwm, duty_ns, period_ns);
155 if (duty_ns == 0) {
156 if (stmpe_pwm->stmpe->partnum == STMPE2401)
157 program[0] = SMAX; /* off all the time */
159 if (stmpe_pwm->stmpe->partnum == STMPE2403)
160 program[0] = LOAD | 0xff; /* LOAD 0xff */
162 stmpe_pwm->last_duty = 0x00;
163 } else if (duty_ns == period_ns) {
164 if (stmpe_pwm->stmpe->partnum == STMPE2401)
165 program[0] = SMIN; /* on all the time */
167 if (stmpe_pwm->stmpe->partnum == STMPE2403)
168 program[0] = LOAD | 0x00; /* LOAD 0x00 */
170 stmpe_pwm->last_duty = 0xff;
171 } else {
172 u8 value, last = stmpe_pwm->last_duty;
173 unsigned long duty;
176 * Counter goes from 0x00 to 0xff repeatedly at 32768 Hz,
177 * (means a period of 30517 ns) then this is compared to the
178 * counter from the ramp, if this is >= PWM counter the output
179 * is high. With LOAD we can define how much of the cycle it
180 * is on.
182 * Prescale = 0 -> 2 kHz -> T = 1/f = 488281.25 ns
185 /* Scale to 0..0xff */
186 duty = duty_ns * 256;
187 duty = DIV_ROUND_CLOSEST(duty, period_ns);
188 value = duty;
190 if (value == last) {
191 /* Run the old program */
192 if (pwm_is_enabled(pwm))
193 stmpe_24xx_pwm_enable(chip, pwm);
195 return 0;
196 } else if (stmpe_pwm->stmpe->partnum == STMPE2403) {
197 /* STMPE2403 can simply set the right PWM value */
198 program[0] = LOAD | value;
199 program[1] = 0x0000;
200 } else if (stmpe_pwm->stmpe->partnum == STMPE2401) {
201 /* STMPE2401 need a complex program */
202 u16 incdec = 0x0000;
204 if (last < value)
205 /* Count up */
206 incdec = RAMPUP | (value - last);
207 else
208 /* Count down */
209 incdec = RAMPDOWN | (last - value);
211 /* Step to desired value, smoothly */
212 program[0] = PRESCALE_512 | STEPTIME_1 | incdec;
214 /* Loop eternally to 0x00 */
215 program[1] = BRANCH;
218 dev_dbg(pwmchip_parent(chip),
219 "PWM#%u: value = %02x, last_duty = %02x, program=%04x,%04x,%04x\n",
220 pwm->hwpwm, value, last, program[0], program[1],
221 program[2]);
222 stmpe_pwm->last_duty = value;
226 * We can write programs of up to 64 16-bit words into this channel.
228 for (i = 0; i < ARRAY_SIZE(program); i++) {
229 u8 value;
231 value = (program[i] >> 8) & 0xff;
233 ret = stmpe_reg_write(stmpe_pwm->stmpe, offset, value);
234 if (ret) {
235 dev_dbg(pwmchip_parent(chip), "error writing register %02x: %d\n",
236 offset, ret);
237 return ret;
240 value = program[i] & 0xff;
242 ret = stmpe_reg_write(stmpe_pwm->stmpe, offset, value);
243 if (ret) {
244 dev_dbg(pwmchip_parent(chip), "error writing register %02x: %d\n",
245 offset, ret);
246 return ret;
250 /* If we were enabled, re-enable this PWM */
251 if (pwm_is_enabled(pwm))
252 stmpe_24xx_pwm_enable(chip, pwm);
254 /* Sleep for 200ms so we're sure it will take effect */
255 msleep(200);
257 dev_dbg(pwmchip_parent(chip), "programmed PWM#%u, %u bytes\n", pwm->hwpwm, i);
259 return 0;
262 static int stmpe_24xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
263 const struct pwm_state *state)
265 int err;
267 if (state->polarity != PWM_POLARITY_NORMAL)
268 return -EINVAL;
270 if (!state->enabled) {
271 if (pwm->state.enabled)
272 return stmpe_24xx_pwm_disable(chip, pwm);
274 return 0;
277 err = stmpe_24xx_pwm_config(chip, pwm, state->duty_cycle, state->period);
278 if (err)
279 return err;
281 if (!pwm->state.enabled)
282 err = stmpe_24xx_pwm_enable(chip, pwm);
284 return err;
287 static const struct pwm_ops stmpe_24xx_pwm_ops = {
288 .apply = stmpe_24xx_pwm_apply,
291 static int __init stmpe_pwm_probe(struct platform_device *pdev)
293 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
294 struct pwm_chip *chip;
295 struct stmpe_pwm *stmpe_pwm;
296 int ret;
298 switch (stmpe->partnum) {
299 case STMPE2401:
300 case STMPE2403:
301 break;
302 case STMPE1601:
303 return dev_err_probe(&pdev->dev, -ENODEV,
304 "STMPE1601 not yet supported\n");
305 default:
306 return dev_err_probe(&pdev->dev, -ENODEV,
307 "Unknown STMPE PWM\n");
310 chip = devm_pwmchip_alloc(&pdev->dev, 3, sizeof(*stmpe_pwm));
311 if (IS_ERR(chip))
312 return PTR_ERR(chip);
313 stmpe_pwm = to_stmpe_pwm(chip);
315 stmpe_pwm->stmpe = stmpe;
317 chip->ops = &stmpe_24xx_pwm_ops;
319 ret = stmpe_enable(stmpe, STMPE_BLOCK_PWM);
320 if (ret)
321 return ret;
323 ret = pwmchip_add(chip);
324 if (ret) {
325 stmpe_disable(stmpe, STMPE_BLOCK_PWM);
326 return ret;
329 return 0;
332 static struct platform_driver stmpe_pwm_driver = {
333 .driver = {
334 .name = "stmpe-pwm",
337 builtin_platform_driver_probe(stmpe_pwm_driver, stmpe_pwm_probe);