drivers/edac/skx_common.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *
   4  * Shared code by both skx_edac and i10nm_edac. Originally split out
   5  * from the skx_edac driver.
   6  *
   7  * This file is linked into both skx_edac and i10nm_edac drivers. In
   8  * order to avoid link errors, this file must be like a pure library
   9  * without including symbols and defines which would otherwise conflict,
  10  * when linked once into a module and into a built-in object, at the
  11  * same time. For example, __this_module symbol references when that
  12  * file is being linked into a built-in object.
  13  *
  14  * Copyright (c) 2018, Intel Corporation.
  15  */
  16
  17 #include <linux/acpi.h>
  18 #include <linux/dmi.h>
  19 #include <linux/adxl.h>
  20 #include <acpi/nfit.h>
  21 #include <asm/mce.h>
  22 #include "edac_module.h"
  23 #include "skx_common.h"
  24
  25 static const char * const component_names[] = {
  26         [INDEX_SOCKET]          = "ProcessorSocketId",
  27         [INDEX_MEMCTRL]         = "MemoryControllerId",
  28         [INDEX_CHANNEL]         = "ChannelId",
  29         [INDEX_DIMM]            = "DimmSlotId",
  30         [INDEX_CS]              = "ChipSelect",
  31         [INDEX_NM_MEMCTRL]      = "NmMemoryControllerId",
  32         [INDEX_NM_CHANNEL]      = "NmChannelId",
  33         [INDEX_NM_DIMM]         = "NmDimmSlotId",
  34         [INDEX_NM_CS]           = "NmChipSelect",
  35 };
  36
  37 static int component_indices[ARRAY_SIZE(component_names)];
  38 static int adxl_component_count;
  39 static const char * const *adxl_component_names;
  40 static u64 *adxl_values;
  41 static char *adxl_msg;
  42 static unsigned long adxl_nm_bitmap;
  43
  44 static char skx_msg[MSG_SIZE];
  45 static skx_decode_f driver_decode;
  46 static skx_show_retry_log_f skx_show_retry_rd_err_log;
  47 static u64 skx_tolm, skx_tohm;
  48 static LIST_HEAD(dev_edac_list);
  49 static bool skx_mem_cfg_2lm;
  50
  51 int skx_adxl_get(void)
  52 {
  53         const char * const *names;
  54         int i, j;
  55
  56         names = adxl_get_component_names();
  57         if (!names) {
  58                 skx_printk(KERN_NOTICE, "No firmware support for address translation.\n");
  59                 return -ENODEV;
  60         }
  61
  62         for (i = 0; i < INDEX_MAX; i++) {
  63                 for (j = 0; names[j]; j++) {
  64                         if (!strcmp(component_names[i], names[j])) {
  65                                 component_indices[i] = j;
  66
  67                                 if (i >= INDEX_NM_FIRST)
  68                                         adxl_nm_bitmap |= 1 << i;
  69
  70                                 break;
  71                         }
  72                 }
  73
  74                 if (!names[j] && i < INDEX_NM_FIRST)
  75                         goto err;
  76         }
  77
  78         if (skx_mem_cfg_2lm) {
  79                 if (!adxl_nm_bitmap)
  80                         skx_printk(KERN_NOTICE, "Not enough ADXL components for 2-level memory.\n");
  81                 else
  82                         edac_dbg(2, "adxl_nm_bitmap: 0x%lx\n", adxl_nm_bitmap);
  83         }
  84
  85         adxl_component_names = names;
  86         while (*names++)
  87                 adxl_component_count++;
  88
  89         adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values),
  90                               GFP_KERNEL);
  91         if (!adxl_values) {
  92                 adxl_component_count = 0;
  93                 return -ENOMEM;
  94         }
  95
  96         adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL);
  97         if (!adxl_msg) {
  98                 adxl_component_count = 0;
  99                 kfree(adxl_values);
 100                 return -ENOMEM;
 101         }
 102
 103         return 0;
 104 err:
 105         skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ",
 106                    component_names[i]);
 107         for (j = 0; names[j]; j++)
 108                 skx_printk(KERN_CONT, "%s ", names[j]);
 109         skx_printk(KERN_CONT, "\n");
 110
 111         return -ENODEV;
 112 }
 113 EXPORT_SYMBOL_GPL(skx_adxl_get);
 114
 115 void skx_adxl_put(void)
 116 {
 117         kfree(adxl_values);
 118         kfree(adxl_msg);
 119 }
 120 EXPORT_SYMBOL_GPL(skx_adxl_put);
 121
 122 static bool skx_adxl_decode(struct decoded_addr *res, bool error_in_1st_level_mem)
 123 {
 124         struct skx_dev *d;
 125         int i, len = 0;
 126
 127         if (res->addr >= skx_tohm || (res->addr >= skx_tolm &&
 128                                       res->addr < BIT_ULL(32))) {
 129                 edac_dbg(0, "Address 0x%llx out of range\n", res->addr);
 130                 return false;
 131         }
 132
 133         if (adxl_decode(res->addr, adxl_values)) {
 134                 edac_dbg(0, "Failed to decode 0x%llx\n", res->addr);
 135                 return false;
 136         }
 137
 138         res->socket  = (int)adxl_values[component_indices[INDEX_SOCKET]];
 139         if (error_in_1st_level_mem) {
 140                 res->imc     = (adxl_nm_bitmap & BIT_NM_MEMCTRL) ?
 141                                (int)adxl_values[component_indices[INDEX_NM_MEMCTRL]] : -1;
 142                 res->channel = (adxl_nm_bitmap & BIT_NM_CHANNEL) ?
 143                                (int)adxl_values[component_indices[INDEX_NM_CHANNEL]] : -1;
 144                 res->dimm    = (adxl_nm_bitmap & BIT_NM_DIMM) ?
 145                                (int)adxl_values[component_indices[INDEX_NM_DIMM]] : -1;
 146                 res->cs      = (adxl_nm_bitmap & BIT_NM_CS) ?
 147                                (int)adxl_values[component_indices[INDEX_NM_CS]] : -1;
 148         } else {
 149                 res->imc     = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
 150                 res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]];
 151                 res->dimm    = (int)adxl_values[component_indices[INDEX_DIMM]];
 152                 res->cs      = (int)adxl_values[component_indices[INDEX_CS]];
 153         }
 154
 155         if (res->imc > NUM_IMC - 1 || res->imc < 0) {
 156                 skx_printk(KERN_ERR, "Bad imc %d\n", res->imc);
 157                 return false;
 158         }
 159
 160         list_for_each_entry(d, &dev_edac_list, list) {
 161                 if (d->imc[0].src_id == res->socket) {
 162                         res->dev = d;
 163                         break;
 164                 }
 165         }
 166
 167         if (!res->dev) {
 168                 skx_printk(KERN_ERR, "No device for src_id %d imc %d\n",
 169                            res->socket, res->imc);
 170                 return false;
 171         }
 172
 173         for (i = 0; i < adxl_component_count; i++) {
 174                 if (adxl_values[i] == ~0x0ull)
 175                         continue;
 176
 177                 len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx",
 178                                 adxl_component_names[i], adxl_values[i]);
 179                 if (MSG_SIZE - len <= 0)
 180                         break;
 181         }
 182
 183         res->decoded_by_adxl = true;
 184
 185         return true;
 186 }
 187
 188 void skx_set_mem_cfg(bool mem_cfg_2lm)
 189 {
 190         skx_mem_cfg_2lm = mem_cfg_2lm;
 191 }
 192 EXPORT_SYMBOL_GPL(skx_set_mem_cfg);
 193
 194 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log)
 195 {
 196         driver_decode = decode;
 197         skx_show_retry_rd_err_log = show_retry_log;
 198 }
 199 EXPORT_SYMBOL_GPL(skx_set_decode);
 200
 201 int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
 202 {
 203         u32 reg;
 204
 205         if (pci_read_config_dword(d->util_all, off, &reg)) {
 206                 skx_printk(KERN_ERR, "Failed to read src id\n");
 207                 return -ENODEV;
 208         }
 209
 210         *id = GET_BITFIELD(reg, 12, 14);
 211         return 0;
 212 }
 213 EXPORT_SYMBOL_GPL(skx_get_src_id);
 214
 215 int skx_get_node_id(struct skx_dev *d, u8 *id)
 216 {
 217         u32 reg;
 218
 219         if (pci_read_config_dword(d->util_all, 0xf4, &reg)) {
 220                 skx_printk(KERN_ERR, "Failed to read node id\n");
 221                 return -ENODEV;
 222         }
 223
 224         *id = GET_BITFIELD(reg, 0, 2);
 225         return 0;
 226 }
 227 EXPORT_SYMBOL_GPL(skx_get_node_id);
 228
 229 static int get_width(u32 mtr)
 230 {
 231         switch (GET_BITFIELD(mtr, 8, 9)) {
 232         case 0:
 233                 return DEV_X4;
 234         case 1:
 235                 return DEV_X8;
 236         case 2:
 237                 return DEV_X16;
 238         }
 239         return DEV_UNKNOWN;
 240 }
 241
 242 /*
 243  * We use the per-socket device @cfg->did to count how many sockets are present,
 244  * and to detemine which PCI buses are associated with each socket. Allocate
 245  * and build the full list of all the skx_dev structures that we need here.
 246  */
 247 int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list)
 248 {
 249         struct pci_dev *pdev, *prev;
 250         struct skx_dev *d;
 251         u32 reg;
 252         int ndev = 0;
 253
 254         prev = NULL;
 255         for (;;) {
 256                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, cfg->decs_did, prev);
 257                 if (!pdev)
 258                         break;
 259                 ndev++;
 260                 d = kzalloc(sizeof(*d), GFP_KERNEL);
 261                 if (!d) {
 262                         pci_dev_put(pdev);
 263                         return -ENOMEM;
 264                 }
 265
 266                 if (pci_read_config_dword(pdev, cfg->busno_cfg_offset, &reg)) {
 267                         kfree(d);
 268                         pci_dev_put(pdev);
 269                         skx_printk(KERN_ERR, "Failed to read bus idx\n");
 270                         return -ENODEV;
 271                 }
 272
 273                 d->bus[0] = GET_BITFIELD(reg, 0, 7);
 274                 d->bus[1] = GET_BITFIELD(reg, 8, 15);
 275                 if (cfg->type == SKX) {
 276                         d->seg = pci_domain_nr(pdev->bus);
 277                         d->bus[2] = GET_BITFIELD(reg, 16, 23);
 278                         d->bus[3] = GET_BITFIELD(reg, 24, 31);
 279                 } else {
 280                         d->seg = GET_BITFIELD(reg, 16, 23);
 281                 }
 282
 283                 edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n",
 284                          d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
 285                 list_add_tail(&d->list, &dev_edac_list);
 286                 prev = pdev;
 287         }
 288
 289         if (list)
 290                 *list = &dev_edac_list;
 291         return ndev;
 292 }
 293 EXPORT_SYMBOL_GPL(skx_get_all_bus_mappings);
 294
 295 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm)
 296 {
 297         struct pci_dev *pdev;
 298         u32 reg;
 299
 300         pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL);
 301         if (!pdev) {
 302                 edac_dbg(2, "Can't get tolm/tohm\n");
 303                 return -ENODEV;
 304         }
 305
 306         if (pci_read_config_dword(pdev, off[0], &reg)) {
 307                 skx_printk(KERN_ERR, "Failed to read tolm\n");
 308                 goto fail;
 309         }
 310         skx_tolm = reg;
 311
 312         if (pci_read_config_dword(pdev, off[1], &reg)) {
 313                 skx_printk(KERN_ERR, "Failed to read lower tohm\n");
 314                 goto fail;
 315         }
 316         skx_tohm = reg;
 317
 318         if (pci_read_config_dword(pdev, off[2], &reg)) {
 319                 skx_printk(KERN_ERR, "Failed to read upper tohm\n");
 320                 goto fail;
 321         }
 322         skx_tohm |= (u64)reg << 32;
 323
 324         pci_dev_put(pdev);
 325         *tolm = skx_tolm;
 326         *tohm = skx_tohm;
 327         edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm);
 328         return 0;
 329 fail:
 330         pci_dev_put(pdev);
 331         return -ENODEV;
 332 }
 333 EXPORT_SYMBOL_GPL(skx_get_hi_lo);
 334
 335 static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add,
 336                              int minval, int maxval, const char *name)
 337 {
 338         u32 val = GET_BITFIELD(reg, lobit, hibit);
 339
 340         if (val < minval || val > maxval) {
 341                 edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg);
 342                 return -EINVAL;
 343         }
 344         return val + add;
 345 }
 346
 347 #define numrank(reg)    skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks")
 348 #define numrow(reg)     skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows")
 349 #define numcol(reg)     skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols")
 350
 351 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
 352                       struct skx_imc *imc, int chan, int dimmno,
 353                       struct res_config *cfg)
 354 {
 355         int  banks, ranks, rows, cols, npages;
 356         enum mem_type mtype;
 357         u64 size;
 358
 359         ranks = numrank(mtr);
 360         rows = numrow(mtr);
 361         cols = imc->hbm_mc ? 6 : numcol(mtr);
 362
 363         if (imc->hbm_mc) {
 364                 banks = 32;
 365                 mtype = MEM_HBM2;
 366         } else if (cfg->support_ddr5) {
 367                 banks = 32;
 368                 mtype = MEM_DDR5;
 369         } else {
 370                 banks = 16;
 371                 mtype = MEM_DDR4;
 372         }
 373
 374         /*
 375          * Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
 376          */
 377         size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
 378         npages = MiB_TO_PAGES(size);
 379
 380         edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n",
 381                  imc->mc, chan, dimmno, size, npages,
 382                  banks, 1 << ranks, rows, cols);
 383
 384         imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0);
 385         imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mcmtr, 9, 9);
 386         imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
 387         imc->chan[chan].dimms[dimmno].rowbits = rows;
 388         imc->chan[chan].dimms[dimmno].colbits = cols;
 389
 390         dimm->nr_pages = npages;
 391         dimm->grain = 32;
 392         dimm->dtype = get_width(mtr);
 393         dimm->mtype = mtype;
 394         dimm->edac_mode = EDAC_SECDED; /* likely better than this */
 395
 396         if (imc->hbm_mc)
 397                 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_HBMC#%u_Chan#%u",
 398                          imc->src_id, imc->lmc, chan);
 399         else
 400                 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
 401                          imc->src_id, imc->lmc, chan, dimmno);
 402
 403         return 1;
 404 }
 405 EXPORT_SYMBOL_GPL(skx_get_dimm_info);
 406
 407 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
 408                         int chan, int dimmno, const char *mod_str)
 409 {
 410         int smbios_handle;
 411         u32 dev_handle;
 412         u16 flags;
 413         u64 size = 0;
 414
 415         dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc,
 416                                                    imc->src_id, 0);
 417
 418         smbios_handle = nfit_get_smbios_id(dev_handle, &flags);
 419         if (smbios_handle == -EOPNOTSUPP) {
 420                 pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str);
 421                 goto unknown_size;
 422         }
 423
 424         if (smbios_handle < 0) {
 425                 skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle);
 426                 goto unknown_size;
 427         }
 428
 429         if (flags & ACPI_NFIT_MEM_MAP_FAILED) {
 430                 skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle);
 431                 goto unknown_size;
 432         }
 433
 434         size = dmi_memdev_size(smbios_handle);
 435         if (size == ~0ull)
 436                 skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n",
 437                            dev_handle, smbios_handle);
 438
 439 unknown_size:
 440         dimm->nr_pages = size >> PAGE_SHIFT;
 441         dimm->grain = 32;
 442         dimm->dtype = DEV_UNKNOWN;
 443         dimm->mtype = MEM_NVDIMM;
 444         dimm->edac_mode = EDAC_SECDED; /* likely better than this */
 445
 446         edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n",
 447                  imc->mc, chan, dimmno, size >> 20, dimm->nr_pages);
 448
 449         snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
 450                  imc->src_id, imc->lmc, chan, dimmno);
 451
 452         return (size == 0 || size == ~0ull) ? 0 : 1;
 453 }
 454 EXPORT_SYMBOL_GPL(skx_get_nvdimm_info);
 455
 456 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
 457                      const char *ctl_name, const char *mod_str,
 458                      get_dimm_config_f get_dimm_config,
 459                      struct res_config *cfg)
 460 {
 461         struct mem_ctl_info *mci;
 462         struct edac_mc_layer layers[2];
 463         struct skx_pvt *pvt;
 464         int rc;
 465
 466         /* Allocate a new MC control structure */
 467         layers[0].type = EDAC_MC_LAYER_CHANNEL;
 468         layers[0].size = NUM_CHANNELS;
 469         layers[0].is_virt_csrow = false;
 470         layers[1].type = EDAC_MC_LAYER_SLOT;
 471         layers[1].size = NUM_DIMMS;
 472         layers[1].is_virt_csrow = true;
 473         mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
 474                             sizeof(struct skx_pvt));
 475
 476         if (unlikely(!mci))
 477                 return -ENOMEM;
 478
 479         edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
 480
 481         /* Associate skx_dev and mci for future usage */
 482         imc->mci = mci;
 483         pvt = mci->pvt_info;
 484         pvt->imc = imc;
 485
 486         mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name,
 487                                   imc->node_id, imc->lmc);
 488         if (!mci->ctl_name) {
 489                 rc = -ENOMEM;
 490                 goto fail0;
 491         }
 492
 493         mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM;
 494         if (cfg->support_ddr5)
 495                 mci->mtype_cap |= MEM_FLAG_DDR5;
 496         mci->edac_ctl_cap = EDAC_FLAG_NONE;
 497         mci->edac_cap = EDAC_FLAG_NONE;
 498         mci->mod_name = mod_str;
 499         mci->dev_name = pci_name(pdev);
 500         mci->ctl_page_to_phys = NULL;
 501
 502         rc = get_dimm_config(mci, cfg);
 503         if (rc < 0)
 504                 goto fail;
 505
 506         /* Record ptr to the generic device */
 507         mci->pdev = &pdev->dev;
 508
 509         /* Add this new MC control structure to EDAC's list of MCs */
 510         if (unlikely(edac_mc_add_mc(mci))) {
 511                 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
 512                 rc = -EINVAL;
 513                 goto fail;
 514         }
 515
 516         return 0;
 517
 518 fail:
 519         kfree(mci->ctl_name);
 520 fail0:
 521         edac_mc_free(mci);
 522         imc->mci = NULL;
 523         return rc;
 524 }
 525 EXPORT_SYMBOL_GPL(skx_register_mci);
 526
 527 static void skx_unregister_mci(struct skx_imc *imc)
 528 {
 529         struct mem_ctl_info *mci = imc->mci;
 530
 531         if (!mci)
 532                 return;
 533
 534         edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
 535
 536         /* Remove MC sysfs nodes */
 537         edac_mc_del_mc(mci->pdev);
 538
 539         edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
 540         kfree(mci->ctl_name);
 541         edac_mc_free(mci);
 542 }
 543
 544 static void skx_mce_output_error(struct mem_ctl_info *mci,
 545                                  const struct mce *m,
 546                                  struct decoded_addr *res)
 547 {
 548         enum hw_event_mc_err_type tp_event;
 549         char *optype;
 550         bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
 551         bool overflow = GET_BITFIELD(m->status, 62, 62);
 552         bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
 553         bool scrub_err = false;
 554         bool recoverable;
 555         int len;
 556         u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
 557         u32 mscod = GET_BITFIELD(m->status, 16, 31);
 558         u32 errcode = GET_BITFIELD(m->status, 0, 15);
 559         u32 optypenum = GET_BITFIELD(m->status, 4, 6);
 560
 561         recoverable = GET_BITFIELD(m->status, 56, 56);
 562
 563         if (uncorrected_error) {
 564                 core_err_cnt = 1;
 565                 if (ripv) {
 566                         tp_event = HW_EVENT_ERR_UNCORRECTED;
 567                 } else {
 568                         tp_event = HW_EVENT_ERR_FATAL;
 569                 }
 570         } else {
 571                 tp_event = HW_EVENT_ERR_CORRECTED;
 572         }
 573
 574         switch (optypenum) {
 575         case 0:
 576                 optype = "generic undef request error";
 577                 break;
 578         case 1:
 579                 optype = "memory read error";
 580                 break;
 581         case 2:
 582                 optype = "memory write error";
 583                 break;
 584         case 3:
 585                 optype = "addr/cmd error";
 586                 break;
 587         case 4:
 588                 optype = "memory scrubbing error";
 589                 scrub_err = true;
 590                 break;
 591         default:
 592                 optype = "reserved";
 593                 break;
 594         }
 595
 596         if (res->decoded_by_adxl) {
 597                 len = snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s",
 598                          overflow ? " OVERFLOW" : "",
 599                          (uncorrected_error && recoverable) ? " recoverable" : "",
 600                          mscod, errcode, adxl_msg);
 601         } else {
 602                 len = snprintf(skx_msg, MSG_SIZE,
 603                          "%s%s err_code:0x%04x:0x%04x ProcessorSocketId:0x%x MemoryControllerId:0x%x PhysicalRankId:0x%x Row:0x%x Column:0x%x Bank:0x%x BankGroup:0x%x",
 604                          overflow ? " OVERFLOW" : "",
 605                          (uncorrected_error && recoverable) ? " recoverable" : "",
 606                          mscod, errcode,
 607                          res->socket, res->imc, res->rank,
 608                          res->row, res->column, res->bank_address, res->bank_group);
 609         }
 610
 611         if (skx_show_retry_rd_err_log)
 612                 skx_show_retry_rd_err_log(res, skx_msg + len, MSG_SIZE - len, scrub_err);
 613
 614         edac_dbg(0, "%s\n", skx_msg);
 615
 616         /* Call the helper to output message */
 617         edac_mc_handle_error(tp_event, mci, core_err_cnt,
 618                              m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
 619                              res->channel, res->dimm, -1,
 620                              optype, skx_msg);
 621 }
 622
 623 static bool skx_error_in_1st_level_mem(const struct mce *m)
 624 {
 625         u32 errcode;
 626
 627         if (!skx_mem_cfg_2lm)
 628                 return false;
 629
 630         errcode = GET_BITFIELD(m->status, 0, 15) & MCACOD_MEM_ERR_MASK;
 631
 632         return errcode == MCACOD_EXT_MEM_ERR;
 633 }
 634
 635 static bool skx_error_in_mem(const struct mce *m)
 636 {
 637         u32 errcode;
 638
 639         errcode = GET_BITFIELD(m->status, 0, 15) & MCACOD_MEM_ERR_MASK;
 640
 641         return (errcode == MCACOD_MEM_CTL_ERR || errcode == MCACOD_EXT_MEM_ERR);
 642 }
 643
 644 int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
 645                         void *data)
 646 {
 647         struct mce *mce = (struct mce *)data;
 648         struct decoded_addr res;
 649         struct mem_ctl_info *mci;
 650         char *type;
 651
 652         if (mce->kflags & MCE_HANDLED_CEC)
 653                 return NOTIFY_DONE;
 654
 655         /* Ignore unless this is memory related with an address */
 656         if (!skx_error_in_mem(mce) || !(mce->status & MCI_STATUS_ADDRV))
 657                 return NOTIFY_DONE;
 658
 659         memset(&res, 0, sizeof(res));
 660         res.mce  = mce;
 661         res.addr = mce->addr & MCI_ADDR_PHYSADDR;
 662         if (!pfn_to_online_page(res.addr >> PAGE_SHIFT) && !arch_is_platform_page(res.addr)) {
 663                 pr_err("Invalid address 0x%llx in IA32_MC%d_ADDR\n", mce->addr, mce->bank);
 664                 return NOTIFY_DONE;
 665         }
 666
 667         /* Try driver decoder first */
 668         if (!(driver_decode && driver_decode(&res))) {
 669                 /* Then try firmware decoder (ACPI DSM methods) */
 670                 if (!(adxl_component_count && skx_adxl_decode(&res, skx_error_in_1st_level_mem(mce))))
 671                         return NOTIFY_DONE;
 672         }
 673
 674         mci = res.dev->imc[res.imc].mci;
 675
 676         if (!mci)
 677                 return NOTIFY_DONE;
 678
 679         if (mce->mcgstatus & MCG_STATUS_MCIP)
 680                 type = "Exception";
 681         else
 682                 type = "Event";
 683
 684         skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
 685
 686         skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx "
 687                            "Bank %d: 0x%llx\n", mce->extcpu, type,
 688                            mce->mcgstatus, mce->bank, mce->status);
 689         skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc);
 690         skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr);
 691         skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc);
 692
 693         skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET "
 694                            "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid,
 695                            mce->time, mce->socketid, mce->apicid);
 696
 697         skx_mce_output_error(mci, mce, &res);
 698
 699         mce->kflags |= MCE_HANDLED_EDAC;
 700         return NOTIFY_DONE;
 701 }
 702 EXPORT_SYMBOL_GPL(skx_mce_check_error);
 703
 704 void skx_remove(void)
 705 {
 706         int i, j;
 707         struct skx_dev *d, *tmp;
 708
 709         edac_dbg(0, "\n");
 710
 711         list_for_each_entry_safe(d, tmp, &dev_edac_list, list) {
 712                 list_del(&d->list);
 713                 for (i = 0; i < NUM_IMC; i++) {
 714                         if (d->imc[i].mci)
 715                                 skx_unregister_mci(&d->imc[i]);
 716
 717                         if (d->imc[i].mdev)
 718                                 pci_dev_put(d->imc[i].mdev);
 719
 720                         if (d->imc[i].mbase)
 721                                 iounmap(d->imc[i].mbase);
 722
 723                         for (j = 0; j < NUM_CHANNELS; j++) {
 724                                 if (d->imc[i].chan[j].cdev)
 725                                         pci_dev_put(d->imc[i].chan[j].cdev);
 726                         }
 727                 }
 728                 if (d->util_all)
 729                         pci_dev_put(d->util_all);
 730                 if (d->pcu_cr3)
 731                         pci_dev_put(d->pcu_cr3);
 732                 if (d->sad_all)
 733                         pci_dev_put(d->sad_all);
 734                 if (d->uracu)
 735                         pci_dev_put(d->uracu);
 736
 737                 kfree(d);
 738         }
 739 }
 740 EXPORT_SYMBOL_GPL(skx_remove);
 741
 742 #ifdef CONFIG_EDAC_DEBUG
 743 /*
 744  * Debug feature.
 745  * Exercise the address decode logic by writing an address to
 746  * /sys/kernel/debug/edac/{skx,i10nm}_test/addr.
 747  */
 748 static struct dentry *skx_test;
 749
 750 static int debugfs_u64_set(void *data, u64 val)
 751 {
 752         struct mce m;
 753
 754         pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
 755
 756         memset(&m, 0, sizeof(m));
 757         /* ADDRV + MemRd + Unknown channel */
 758         m.status = MCI_STATUS_ADDRV + 0x90;
 759         /* One corrected error */
 760         m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
 761         m.addr = val;
 762         skx_mce_check_error(NULL, 0, &m);
 763
 764         return 0;
 765 }
 766 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
 767
 768 void skx_setup_debug(const char *name)
 769 {
 770         skx_test = edac_debugfs_create_dir(name);
 771         if (!skx_test)
 772                 return;
 773
 774         if (!edac_debugfs_create_file("addr", 0200, skx_test,
 775                                       NULL, &fops_u64_wo)) {
 776                 debugfs_remove(skx_test);
 777                 skx_test = NULL;
 778         }
 779 }
 780 EXPORT_SYMBOL_GPL(skx_setup_debug);
 781
 782 void skx_teardown_debug(void)
 783 {
 784         debugfs_remove_recursive(skx_test);
 785 }
 786 EXPORT_SYMBOL_GPL(skx_teardown_debug);
 787 #endif /*CONFIG_EDAC_DEBUG*/
 788
 789 MODULE_LICENSE("GPL v2");
 790 MODULE_AUTHOR("Tony Luck");
 791 MODULE_DESCRIPTION("MC Driver for Intel server processors");