1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008 Nuovation System Designs, LLC
4 * Grant Erickson <gerickson@nuovations.com>
7 #include <linux/edac.h>
8 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <linux/types.h>
20 #include "edac_module.h"
21 #include "ppc4xx_edac.h"
24 * This file implements a driver for monitoring and handling events
25 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
26 * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX.
28 * As realized in the 405EX[r], this controller features:
30 * - Support for registered- and non-registered DDR1 and DDR2 memory.
31 * - 32-bit or 16-bit memory interface with optional ECC.
33 * o ECC support includes:
36 * - Aligned-nibble error detect
39 * - Two (2) memory banks/ranks.
40 * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
41 * bank/rank in 16-bit mode.
43 * As realized in the 440SP and 440SPe, this controller changes/adds:
45 * - 64-bit or 32-bit memory interface with optional ECC.
47 * o ECC support includes:
50 * - Aligned-nibble error detect
53 * - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB
54 * per bank/rank in 32-bit mode.
56 * As realized in the 460EX and 460GT, this controller changes/adds:
58 * - 64-bit or 32-bit memory interface with optional ECC.
60 * o ECC support includes:
63 * - Aligned-nibble error detect
66 * - Four (4) memory banks/ranks.
67 * - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB
68 * per bank/rank in 32-bit mode.
70 * At present, this driver has ONLY been tested against the controller
71 * realization in the 405EX[r] on the AMCC Kilauea and Haleakala
72 * boards (256 MiB w/o ECC memory soldered onto the board) and a
73 * proprietary board based on those designs (128 MiB ECC memory, also
74 * soldered onto the board).
76 * Dynamic feature detection and handling needs to be added for the
77 * other realizations of this controller listed above.
79 * Eventually, this driver will likely be adapted to the above variant
80 * realizations of this controller as well as broken apart to handle
81 * the other known ECC-capable controllers prevalent in other 4xx
84 * - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
85 * - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr"
86 * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
88 * For this controller, unfortunately, correctable errors report
89 * nothing more than the beat/cycle and byte/lane the correction
90 * occurred on and the check bit group that covered the error.
92 * In contrast, uncorrectable errors also report the failing address,
93 * the bus master and the transaction direction (i.e. read or write)
95 * Regardless of whether the error is a CE or a UE, we report the
96 * following pieces of information in the driver-unique message to the
101 * - Check bit error group
105 /* Preprocessor Definitions */
107 #define EDAC_OPSTATE_INT_STR "interrupt"
108 #define EDAC_OPSTATE_POLL_STR "polled"
109 #define EDAC_OPSTATE_UNKNOWN_STR "unknown"
111 #define PPC4XX_EDAC_MODULE_NAME "ppc4xx_edac"
112 #define PPC4XX_EDAC_MODULE_REVISION "v1.0.0"
114 #define PPC4XX_EDAC_MESSAGE_SIZE 256
117 * Kernel logging without an EDAC instance
119 #define ppc4xx_edac_printk(level, fmt, arg...) \
120 edac_printk(level, "PPC4xx MC", fmt, ##arg)
123 * Kernel logging with an EDAC instance
125 #define ppc4xx_edac_mc_printk(level, mci, fmt, arg...) \
126 edac_mc_chipset_printk(mci, level, "PPC4xx", fmt, ##arg)
129 * Macros to convert bank configuration size enumerations into MiB and
132 #define SDRAM_MBCF_SZ_MiB_MIN 4
133 #define SDRAM_MBCF_SZ_TO_MiB(n) (SDRAM_MBCF_SZ_MiB_MIN \
134 << (SDRAM_MBCF_SZ_DECODE(n)))
135 #define SDRAM_MBCF_SZ_TO_PAGES(n) (SDRAM_MBCF_SZ_MiB_MIN \
136 << (20 - PAGE_SHIFT + \
137 SDRAM_MBCF_SZ_DECODE(n)))
140 * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
141 * indirectly accessed and have a base and length defined by the
142 * device tree. The base can be anything; however, we expect the
143 * length to be precisely two registers, the first for the address
144 * window and the second for the data window.
146 #define SDRAM_DCR_RESOURCE_LEN 2
147 #define SDRAM_DCR_ADDR_OFFSET 0
148 #define SDRAM_DCR_DATA_OFFSET 1
151 * Device tree interrupt indices
153 #define INTMAP_ECCDED_INDEX 0 /* Double-bit Error Detect */
154 #define INTMAP_ECCSEC_INDEX 1 /* Single-bit Error Correct */
156 /* Type Definitions */
159 * PPC4xx SDRAM memory controller private instance data
161 struct ppc4xx_edac_pdata
{
162 dcr_host_t dcr_host
; /* Indirect DCR address/data window mapping */
164 int sec
; /* Single-bit correctable error IRQ assigned */
165 int ded
; /* Double-bit detectable error IRQ assigned */
170 * Various status data gathered and manipulated when checking and
171 * reporting ECC status.
173 struct ppc4xx_ecc_status
{
181 /* Global Variables */
184 * Device tree node type and compatible tuples this driver can match
187 static const struct of_device_id ppc4xx_edac_match
[] = {
189 .compatible
= "ibm,sdram-4xx-ddr2"
193 MODULE_DEVICE_TABLE(of
, ppc4xx_edac_match
);
196 * TODO: The row and channel parameters likely need to be dynamically
197 * set based on the aforementioned variant controller realizations.
199 static const unsigned ppc4xx_edac_nr_csrows
= 2;
200 static const unsigned ppc4xx_edac_nr_chans
= 1;
203 * Strings associated with PLB master IDs capable of being posted in
204 * SDRAM_BESR or SDRAM_WMIRQ on uncorrectable ECC errors.
206 static const char * const ppc4xx_plb_masters
[9] = {
207 [SDRAM_PLB_M0ID_ICU
] = "ICU",
208 [SDRAM_PLB_M0ID_PCIE0
] = "PCI-E 0",
209 [SDRAM_PLB_M0ID_PCIE1
] = "PCI-E 1",
210 [SDRAM_PLB_M0ID_DMA
] = "DMA",
211 [SDRAM_PLB_M0ID_DCU
] = "DCU",
212 [SDRAM_PLB_M0ID_OPB
] = "OPB",
213 [SDRAM_PLB_M0ID_MAL
] = "MAL",
214 [SDRAM_PLB_M0ID_SEC
] = "SEC",
215 [SDRAM_PLB_M0ID_AHB
] = "AHB"
219 * mfsdram - read and return controller register data
220 * @dcr_host: A pointer to the DCR mapping.
221 * @idcr_n: The indirect DCR register to read.
223 * This routine reads and returns the data associated with the
224 * controller's specified indirect DCR register.
226 * Returns the read data.
229 mfsdram(const dcr_host_t
*dcr_host
, unsigned int idcr_n
)
231 return __mfdcri(dcr_host
->base
+ SDRAM_DCR_ADDR_OFFSET
,
232 dcr_host
->base
+ SDRAM_DCR_DATA_OFFSET
,
237 * mtsdram - write controller register data
238 * @dcr_host: A pointer to the DCR mapping.
239 * @idcr_n: The indirect DCR register to write.
240 * @value: The data to write.
242 * This routine writes the provided data to the controller's specified
243 * indirect DCR register.
246 mtsdram(const dcr_host_t
*dcr_host
, unsigned int idcr_n
, u32 value
)
248 return __mtdcri(dcr_host
->base
+ SDRAM_DCR_ADDR_OFFSET
,
249 dcr_host
->base
+ SDRAM_DCR_DATA_OFFSET
,
255 * ppc4xx_edac_check_bank_error - check a bank for an ECC bank error
256 * @status: A pointer to the ECC status structure to check for an
258 * @bank: The bank to check for an ECC error.
260 * This routine determines whether the specified bank has an ECC
263 * Returns true if the specified bank has an ECC error; otherwise,
267 ppc4xx_edac_check_bank_error(const struct ppc4xx_ecc_status
*status
,
272 return status
->ecces
& SDRAM_ECCES_BK0ER
;
274 return status
->ecces
& SDRAM_ECCES_BK1ER
;
281 * ppc4xx_edac_generate_bank_message - generate interpretted bank status message
282 * @mci: A pointer to the EDAC memory controller instance associated
283 * with the bank message being generated.
284 * @status: A pointer to the ECC status structure to generate the
286 * @buffer: A pointer to the buffer in which to generate the
288 * @size: The size, in bytes, of space available in buffer.
290 * This routine generates to the provided buffer the portion of the
291 * driver-unique report message associated with the ECCESS[BKNER]
292 * field of the specified ECC status.
294 * Returns the number of characters generated on success; otherwise, <
298 ppc4xx_edac_generate_bank_message(const struct mem_ctl_info
*mci
,
299 const struct ppc4xx_ecc_status
*status
,
304 unsigned int row
, rows
;
306 n
= snprintf(buffer
, size
, "%s: Banks: ", mci
->dev_name
);
308 if (n
< 0 || n
>= size
)
315 for (rows
= 0, row
= 0; row
< mci
->nr_csrows
; row
++) {
316 if (ppc4xx_edac_check_bank_error(status
, row
)) {
317 n
= snprintf(buffer
, size
, "%s%u",
318 (rows
++ ? ", " : ""), row
);
320 if (n
< 0 || n
>= size
)
329 n
= snprintf(buffer
, size
, "%s; ", rows
? "" : "None");
331 if (n
< 0 || n
>= size
)
343 * ppc4xx_edac_generate_checkbit_message - generate interpretted checkbit message
344 * @mci: A pointer to the EDAC memory controller instance associated
345 * with the checkbit message being generated.
346 * @status: A pointer to the ECC status structure to generate the
348 * @buffer: A pointer to the buffer in which to generate the
350 * @size: The size, in bytes, of space available in buffer.
352 * This routine generates to the provided buffer the portion of the
353 * driver-unique report message associated with the ECCESS[CKBER]
354 * field of the specified ECC status.
356 * Returns the number of characters generated on success; otherwise, <
360 ppc4xx_edac_generate_checkbit_message(const struct mem_ctl_info
*mci
,
361 const struct ppc4xx_ecc_status
*status
,
365 const struct ppc4xx_edac_pdata
*pdata
= mci
->pvt_info
;
366 const char *ckber
= NULL
;
368 switch (status
->ecces
& SDRAM_ECCES_CKBER_MASK
) {
369 case SDRAM_ECCES_CKBER_NONE
:
372 case SDRAM_ECCES_CKBER_32_ECC_0_3
:
375 case SDRAM_ECCES_CKBER_32_ECC_4_8
:
376 switch (mfsdram(&pdata
->dcr_host
, SDRAM_MCOPT1
) &
377 SDRAM_MCOPT1_WDTH_MASK
) {
378 case SDRAM_MCOPT1_WDTH_16
:
381 case SDRAM_MCOPT1_WDTH_32
:
389 case SDRAM_ECCES_CKBER_32_ECC_0_8
:
397 return snprintf(buffer
, size
, "Checkbit Error: %s", ckber
);
401 * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message
402 * @mci: A pointer to the EDAC memory controller instance associated
403 * with the byte lane message being generated.
404 * @status: A pointer to the ECC status structure to generate the
406 * @buffer: A pointer to the buffer in which to generate the
408 * @size: The size, in bytes, of space available in buffer.
410 * This routine generates to the provided buffer the portion of the
411 * driver-unique report message associated with the ECCESS[BNCE]
412 * field of the specified ECC status.
414 * Returns the number of characters generated on success; otherwise, <
418 ppc4xx_edac_generate_lane_message(const struct mem_ctl_info
*mci
,
419 const struct ppc4xx_ecc_status
*status
,
424 unsigned int lane
, lanes
;
425 const unsigned int first_lane
= 0;
426 const unsigned int lane_count
= 16;
428 n
= snprintf(buffer
, size
, "; Byte Lane Errors: ");
430 if (n
< 0 || n
>= size
)
437 for (lanes
= 0, lane
= first_lane
; lane
< lane_count
; lane
++) {
438 if ((status
->ecces
& SDRAM_ECCES_BNCE_ENCODE(lane
)) != 0) {
439 n
= snprintf(buffer
, size
,
441 (lanes
++ ? ", " : ""), lane
);
443 if (n
< 0 || n
>= size
)
452 n
= snprintf(buffer
, size
, "%s; ", lanes
? "" : "None");
454 if (n
< 0 || n
>= size
)
466 * ppc4xx_edac_generate_ecc_message - generate interpretted ECC status message
467 * @mci: A pointer to the EDAC memory controller instance associated
468 * with the ECCES message being generated.
469 * @status: A pointer to the ECC status structure to generate the
471 * @buffer: A pointer to the buffer in which to generate the
473 * @size: The size, in bytes, of space available in buffer.
475 * This routine generates to the provided buffer the portion of the
476 * driver-unique report message associated with the ECCESS register of
477 * the specified ECC status.
479 * Returns the number of characters generated on success; otherwise, <
483 ppc4xx_edac_generate_ecc_message(const struct mem_ctl_info
*mci
,
484 const struct ppc4xx_ecc_status
*status
,
490 n
= ppc4xx_edac_generate_bank_message(mci
, status
, buffer
, size
);
492 if (n
< 0 || n
>= size
)
499 n
= ppc4xx_edac_generate_checkbit_message(mci
, status
, buffer
, size
);
501 if (n
< 0 || n
>= size
)
508 n
= ppc4xx_edac_generate_lane_message(mci
, status
, buffer
, size
);
510 if (n
< 0 || n
>= size
)
522 * ppc4xx_edac_generate_plb_message - generate interpretted PLB status message
523 * @mci: A pointer to the EDAC memory controller instance associated
524 * with the PLB message being generated.
525 * @status: A pointer to the ECC status structure to generate the
527 * @buffer: A pointer to the buffer in which to generate the
529 * @size: The size, in bytes, of space available in buffer.
531 * This routine generates to the provided buffer the portion of the
532 * driver-unique report message associated with the PLB-related BESR
533 * and/or WMIRQ registers of the specified ECC status.
535 * Returns the number of characters generated on success; otherwise, <
539 ppc4xx_edac_generate_plb_message(const struct mem_ctl_info
*mci
,
540 const struct ppc4xx_ecc_status
*status
,
547 if ((status
->besr
& SDRAM_BESR_MASK
) == 0)
550 if ((status
->besr
& SDRAM_BESR_M0ET_MASK
) == SDRAM_BESR_M0ET_NONE
)
553 read
= ((status
->besr
& SDRAM_BESR_M0RW_MASK
) == SDRAM_BESR_M0RW_READ
);
555 master
= SDRAM_BESR_M0ID_DECODE(status
->besr
);
557 return snprintf(buffer
, size
,
558 "%s error w/ PLB master %u \"%s\"; ",
559 (read
? "Read" : "Write"),
561 (((master
>= SDRAM_PLB_M0ID_FIRST
) &&
562 (master
<= SDRAM_PLB_M0ID_LAST
)) ?
563 ppc4xx_plb_masters
[master
] : "UNKNOWN"));
567 * ppc4xx_edac_generate_message - generate interpretted status message
568 * @mci: A pointer to the EDAC memory controller instance associated
569 * with the driver-unique message being generated.
570 * @status: A pointer to the ECC status structure to generate the
572 * @buffer: A pointer to the buffer in which to generate the
574 * @size: The size, in bytes, of space available in buffer.
576 * This routine generates to the provided buffer the driver-unique
577 * EDAC report message from the specified ECC status.
580 ppc4xx_edac_generate_message(const struct mem_ctl_info
*mci
,
581 const struct ppc4xx_ecc_status
*status
,
587 if (buffer
== NULL
|| size
== 0)
590 n
= ppc4xx_edac_generate_ecc_message(mci
, status
, buffer
, size
);
592 if (n
< 0 || n
>= size
)
598 ppc4xx_edac_generate_plb_message(mci
, status
, buffer
, size
);
603 * ppc4xx_ecc_dump_status - dump controller ECC status registers
604 * @mci: A pointer to the EDAC memory controller instance
605 * associated with the status being dumped.
606 * @status: A pointer to the ECC status structure to generate the
609 * This routine dumps to the kernel log buffer the raw and
610 * interpretted specified ECC status.
613 ppc4xx_ecc_dump_status(const struct mem_ctl_info
*mci
,
614 const struct ppc4xx_ecc_status
*status
)
616 char message
[PPC4XX_EDAC_MESSAGE_SIZE
];
618 ppc4xx_edac_generate_message(mci
, status
, message
, sizeof(message
));
620 ppc4xx_edac_mc_printk(KERN_INFO
, mci
,
625 "\tBEAR: 0x%08x%08x\n"
637 * ppc4xx_ecc_get_status - get controller ECC status
638 * @mci: A pointer to the EDAC memory controller instance
639 * associated with the status being retrieved.
640 * @status: A pointer to the ECC status structure to populate the
643 * This routine reads and masks, as appropriate, all the relevant
644 * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
645 * While we read all of them, for correctable errors, we only expect
646 * to deal with ECCES. For uncorrectable errors, we expect to deal
650 ppc4xx_ecc_get_status(const struct mem_ctl_info
*mci
,
651 struct ppc4xx_ecc_status
*status
)
653 const struct ppc4xx_edac_pdata
*pdata
= mci
->pvt_info
;
654 const dcr_host_t
*dcr_host
= &pdata
->dcr_host
;
656 status
->ecces
= mfsdram(dcr_host
, SDRAM_ECCES
) & SDRAM_ECCES_MASK
;
657 status
->wmirq
= mfsdram(dcr_host
, SDRAM_WMIRQ
) & SDRAM_WMIRQ_MASK
;
658 status
->besr
= mfsdram(dcr_host
, SDRAM_BESR
) & SDRAM_BESR_MASK
;
659 status
->bearl
= mfsdram(dcr_host
, SDRAM_BEARL
);
660 status
->bearh
= mfsdram(dcr_host
, SDRAM_BEARH
);
664 * ppc4xx_ecc_clear_status - clear controller ECC status
665 * @mci: A pointer to the EDAC memory controller instance
666 * associated with the status being cleared.
667 * @status: A pointer to the ECC status structure containing the
668 * values to write to clear the ECC status.
670 * This routine clears--by writing the masked (as appropriate) status
671 * values back to--the status registers that deal with
672 * ibm,sdram-4xx-ddr2 ECC errors.
675 ppc4xx_ecc_clear_status(const struct mem_ctl_info
*mci
,
676 const struct ppc4xx_ecc_status
*status
)
678 const struct ppc4xx_edac_pdata
*pdata
= mci
->pvt_info
;
679 const dcr_host_t
*dcr_host
= &pdata
->dcr_host
;
681 mtsdram(dcr_host
, SDRAM_ECCES
, status
->ecces
& SDRAM_ECCES_MASK
);
682 mtsdram(dcr_host
, SDRAM_WMIRQ
, status
->wmirq
& SDRAM_WMIRQ_MASK
);
683 mtsdram(dcr_host
, SDRAM_BESR
, status
->besr
& SDRAM_BESR_MASK
);
684 mtsdram(dcr_host
, SDRAM_BEARL
, 0);
685 mtsdram(dcr_host
, SDRAM_BEARH
, 0);
689 * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE)
690 * @mci: A pointer to the EDAC memory controller instance
691 * associated with the correctable error being handled and reported.
692 * @status: A pointer to the ECC status structure associated with
693 * the correctable error being handled and reported.
695 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
696 * correctable error. Per the aforementioned discussion, there's not
697 * enough status available to use the full EDAC correctable error
698 * interface, so we just pass driver-unique message to the "no info"
702 ppc4xx_edac_handle_ce(struct mem_ctl_info
*mci
,
703 const struct ppc4xx_ecc_status
*status
)
706 char message
[PPC4XX_EDAC_MESSAGE_SIZE
];
708 ppc4xx_edac_generate_message(mci
, status
, message
, sizeof(message
));
710 for (row
= 0; row
< mci
->nr_csrows
; row
++)
711 if (ppc4xx_edac_check_bank_error(status
, row
))
712 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED
, mci
, 1,
719 * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE)
720 * @mci: A pointer to the EDAC memory controller instance
721 * associated with the uncorrectable error being handled and
723 * @status: A pointer to the ECC status structure associated with
724 * the uncorrectable error being handled and reported.
726 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
727 * uncorrectable error.
730 ppc4xx_edac_handle_ue(struct mem_ctl_info
*mci
,
731 const struct ppc4xx_ecc_status
*status
)
733 const u64 bear
= ((u64
)status
->bearh
<< 32 | status
->bearl
);
734 const unsigned long page
= bear
>> PAGE_SHIFT
;
735 const unsigned long offset
= bear
& ~PAGE_MASK
;
737 char message
[PPC4XX_EDAC_MESSAGE_SIZE
];
739 ppc4xx_edac_generate_message(mci
, status
, message
, sizeof(message
));
741 for (row
= 0; row
< mci
->nr_csrows
; row
++)
742 if (ppc4xx_edac_check_bank_error(status
, row
))
743 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED
, mci
, 1,
750 * ppc4xx_edac_check - check controller for ECC errors
751 * @mci: A pointer to the EDAC memory controller instance
752 * associated with the ibm,sdram-4xx-ddr2 controller being
755 * This routine is used to check and post ECC errors and is called by
756 * both the EDAC polling thread and this driver's CE and UE interrupt
760 ppc4xx_edac_check(struct mem_ctl_info
*mci
)
763 static unsigned int count
;
765 struct ppc4xx_ecc_status status
;
767 ppc4xx_ecc_get_status(mci
, &status
);
770 if (count
++ % 30 == 0)
771 ppc4xx_ecc_dump_status(mci
, &status
);
774 if (status
.ecces
& SDRAM_ECCES_UE
)
775 ppc4xx_edac_handle_ue(mci
, &status
);
777 if (status
.ecces
& SDRAM_ECCES_CE
)
778 ppc4xx_edac_handle_ce(mci
, &status
);
780 ppc4xx_ecc_clear_status(mci
, &status
);
784 * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine
785 * @irq: The virtual interrupt number being serviced.
786 * @dev_id: A pointer to the EDAC memory controller instance
787 * associated with the interrupt being handled.
789 * This routine implements the interrupt handler for both correctable
790 * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2
791 * controller. It simply calls through to the same routine used during
792 * polling to check, report and clear the ECC status.
794 * Unconditionally returns IRQ_HANDLED.
797 ppc4xx_edac_isr(int irq
, void *dev_id
)
799 struct mem_ctl_info
*mci
= dev_id
;
801 ppc4xx_edac_check(mci
);
807 * ppc4xx_edac_get_dtype - return the controller memory width
808 * @mcopt1: The 32-bit Memory Controller Option 1 register value
809 * currently set for the controller, from which the width
812 * This routine returns the EDAC device type width appropriate for the
813 * current controller configuration.
815 * TODO: This needs to be conditioned dynamically through feature
816 * flags or some such when other controller variants are supported as
817 * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the
818 * 16- and 64-bit field definition/value/enumeration (b1) overloaded
821 * Returns a device type width enumeration.
823 static enum dev_type
ppc4xx_edac_get_dtype(u32 mcopt1
)
825 switch (mcopt1
& SDRAM_MCOPT1_WDTH_MASK
) {
826 case SDRAM_MCOPT1_WDTH_16
:
828 case SDRAM_MCOPT1_WDTH_32
:
836 * ppc4xx_edac_get_mtype - return controller memory type
837 * @mcopt1: The 32-bit Memory Controller Option 1 register value
838 * currently set for the controller, from which the memory type
841 * This routine returns the EDAC memory type appropriate for the
842 * current controller configuration.
844 * Returns a memory type enumeration.
846 static enum mem_type
ppc4xx_edac_get_mtype(u32 mcopt1
)
848 bool rden
= ((mcopt1
& SDRAM_MCOPT1_RDEN_MASK
) == SDRAM_MCOPT1_RDEN
);
850 switch (mcopt1
& SDRAM_MCOPT1_DDR_TYPE_MASK
) {
851 case SDRAM_MCOPT1_DDR2_TYPE
:
852 return rden
? MEM_RDDR2
: MEM_DDR2
;
853 case SDRAM_MCOPT1_DDR1_TYPE
:
854 return rden
? MEM_RDDR
: MEM_DDR
;
861 * ppc4xx_edac_init_csrows - initialize driver instance rows
862 * @mci: A pointer to the EDAC memory controller instance
863 * associated with the ibm,sdram-4xx-ddr2 controller for which
864 * the csrows (i.e. banks/ranks) are being initialized.
865 * @mcopt1: The 32-bit Memory Controller Option 1 register value
866 * currently set for the controller, from which bank width
867 * and memory typ information is derived.
869 * This routine initializes the virtual "chip select rows" associated
870 * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
871 * controller bank/rank is mapped to a row.
873 * Returns 0 if OK; otherwise, -EINVAL if the memory bank size
874 * configuration cannot be determined.
876 static int ppc4xx_edac_init_csrows(struct mem_ctl_info
*mci
, u32 mcopt1
)
878 const struct ppc4xx_edac_pdata
*pdata
= mci
->pvt_info
;
882 enum edac_type edac_mode
;
884 u32 mbxcf
, size
, nr_pages
;
886 /* Establish the memory type and width */
888 mtype
= ppc4xx_edac_get_mtype(mcopt1
);
889 dtype
= ppc4xx_edac_get_dtype(mcopt1
);
891 /* Establish EDAC mode */
893 if (mci
->edac_cap
& EDAC_FLAG_SECDED
)
894 edac_mode
= EDAC_SECDED
;
895 else if (mci
->edac_cap
& EDAC_FLAG_EC
)
898 edac_mode
= EDAC_NONE
;
901 * Initialize each chip select row structure which correspond
902 * 1:1 with a controller bank/rank.
905 for (row
= 0; row
< mci
->nr_csrows
; row
++) {
906 struct csrow_info
*csi
= mci
->csrows
[row
];
909 * Get the configuration settings for this
910 * row/bank/rank and skip disabled banks.
913 mbxcf
= mfsdram(&pdata
->dcr_host
, SDRAM_MBXCF(row
));
915 if ((mbxcf
& SDRAM_MBCF_BE_MASK
) != SDRAM_MBCF_BE_ENABLE
)
918 /* Map the bank configuration size setting to pages. */
920 size
= mbxcf
& SDRAM_MBCF_SZ_MASK
;
923 case SDRAM_MBCF_SZ_4MB
:
924 case SDRAM_MBCF_SZ_8MB
:
925 case SDRAM_MBCF_SZ_16MB
:
926 case SDRAM_MBCF_SZ_32MB
:
927 case SDRAM_MBCF_SZ_64MB
:
928 case SDRAM_MBCF_SZ_128MB
:
929 case SDRAM_MBCF_SZ_256MB
:
930 case SDRAM_MBCF_SZ_512MB
:
931 case SDRAM_MBCF_SZ_1GB
:
932 case SDRAM_MBCF_SZ_2GB
:
933 case SDRAM_MBCF_SZ_4GB
:
934 case SDRAM_MBCF_SZ_8GB
:
935 nr_pages
= SDRAM_MBCF_SZ_TO_PAGES(size
);
938 ppc4xx_edac_mc_printk(KERN_ERR
, mci
,
939 "Unrecognized memory bank %d "
941 row
, SDRAM_MBCF_SZ_DECODE(size
));
947 * It's unclear exactly what grain should be set to
948 * here. The SDRAM_ECCES register allows resolution of
949 * an error down to a nibble which would potentially
950 * argue for a grain of '1' byte, even though we only
951 * know the associated address for uncorrectable
952 * errors. This value is not used at present for
953 * anything other than error reporting so getting it
954 * wrong should be of little consequence. Other
955 * possible values would be the PLB width (16), the
956 * page size (PAGE_SIZE) or the memory width (2 or 4).
958 for (j
= 0; j
< csi
->nr_channels
; j
++) {
959 struct dimm_info
*dimm
= csi
->channels
[j
]->dimm
;
961 dimm
->nr_pages
= nr_pages
/ csi
->nr_channels
;
967 dimm
->edac_mode
= edac_mode
;
976 * ppc4xx_edac_mc_init - initialize driver instance
977 * @mci: A pointer to the EDAC memory controller instance being
979 * @op: A pointer to the OpenFirmware device tree node associated
980 * with the controller this EDAC instance is bound to.
981 * @dcr_host: A pointer to the DCR data containing the DCR mapping
982 * for this controller instance.
983 * @mcopt1: The 32-bit Memory Controller Option 1 register value
984 * currently set for the controller, from which ECC capabilities
985 * and scrub mode are derived.
987 * This routine performs initialization of the EDAC memory controller
988 * instance and related driver-private data associated with the
989 * ibm,sdram-4xx-ddr2 memory controller the instance is bound to.
991 * Returns 0 if OK; otherwise, < 0 on error.
993 static int ppc4xx_edac_mc_init(struct mem_ctl_info
*mci
,
994 struct platform_device
*op
,
995 const dcr_host_t
*dcr_host
, u32 mcopt1
)
998 const u32 memcheck
= (mcopt1
& SDRAM_MCOPT1_MCHK_MASK
);
999 struct ppc4xx_edac_pdata
*pdata
= NULL
;
1000 const struct device_node
*np
= op
->dev
.of_node
;
1002 if (of_match_device(ppc4xx_edac_match
, &op
->dev
) == NULL
)
1005 /* Initial driver pointers and private data */
1007 mci
->pdev
= &op
->dev
;
1009 dev_set_drvdata(mci
->pdev
, mci
);
1011 pdata
= mci
->pvt_info
;
1013 pdata
->dcr_host
= *dcr_host
;
1015 /* Initialize controller capabilities and configuration */
1017 mci
->mtype_cap
= (MEM_FLAG_DDR
| MEM_FLAG_RDDR
|
1018 MEM_FLAG_DDR2
| MEM_FLAG_RDDR2
);
1020 mci
->edac_ctl_cap
= (EDAC_FLAG_NONE
|
1024 mci
->scrub_cap
= SCRUB_NONE
;
1025 mci
->scrub_mode
= SCRUB_NONE
;
1028 * Update the actual capabilites based on the MCOPT1[MCHK]
1029 * settings. Scrubbing is only useful if reporting is enabled.
1033 case SDRAM_MCOPT1_MCHK_CHK
:
1034 mci
->edac_cap
= EDAC_FLAG_EC
;
1036 case SDRAM_MCOPT1_MCHK_CHK_REP
:
1037 mci
->edac_cap
= (EDAC_FLAG_EC
| EDAC_FLAG_SECDED
);
1038 mci
->scrub_mode
= SCRUB_SW_SRC
;
1041 mci
->edac_cap
= EDAC_FLAG_NONE
;
1045 /* Initialize strings */
1047 mci
->mod_name
= PPC4XX_EDAC_MODULE_NAME
;
1048 mci
->ctl_name
= ppc4xx_edac_match
->compatible
;
1049 mci
->dev_name
= np
->full_name
;
1051 /* Initialize callbacks */
1053 mci
->edac_check
= ppc4xx_edac_check
;
1054 mci
->ctl_page_to_phys
= NULL
;
1056 /* Initialize chip select rows */
1058 status
= ppc4xx_edac_init_csrows(mci
, mcopt1
);
1061 ppc4xx_edac_mc_printk(KERN_ERR
, mci
,
1062 "Failed to initialize rows!\n");
1068 * ppc4xx_edac_register_irq - setup and register controller interrupts
1069 * @op: A pointer to the OpenFirmware device tree node associated
1070 * with the controller this EDAC instance is bound to.
1071 * @mci: A pointer to the EDAC memory controller instance
1072 * associated with the ibm,sdram-4xx-ddr2 controller for which
1073 * interrupts are being registered.
1075 * This routine parses the correctable (CE) and uncorrectable error (UE)
1076 * interrupts from the device tree node and maps and assigns them to
1077 * the associated EDAC memory controller instance.
1079 * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be
1080 * mapped and assigned.
1082 static int ppc4xx_edac_register_irq(struct platform_device
*op
,
1083 struct mem_ctl_info
*mci
)
1086 int ded_irq
, sec_irq
;
1087 struct ppc4xx_edac_pdata
*pdata
= mci
->pvt_info
;
1088 struct device_node
*np
= op
->dev
.of_node
;
1090 ded_irq
= irq_of_parse_and_map(np
, INTMAP_ECCDED_INDEX
);
1091 sec_irq
= irq_of_parse_and_map(np
, INTMAP_ECCSEC_INDEX
);
1093 if (!ded_irq
|| !sec_irq
) {
1094 ppc4xx_edac_mc_printk(KERN_ERR
, mci
,
1095 "Unable to map interrupts.\n");
1100 status
= request_irq(ded_irq
,
1107 ppc4xx_edac_mc_printk(KERN_ERR
, mci
,
1108 "Unable to request irq %d for ECC DED",
1114 status
= request_irq(sec_irq
,
1121 ppc4xx_edac_mc_printk(KERN_ERR
, mci
,
1122 "Unable to request irq %d for ECC SEC",
1128 ppc4xx_edac_mc_printk(KERN_INFO
, mci
, "ECCDED irq is %d\n", ded_irq
);
1129 ppc4xx_edac_mc_printk(KERN_INFO
, mci
, "ECCSEC irq is %d\n", sec_irq
);
1131 pdata
->irqs
.ded
= ded_irq
;
1132 pdata
->irqs
.sec
= sec_irq
;
1137 free_irq(sec_irq
, mci
);
1140 free_irq(ded_irq
, mci
);
1147 * ppc4xx_edac_map_dcrs - locate and map controller registers
1148 * @np: A pointer to the device tree node containing the DCR
1150 * @dcr_host: A pointer to the DCR data to populate with the
1153 * This routine attempts to locate in the device tree and map the DCR
1154 * register resources associated with the controller's indirect DCR
1155 * address and data windows.
1157 * Returns 0 if the DCRs were successfully mapped; otherwise, < 0 on
1160 static int ppc4xx_edac_map_dcrs(const struct device_node
*np
,
1161 dcr_host_t
*dcr_host
)
1163 unsigned int dcr_base
, dcr_len
;
1165 if (np
== NULL
|| dcr_host
== NULL
)
1168 /* Get the DCR resource extent and sanity check the values. */
1170 dcr_base
= dcr_resource_start(np
, 0);
1171 dcr_len
= dcr_resource_len(np
, 0);
1173 if (dcr_base
== 0 || dcr_len
== 0) {
1174 ppc4xx_edac_printk(KERN_ERR
,
1175 "Failed to obtain DCR property.\n");
1179 if (dcr_len
!= SDRAM_DCR_RESOURCE_LEN
) {
1180 ppc4xx_edac_printk(KERN_ERR
,
1181 "Unexpected DCR length %d, expected %d.\n",
1182 dcr_len
, SDRAM_DCR_RESOURCE_LEN
);
1186 /* Attempt to map the DCR extent. */
1188 *dcr_host
= dcr_map(np
, dcr_base
, dcr_len
);
1190 if (!DCR_MAP_OK(*dcr_host
)) {
1191 ppc4xx_edac_printk(KERN_INFO
, "Failed to map DCRs.\n");
1199 * ppc4xx_edac_probe - check controller and bind driver
1200 * @op: A pointer to the OpenFirmware device tree node associated
1201 * with the controller being probed for driver binding.
1203 * This routine probes a specific ibm,sdram-4xx-ddr2 controller
1204 * instance for binding with the driver.
1206 * Returns 0 if the controller instance was successfully bound to the
1207 * driver; otherwise, < 0 on error.
1209 static int ppc4xx_edac_probe(struct platform_device
*op
)
1212 u32 mcopt1
, memcheck
;
1213 dcr_host_t dcr_host
;
1214 const struct device_node
*np
= op
->dev
.of_node
;
1215 struct mem_ctl_info
*mci
= NULL
;
1216 struct edac_mc_layer layers
[2];
1217 static int ppc4xx_edac_instance
;
1220 * At this point, we only support the controller realized on
1221 * the AMCC PPC 405EX[r]. Reject anything else.
1224 if (!of_device_is_compatible(np
, "ibm,sdram-405ex") &&
1225 !of_device_is_compatible(np
, "ibm,sdram-405exr")) {
1226 ppc4xx_edac_printk(KERN_NOTICE
,
1227 "Only the PPC405EX[r] is supported.\n");
1232 * Next, get the DCR property and attempt to map it so that we
1233 * can probe the controller.
1236 status
= ppc4xx_edac_map_dcrs(np
, &dcr_host
);
1242 * First determine whether ECC is enabled at all. If not,
1243 * there is no useful checking or monitoring that can be done
1244 * for this controller.
1247 mcopt1
= mfsdram(&dcr_host
, SDRAM_MCOPT1
);
1248 memcheck
= (mcopt1
& SDRAM_MCOPT1_MCHK_MASK
);
1250 if (memcheck
== SDRAM_MCOPT1_MCHK_NON
) {
1251 ppc4xx_edac_printk(KERN_INFO
, "%pOF: No ECC memory detected or "
1252 "ECC is disabled.\n", np
);
1258 * At this point, we know ECC is enabled, allocate an EDAC
1259 * controller instance and perform the appropriate
1262 layers
[0].type
= EDAC_MC_LAYER_CHIP_SELECT
;
1263 layers
[0].size
= ppc4xx_edac_nr_csrows
;
1264 layers
[0].is_virt_csrow
= true;
1265 layers
[1].type
= EDAC_MC_LAYER_CHANNEL
;
1266 layers
[1].size
= ppc4xx_edac_nr_chans
;
1267 layers
[1].is_virt_csrow
= false;
1268 mci
= edac_mc_alloc(ppc4xx_edac_instance
, ARRAY_SIZE(layers
), layers
,
1269 sizeof(struct ppc4xx_edac_pdata
));
1271 ppc4xx_edac_printk(KERN_ERR
, "%pOF: "
1272 "Failed to allocate EDAC MC instance!\n",
1278 status
= ppc4xx_edac_mc_init(mci
, op
, &dcr_host
, mcopt1
);
1281 ppc4xx_edac_mc_printk(KERN_ERR
, mci
,
1282 "Failed to initialize instance!\n");
1287 * We have a valid, initialized EDAC instance bound to the
1288 * controller. Attempt to register it with the EDAC subsystem
1289 * and, if necessary, register interrupts.
1292 if (edac_mc_add_mc(mci
)) {
1293 ppc4xx_edac_mc_printk(KERN_ERR
, mci
,
1294 "Failed to add instance!\n");
1299 if (edac_op_state
== EDAC_OPSTATE_INT
) {
1300 status
= ppc4xx_edac_register_irq(op
, mci
);
1306 ppc4xx_edac_instance
++;
1311 edac_mc_del_mc(mci
->pdev
);
1321 * ppc4xx_edac_remove - unbind driver from controller
1322 * @op: A pointer to the OpenFirmware device tree node associated
1323 * with the controller this EDAC instance is to be unbound/removed
1326 * This routine unbinds the EDAC memory controller instance associated
1327 * with the specified ibm,sdram-4xx-ddr2 controller described by the
1328 * OpenFirmware device tree node passed as a parameter.
1330 * Unconditionally returns 0.
1332 static void ppc4xx_edac_remove(struct platform_device
*op
)
1334 struct mem_ctl_info
*mci
= dev_get_drvdata(&op
->dev
);
1335 struct ppc4xx_edac_pdata
*pdata
= mci
->pvt_info
;
1337 if (edac_op_state
== EDAC_OPSTATE_INT
) {
1338 free_irq(pdata
->irqs
.sec
, mci
);
1339 free_irq(pdata
->irqs
.ded
, mci
);
1342 dcr_unmap(pdata
->dcr_host
, SDRAM_DCR_RESOURCE_LEN
);
1344 edac_mc_del_mc(mci
->pdev
);
1349 * ppc4xx_edac_opstate_init - initialize EDAC reporting method
1351 * This routine ensures that the EDAC memory controller reporting
1352 * method is mapped to a sane value as the EDAC core defines the value
1353 * to EDAC_OPSTATE_INVAL by default. We don't call the global
1354 * opstate_init as that defaults to polling and we want interrupt as
1357 static inline void __init
1358 ppc4xx_edac_opstate_init(void)
1360 switch (edac_op_state
) {
1361 case EDAC_OPSTATE_POLL
:
1362 case EDAC_OPSTATE_INT
:
1365 edac_op_state
= EDAC_OPSTATE_INT
;
1369 ppc4xx_edac_printk(KERN_INFO
, "Reporting type: %s\n",
1370 ((edac_op_state
== EDAC_OPSTATE_POLL
) ?
1371 EDAC_OPSTATE_POLL_STR
:
1372 ((edac_op_state
== EDAC_OPSTATE_INT
) ?
1373 EDAC_OPSTATE_INT_STR
:
1374 EDAC_OPSTATE_UNKNOWN_STR
)));
1377 static struct platform_driver ppc4xx_edac_driver
= {
1378 .probe
= ppc4xx_edac_probe
,
1379 .remove_new
= ppc4xx_edac_remove
,
1381 .name
= PPC4XX_EDAC_MODULE_NAME
,
1382 .of_match_table
= ppc4xx_edac_match
,
1387 * ppc4xx_edac_init - driver/module insertion entry point
1389 * This routine is the driver/module insertion entry point. It
1390 * initializes the EDAC memory controller reporting state and
1391 * registers the driver as an OpenFirmware device tree platform
1395 ppc4xx_edac_init(void)
1397 ppc4xx_edac_printk(KERN_INFO
, PPC4XX_EDAC_MODULE_REVISION
"\n");
1399 ppc4xx_edac_opstate_init();
1401 return platform_driver_register(&ppc4xx_edac_driver
);
1405 * ppc4xx_edac_exit - driver/module removal entry point
1407 * This routine is the driver/module removal entry point. It
1408 * unregisters the driver as an OpenFirmware device tree platform
1412 ppc4xx_edac_exit(void)
1414 platform_driver_unregister(&ppc4xx_edac_driver
);
1417 module_init(ppc4xx_edac_init
);
1418 module_exit(ppc4xx_edac_exit
);
1420 MODULE_LICENSE("GPL v2");
1421 MODULE_AUTHOR("Grant Erickson <gerickson@nuovations.com>");
1422 MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller");
1423 module_param(edac_op_state
, int, 0444);
1424 MODULE_PARM_DESC(edac_op_state
, "EDAC Error Reporting State: "
1425 "0=" EDAC_OPSTATE_POLL_STR
", 2=" EDAC_OPSTATE_INT_STR
);