1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
4 #define pr_fmt(fmt) "mips-gic-timer: " fmt
7 #include <linux/clockchips.h>
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
11 #include <linux/notifier.h>
12 #include <linux/of_irq.h>
13 #include <linux/percpu.h>
14 #include <linux/sched_clock.h>
15 #include <linux/smp.h>
16 #include <linux/time.h>
17 #include <asm/mips-cps.h>
19 static DEFINE_PER_CPU(struct clock_event_device
, gic_clockevent_device
);
20 static int gic_timer_irq
;
21 static unsigned int gic_frequency
;
22 static unsigned int gic_count_width
;
23 static bool __read_mostly gic_clock_unstable
;
25 static void gic_clocksource_unstable(char *reason
);
27 static u64 notrace
gic_read_count_2x32(void)
29 unsigned int hi
, hi2
, lo
;
32 hi
= read_gic_counter_32h();
33 lo
= read_gic_counter_32l();
34 hi2
= read_gic_counter_32h();
37 return (((u64
) hi
) << 32) + lo
;
40 static u64 notrace
gic_read_count_64(void)
42 return read_gic_counter();
45 static u64 notrace
gic_read_count(void)
48 return gic_read_count_64();
50 return gic_read_count_2x32();
53 static int gic_next_event(unsigned long delta
, struct clock_event_device
*evt
)
55 int cpu
= cpumask_first(evt
->cpumask
);
59 cnt
= gic_read_count();
61 if (cpu
== raw_smp_processor_id()) {
62 write_gic_vl_compare(cnt
);
64 write_gic_vl_other(mips_cm_vp_id(cpu
));
65 write_gic_vo_compare(cnt
);
67 res
= ((int)(gic_read_count() - cnt
) >= 0) ? -ETIME
: 0;
71 static irqreturn_t
gic_compare_interrupt(int irq
, void *dev_id
)
73 struct clock_event_device
*cd
= dev_id
;
75 write_gic_vl_compare(read_gic_vl_compare());
76 cd
->event_handler(cd
);
80 static struct irqaction gic_compare_irqaction
= {
81 .handler
= gic_compare_interrupt
,
82 .percpu_dev_id
= &gic_clockevent_device
,
83 .flags
= IRQF_PERCPU
| IRQF_TIMER
,
87 static void gic_clockevent_cpu_init(unsigned int cpu
,
88 struct clock_event_device
*cd
)
90 cd
->name
= "MIPS GIC";
91 cd
->features
= CLOCK_EVT_FEAT_ONESHOT
|
92 CLOCK_EVT_FEAT_C3STOP
;
95 cd
->irq
= gic_timer_irq
;
96 cd
->cpumask
= cpumask_of(cpu
);
97 cd
->set_next_event
= gic_next_event
;
99 clockevents_config_and_register(cd
, gic_frequency
, 0x300, 0x7fffffff);
101 enable_percpu_irq(gic_timer_irq
, IRQ_TYPE_NONE
);
104 static void gic_clockevent_cpu_exit(struct clock_event_device
*cd
)
106 disable_percpu_irq(gic_timer_irq
);
109 static void gic_update_frequency(void *data
)
111 unsigned long rate
= (unsigned long)data
;
113 clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device
), rate
);
116 static int gic_starting_cpu(unsigned int cpu
)
118 gic_clockevent_cpu_init(cpu
, this_cpu_ptr(&gic_clockevent_device
));
122 static int gic_clk_notifier(struct notifier_block
*nb
, unsigned long action
,
125 struct clk_notifier_data
*cnd
= data
;
127 if (action
== POST_RATE_CHANGE
) {
128 gic_clocksource_unstable("ref clock rate change");
129 on_each_cpu(gic_update_frequency
, (void *)cnd
->new_rate
, 1);
135 static int gic_dying_cpu(unsigned int cpu
)
137 gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device
));
141 static struct notifier_block gic_clk_nb
= {
142 .notifier_call
= gic_clk_notifier
,
145 static int gic_clockevent_init(void)
152 ret
= setup_percpu_irq(gic_timer_irq
, &gic_compare_irqaction
);
154 pr_err("IRQ %d setup failed (%d)\n", gic_timer_irq
, ret
);
158 cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING
,
159 "clockevents/mips/gic/timer:starting",
160 gic_starting_cpu
, gic_dying_cpu
);
164 static u64
gic_hpt_read(struct clocksource
*cs
)
166 return gic_read_count();
169 static struct clocksource gic_clocksource
= {
171 .read
= gic_hpt_read
,
172 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
173 .vdso_clock_mode
= VDSO_CLOCKMODE_GIC
,
176 static void gic_clocksource_unstable(char *reason
)
178 if (gic_clock_unstable
)
181 gic_clock_unstable
= true;
183 pr_info("GIC timer is unstable due to %s\n", reason
);
185 clocksource_mark_unstable(&gic_clocksource
);
188 static int __init
__gic_clocksource_init(void)
192 /* Set clocksource mask. */
193 gic_count_width
= read_gic_config() & GIC_CONFIG_COUNTBITS
;
194 gic_count_width
>>= __ffs(GIC_CONFIG_COUNTBITS
);
195 gic_count_width
*= 4;
196 gic_count_width
+= 32;
197 gic_clocksource
.mask
= CLOCKSOURCE_MASK(gic_count_width
);
199 /* Calculate a somewhat reasonable rating value. */
200 if (mips_cm_revision() >= CM_REV_CM3
|| !IS_ENABLED(CONFIG_CPU_FREQ
))
201 gic_clocksource
.rating
= 300; /* Good when frequecy is stable */
203 gic_clocksource
.rating
= 200;
204 gic_clocksource
.rating
+= clamp(gic_frequency
/ 10000000, 0, 99);
206 ret
= clocksource_register_hz(&gic_clocksource
, gic_frequency
);
208 pr_warn("Unable to register clocksource\n");
213 static int __init
gic_clocksource_of_init(struct device_node
*node
)
218 if (!mips_gic_present() || !node
->parent
||
219 !of_device_is_compatible(node
->parent
, "mti,gic")) {
220 pr_warn("No DT definition\n");
224 clk
= of_clk_get(node
, 0);
226 ret
= clk_prepare_enable(clk
);
228 pr_err("Failed to enable clock\n");
233 gic_frequency
= clk_get_rate(clk
);
234 } else if (of_property_read_u32(node
, "clock-frequency",
236 pr_err("Frequency not specified\n");
239 gic_timer_irq
= irq_of_parse_and_map(node
, 0);
240 if (!gic_timer_irq
) {
241 pr_err("IRQ not specified\n");
245 ret
= __gic_clocksource_init();
249 ret
= gic_clockevent_init();
250 if (!ret
&& !IS_ERR(clk
)) {
251 if (clk_notifier_register(clk
, &gic_clk_nb
) < 0)
252 pr_warn("Unable to register clock notifier\n");
255 /* And finally start the counter */
256 clear_gic_config(GIC_CONFIG_COUNTSTOP
);
259 * It's safe to use the MIPS GIC timer as a sched clock source only if
260 * its ticks are stable, which is true on either the platforms with
261 * stable CPU frequency or on the platforms with CM3 and CPU frequency
262 * change performed by the CPC core clocks divider.
264 if (mips_cm_revision() >= CM_REV_CM3
|| !IS_ENABLED(CONFIG_CPU_FREQ
)) {
265 sched_clock_register(mips_cm_is64
?
266 gic_read_count_64
: gic_read_count_2x32
,
267 gic_count_width
, gic_frequency
);
272 TIMER_OF_DECLARE(mips_gic_timer
, "mti,gic-timer",
273 gic_clocksource_of_init
);