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serial: fix race between flush_to_ldisc and tty_open
[linux-stable.git] / drivers / iommu / intel_irq_remapping.c
blob25842b566c39c1497d1cecd91b6af8a079492185
1 // SPDX-License-Identifier: GPL-2.0
2
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
4
5 #include <linux/interrupt.h>
6 #include <linux/dmar.h>
7 #include <linux/spinlock.h>
8 #include <linux/slab.h>
9 #include <linux/jiffies.h>
10 #include <linux/hpet.h>
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/intel-iommu.h>
14 #include <linux/acpi.h>
15 #include <linux/irqdomain.h>
16 #include <linux/crash_dump.h>
17 #include <asm/io_apic.h>
18 #include <asm/smp.h>
19 #include <asm/cpu.h>
20 #include <asm/irq_remapping.h>
21 #include <asm/pci-direct.h>
22 #include <asm/msidef.h>
23
24 #include "irq_remapping.h"
25
26 enum irq_mode {
27 IRQ_REMAPPING,
28 IRQ_POSTING,
29 };
30
31 struct ioapic_scope {
32 struct intel_iommu *iommu;
33 unsigned int id;
34 unsigned int bus; /* PCI bus number */
35 unsigned int devfn; /* PCI devfn number */
36 };
37
38 struct hpet_scope {
39 struct intel_iommu *iommu;
40 u8 id;
41 unsigned int bus;
42 unsigned int devfn;
43 };
44
45 struct irq_2_iommu {
46 struct intel_iommu *iommu;
47 u16 irte_index;
48 u16 sub_handle;
49 u8 irte_mask;
50 enum irq_mode mode;
51 };
52
53 struct intel_ir_data {
54 struct irq_2_iommu irq_2_iommu;
55 struct irte irte_entry;
56 union {
57 struct msi_msg msi_entry;
58 };
59 };
60
61 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
62 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
63
64 static int __read_mostly eim_mode;
65 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
66 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
67
68 /*
69 * Lock ordering:
70 * ->dmar_global_lock
71 * ->irq_2_ir_lock
72 * ->qi->q_lock
73 * ->iommu->register_lock
74 * Note:
75 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
76 * in single-threaded environment with interrupt disabled, so no need to tabke
77 * the dmar_global_lock.
78 */
79 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
80 static const struct irq_domain_ops intel_ir_domain_ops;
81
82 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
83 static int __init parse_ioapics_under_ir(void);
84
85 static bool ir_pre_enabled(struct intel_iommu *iommu)
86 {
87 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
88 }
89
90 static void clear_ir_pre_enabled(struct intel_iommu *iommu)
91 {
92 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
93 }
94
95 static void init_ir_status(struct intel_iommu *iommu)
96 {
97 u32 gsts;
98
99 gsts = readl(iommu->reg + DMAR_GSTS_REG);
100 if (gsts & DMA_GSTS_IRES)
101 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
102 }
103
104 static int alloc_irte(struct intel_iommu *iommu, int irq,
105 struct irq_2_iommu *irq_iommu, u16 count)
106 {
107 struct ir_table *table = iommu->ir_table;
108 unsigned int mask = 0;
109 unsigned long flags;
110 int index;
111
112 if (!count || !irq_iommu)
113 return -1;
114
115 if (count > 1) {
116 count = __roundup_pow_of_two(count);
117 mask = ilog2(count);
118 }
119
120 if (mask > ecap_max_handle_mask(iommu->ecap)) {
121 pr_err("Requested mask %x exceeds the max invalidation handle"
122 " mask value %Lx\n", mask,
123 ecap_max_handle_mask(iommu->ecap));
124 return -1;
125 }
126
127 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
128 index = bitmap_find_free_region(table->bitmap,
129 INTR_REMAP_TABLE_ENTRIES, mask);
130 if (index < 0) {
131 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
132 } else {
133 irq_iommu->iommu = iommu;
134 irq_iommu->irte_index = index;
135 irq_iommu->sub_handle = 0;
136 irq_iommu->irte_mask = mask;
137 irq_iommu->mode = IRQ_REMAPPING;
138 }
139 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
140
141 return index;
142 }
143
144 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
145 {
146 struct qi_desc desc;
147
148 desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
149 | QI_IEC_SELECTIVE;
150 desc.high = 0;
151
152 return qi_submit_sync(&desc, iommu);
153 }
154
155 static int modify_irte(struct irq_2_iommu *irq_iommu,
156 struct irte *irte_modified)
157 {
158 struct intel_iommu *iommu;
159 unsigned long flags;
160 struct irte *irte;
161 int rc, index;
162
163 if (!irq_iommu)
164 return -1;
165
166 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
167
168 iommu = irq_iommu->iommu;
169
170 index = irq_iommu->irte_index + irq_iommu->sub_handle;
171 irte = &iommu->ir_table->base[index];
172
173 #if defined(CONFIG_HAVE_CMPXCHG_DOUBLE)
174 if ((irte->pst == 1) || (irte_modified->pst == 1)) {
175 bool ret;
176
177 ret = cmpxchg_double(&irte->low, &irte->high,
178 irte->low, irte->high,
179 irte_modified->low, irte_modified->high);
180 /*
181 * We use cmpxchg16 to atomically update the 128-bit IRTE,
182 * and it cannot be updated by the hardware or other processors
183 * behind us, so the return value of cmpxchg16 should be the
184 * same as the old value.
185 */
186 WARN_ON(!ret);
187 } else
188 #endif
189 {
190 set_64bit(&irte->low, irte_modified->low);
191 set_64bit(&irte->high, irte_modified->high);
192 }
193 __iommu_flush_cache(iommu, irte, sizeof(*irte));
194
195 rc = qi_flush_iec(iommu, index, 0);
196
197 /* Update iommu mode according to the IRTE mode */
198 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
199 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
200
201 return rc;
202 }
203
204 static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
205 {
206 int i;
207
208 for (i = 0; i < MAX_HPET_TBS; i++)
209 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
210 return ir_hpet[i].iommu;
211 return NULL;
212 }
213
214 static struct intel_iommu *map_ioapic_to_ir(int apic)
215 {
216 int i;
217
218 for (i = 0; i < MAX_IO_APICS; i++)
219 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
220 return ir_ioapic[i].iommu;
221 return NULL;
222 }
223
224 static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
225 {
226 struct dmar_drhd_unit *drhd;
227
228 drhd = dmar_find_matched_drhd_unit(dev);
229 if (!drhd)
230 return NULL;
231
232 return drhd->iommu;
233 }
234
235 static int clear_entries(struct irq_2_iommu *irq_iommu)
236 {
237 struct irte *start, *entry, *end;
238 struct intel_iommu *iommu;
239 int index;
240
241 if (irq_iommu->sub_handle)
242 return 0;
243
244 iommu = irq_iommu->iommu;
245 index = irq_iommu->irte_index;
246
247 start = iommu->ir_table->base + index;
248 end = start + (1 << irq_iommu->irte_mask);
249
250 for (entry = start; entry < end; entry++) {
251 set_64bit(&entry->low, 0);
252 set_64bit(&entry->high, 0);
253 }
254 bitmap_release_region(iommu->ir_table->bitmap, index,
255 irq_iommu->irte_mask);
256
257 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
258 }
259
260 /*
261 * source validation type
262 */
263 #define SVT_NO_VERIFY 0x0 /* no verification is required */
264 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
265 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
266
267 /*
268 * source-id qualifier
269 */
270 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
271 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
272 * the third least significant bit
273 */
274 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
275 * the second and third least significant bits
276 */
277 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
278 * the least three significant bits
279 */
280
281 /*
282 * set SVT, SQ and SID fields of irte to verify
283 * source ids of interrupt requests
284 */
285 static void set_irte_sid(struct irte *irte, unsigned int svt,
286 unsigned int sq, unsigned int sid)
287 {
288 if (disable_sourceid_checking)
289 svt = SVT_NO_VERIFY;
290 irte->svt = svt;
291 irte->sq = sq;
292 irte->sid = sid;
293 }
294
295 static int set_ioapic_sid(struct irte *irte, int apic)
296 {
297 int i;
298 u16 sid = 0;
299
300 if (!irte)
301 return -1;
302
303 down_read(&dmar_global_lock);
304 for (i = 0; i < MAX_IO_APICS; i++) {
305 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
306 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
307 break;
308 }
309 }
310 up_read(&dmar_global_lock);
311
312 if (sid == 0) {
313 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
314 return -1;
315 }
316
317 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
318
319 return 0;
320 }
321
322 static int set_hpet_sid(struct irte *irte, u8 id)
323 {
324 int i;
325 u16 sid = 0;
326
327 if (!irte)
328 return -1;
329
330 down_read(&dmar_global_lock);
331 for (i = 0; i < MAX_HPET_TBS; i++) {
332 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
333 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
334 break;
335 }
336 }
337 up_read(&dmar_global_lock);
338
339 if (sid == 0) {
340 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
341 return -1;
342 }
343
344 /*
345 * Should really use SQ_ALL_16. Some platforms are broken.
346 * While we figure out the right quirks for these broken platforms, use
347 * SQ_13_IGNORE_3 for now.
348 */
349 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
350
351 return 0;
352 }
353
354 struct set_msi_sid_data {
355 struct pci_dev *pdev;
356 u16 alias;
357 };
358
359 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
360 {
361 struct set_msi_sid_data *data = opaque;
362
363 data->pdev = pdev;
364 data->alias = alias;
365
366 return 0;
367 }
368
369 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
370 {
371 struct set_msi_sid_data data;
372
373 if (!irte || !dev)
374 return -1;
375
376 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
377
378 /*
379 * DMA alias provides us with a PCI device and alias. The only case
380 * where the it will return an alias on a different bus than the
381 * device is the case of a PCIe-to-PCI bridge, where the alias is for
382 * the subordinate bus. In this case we can only verify the bus.
383 *
384 * If the alias device is on a different bus than our source device
385 * then we have a topology based alias, use it.
386 *
387 * Otherwise, the alias is for a device DMA quirk and we cannot
388 * assume that MSI uses the same requester ID. Therefore use the
389 * original device.
390 */
391 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
392 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
393 PCI_DEVID(PCI_BUS_NUM(data.alias),
394 dev->bus->number));
395 else if (data.pdev->bus->number != dev->bus->number)
396 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
397 else
398 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
399 PCI_DEVID(dev->bus->number, dev->devfn));
400
401 return 0;
402 }
403
404 static int iommu_load_old_irte(struct intel_iommu *iommu)
405 {
406 struct irte *old_ir_table;
407 phys_addr_t irt_phys;
408 unsigned int i;
409 size_t size;
410 u64 irta;
411
412 /* Check whether the old ir-table has the same size as ours */
413 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
414 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
415 != INTR_REMAP_TABLE_REG_SIZE)
416 return -EINVAL;
417
418 irt_phys = irta & VTD_PAGE_MASK;
419 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
420
421 /* Map the old IR table */
422 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
423 if (!old_ir_table)
424 return -ENOMEM;
425
426 /* Copy data over */
427 memcpy(iommu->ir_table->base, old_ir_table, size);
428
429 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
430
431 /*
432 * Now check the table for used entries and mark those as
433 * allocated in the bitmap
434 */
435 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
436 if (iommu->ir_table->base[i].present)
437 bitmap_set(iommu->ir_table->bitmap, i, 1);
438 }
439
440 memunmap(old_ir_table);
441
442 return 0;
443 }
444
445
446 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
447 {
448 unsigned long flags;
449 u64 addr;
450 u32 sts;
451
452 addr = virt_to_phys((void *)iommu->ir_table->base);
453
454 raw_spin_lock_irqsave(&iommu->register_lock, flags);
455
456 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
457 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
458
459 /* Set interrupt-remapping table pointer */
460 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
461
462 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
463 readl, (sts & DMA_GSTS_IRTPS), sts);
464 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
465
466 /*
467 * Global invalidation of interrupt entry cache to make sure the
468 * hardware uses the new irq remapping table.
469 */
470 qi_global_iec(iommu);
471 }
472
473 static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
474 {
475 unsigned long flags;
476 u32 sts;
477
478 raw_spin_lock_irqsave(&iommu->register_lock, flags);
479
480 /* Enable interrupt-remapping */
481 iommu->gcmd |= DMA_GCMD_IRE;
482 iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
483 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
484
485 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
486 readl, (sts & DMA_GSTS_IRES), sts);
487
488 /*
489 * With CFI clear in the Global Command register, we should be
490 * protected from dangerous (i.e. compatibility) interrupts
491 * regardless of x2apic status. Check just to be sure.
492 */
493 if (sts & DMA_GSTS_CFIS)
494 WARN(1, KERN_WARNING
495 "Compatibility-format IRQs enabled despite intr remapping;\n"
496 "you are vulnerable to IRQ injection.\n");
497
498 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
499 }
500
501 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
502 {
503 struct ir_table *ir_table;
504 struct fwnode_handle *fn;
505 unsigned long *bitmap;
506 struct page *pages;
507
508 if (iommu->ir_table)
509 return 0;
510
511 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
512 if (!ir_table)
513 return -ENOMEM;
514
515 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
516 INTR_REMAP_PAGE_ORDER);
517 if (!pages) {
518 pr_err("IR%d: failed to allocate pages of order %d\n",
519 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
520 goto out_free_table;
521 }
522
523 bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
524 sizeof(long), GFP_ATOMIC);
525 if (bitmap == NULL) {
526 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
527 goto out_free_pages;
528 }
529
530 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
531 if (!fn)
532 goto out_free_bitmap;
533
534 iommu->ir_domain =
535 irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
536 0, INTR_REMAP_TABLE_ENTRIES,
537 fn, &intel_ir_domain_ops,
538 iommu);
539 irq_domain_free_fwnode(fn);
540 if (!iommu->ir_domain) {
541 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
542 goto out_free_bitmap;
543 }
544 iommu->ir_msi_domain =
545 arch_create_remap_msi_irq_domain(iommu->ir_domain,
546 "INTEL-IR-MSI",
547 iommu->seq_id);
548
549 ir_table->base = page_address(pages);
550 ir_table->bitmap = bitmap;
551 iommu->ir_table = ir_table;
552
553 /*
554 * If the queued invalidation is already initialized,
555 * shouldn't disable it.
556 */
557 if (!iommu->qi) {
558 /*
559 * Clear previous faults.
560 */
561 dmar_fault(-1, iommu);
562 dmar_disable_qi(iommu);
563
564 if (dmar_enable_qi(iommu)) {
565 pr_err("Failed to enable queued invalidation\n");
566 goto out_free_bitmap;
567 }
568 }
569
570 init_ir_status(iommu);
571
572 if (ir_pre_enabled(iommu)) {
573 if (!is_kdump_kernel()) {
574 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
575 iommu->name);
576 clear_ir_pre_enabled(iommu);
577 iommu_disable_irq_remapping(iommu);
578 } else if (iommu_load_old_irte(iommu))
579 pr_err("Failed to copy IR table for %s from previous kernel\n",
580 iommu->name);
581 else
582 pr_info("Copied IR table for %s from previous kernel\n",
583 iommu->name);
584 }
585
586 iommu_set_irq_remapping(iommu, eim_mode);
587
588 return 0;
589
590 out_free_bitmap:
591 kfree(bitmap);
592 out_free_pages:
593 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
594 out_free_table:
595 kfree(ir_table);
596
597 iommu->ir_table = NULL;
598
599 return -ENOMEM;
600 }
601
602 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
603 {
604 if (iommu && iommu->ir_table) {
605 if (iommu->ir_msi_domain) {
606 irq_domain_remove(iommu->ir_msi_domain);
607 iommu->ir_msi_domain = NULL;
608 }
609 if (iommu->ir_domain) {
610 irq_domain_remove(iommu->ir_domain);
611 iommu->ir_domain = NULL;
612 }
613 free_pages((unsigned long)iommu->ir_table->base,
614 INTR_REMAP_PAGE_ORDER);
615 kfree(iommu->ir_table->bitmap);
616 kfree(iommu->ir_table);
617 iommu->ir_table = NULL;
618 }
619 }
620
621 /*
622 * Disable Interrupt Remapping.
623 */
624 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
625 {
626 unsigned long flags;
627 u32 sts;
628
629 if (!ecap_ir_support(iommu->ecap))
630 return;
631
632 /*
633 * global invalidation of interrupt entry cache before disabling
634 * interrupt-remapping.
635 */
636 qi_global_iec(iommu);
637
638 raw_spin_lock_irqsave(&iommu->register_lock, flags);
639
640 sts = readl(iommu->reg + DMAR_GSTS_REG);
641 if (!(sts & DMA_GSTS_IRES))
642 goto end;
643
644 iommu->gcmd &= ~DMA_GCMD_IRE;
645 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
646
647 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
648 readl, !(sts & DMA_GSTS_IRES), sts);
649
650 end:
651 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
652 }
653
654 static int __init dmar_x2apic_optout(void)
655 {
656 struct acpi_table_dmar *dmar;
657 dmar = (struct acpi_table_dmar *)dmar_tbl;
658 if (!dmar || no_x2apic_optout)
659 return 0;
660 return dmar->flags & DMAR_X2APIC_OPT_OUT;
661 }
662
663 static void __init intel_cleanup_irq_remapping(void)
664 {
665 struct dmar_drhd_unit *drhd;
666 struct intel_iommu *iommu;
667
668 for_each_iommu(iommu, drhd) {
669 if (ecap_ir_support(iommu->ecap)) {
670 iommu_disable_irq_remapping(iommu);
671 intel_teardown_irq_remapping(iommu);
672 }
673 }
674
675 if (x2apic_supported())
676 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
677 }
678
679 static int __init intel_prepare_irq_remapping(void)
680 {
681 struct dmar_drhd_unit *drhd;
682 struct intel_iommu *iommu;
683 int eim = 0;
684
685 if (irq_remap_broken) {
686 pr_warn("This system BIOS has enabled interrupt remapping\n"
687 "on a chipset that contains an erratum making that\n"
688 "feature unstable. To maintain system stability\n"
689 "interrupt remapping is being disabled. Please\n"
690 "contact your BIOS vendor for an update\n");
691 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
692 return -ENODEV;
693 }
694
695 if (dmar_table_init() < 0)
696 return -ENODEV;
697
698 if (!dmar_ir_support())
699 return -ENODEV;
700
701 if (parse_ioapics_under_ir()) {
702 pr_info("Not enabling interrupt remapping\n");
703 goto error;
704 }
705
706 /* First make sure all IOMMUs support IRQ remapping */
707 for_each_iommu(iommu, drhd)
708 if (!ecap_ir_support(iommu->ecap))
709 goto error;
710
711 /* Detect remapping mode: lapic or x2apic */
712 if (x2apic_supported()) {
713 eim = !dmar_x2apic_optout();
714 if (!eim) {
715 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
716 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
717 }
718 }
719
720 for_each_iommu(iommu, drhd) {
721 if (eim && !ecap_eim_support(iommu->ecap)) {
722 pr_info("%s does not support EIM\n", iommu->name);
723 eim = 0;
724 }
725 }
726
727 eim_mode = eim;
728 if (eim)
729 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
730
731 /* Do the initializations early */
732 for_each_iommu(iommu, drhd) {
733 if (intel_setup_irq_remapping(iommu)) {
734 pr_err("Failed to setup irq remapping for %s\n",
735 iommu->name);
736 goto error;
737 }
738 }
739
740 return 0;
741
742 error:
743 intel_cleanup_irq_remapping();
744 return -ENODEV;
745 }
746
747 /*
748 * Set Posted-Interrupts capability.
749 */
750 static inline void set_irq_posting_cap(void)
751 {
752 struct dmar_drhd_unit *drhd;
753 struct intel_iommu *iommu;
754
755 if (!disable_irq_post) {
756 /*
757 * If IRTE is in posted format, the 'pda' field goes across the
758 * 64-bit boundary, we need use cmpxchg16b to atomically update
759 * it. We only expose posted-interrupt when X86_FEATURE_CX16
760 * is supported. Actually, hardware platforms supporting PI
761 * should have X86_FEATURE_CX16 support, this has been confirmed
762 * with Intel hardware guys.
763 */
764 if (boot_cpu_has(X86_FEATURE_CX16))
765 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
766
767 for_each_iommu(iommu, drhd)
768 if (!cap_pi_support(iommu->cap)) {
769 intel_irq_remap_ops.capability &=
770 ~(1 << IRQ_POSTING_CAP);
771 break;
772 }
773 }
774 }
775
776 static int __init intel_enable_irq_remapping(void)
777 {
778 struct dmar_drhd_unit *drhd;
779 struct intel_iommu *iommu;
780 bool setup = false;
781
782 /*
783 * Setup Interrupt-remapping for all the DRHD's now.
784 */
785 for_each_iommu(iommu, drhd) {
786 if (!ir_pre_enabled(iommu))
787 iommu_enable_irq_remapping(iommu);
788 setup = true;
789 }
790
791 if (!setup)
792 goto error;
793
794 irq_remapping_enabled = 1;
795
796 set_irq_posting_cap();
797
798 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
799
800 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
801
802 error:
803 intel_cleanup_irq_remapping();
804 return -1;
805 }
806
807 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
808 struct intel_iommu *iommu,
809 struct acpi_dmar_hardware_unit *drhd)
810 {
811 struct acpi_dmar_pci_path *path;
812 u8 bus;
813 int count, free = -1;
814
815 bus = scope->bus;
816 path = (struct acpi_dmar_pci_path *)(scope + 1);
817 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
818 / sizeof(struct acpi_dmar_pci_path);
819
820 while (--count > 0) {
821 /*
822 * Access PCI directly due to the PCI
823 * subsystem isn't initialized yet.
824 */
825 bus = read_pci_config_byte(bus, path->device, path->function,
826 PCI_SECONDARY_BUS);
827 path++;
828 }
829
830 for (count = 0; count < MAX_HPET_TBS; count++) {
831 if (ir_hpet[count].iommu == iommu &&
832 ir_hpet[count].id == scope->enumeration_id)
833 return 0;
834 else if (ir_hpet[count].iommu == NULL && free == -1)
835 free = count;
836 }
837 if (free == -1) {
838 pr_warn("Exceeded Max HPET blocks\n");
839 return -ENOSPC;
840 }
841
842 ir_hpet[free].iommu = iommu;
843 ir_hpet[free].id = scope->enumeration_id;
844 ir_hpet[free].bus = bus;
845 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
846 pr_info("HPET id %d under DRHD base 0x%Lx\n",
847 scope->enumeration_id, drhd->address);
848
849 return 0;
850 }
851
852 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
853 struct intel_iommu *iommu,
854 struct acpi_dmar_hardware_unit *drhd)
855 {
856 struct acpi_dmar_pci_path *path;
857 u8 bus;
858 int count, free = -1;
859
860 bus = scope->bus;
861 path = (struct acpi_dmar_pci_path *)(scope + 1);
862 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
863 / sizeof(struct acpi_dmar_pci_path);
864
865 while (--count > 0) {
866 /*
867 * Access PCI directly due to the PCI
868 * subsystem isn't initialized yet.
869 */
870 bus = read_pci_config_byte(bus, path->device, path->function,
871 PCI_SECONDARY_BUS);
872 path++;
873 }
874
875 for (count = 0; count < MAX_IO_APICS; count++) {
876 if (ir_ioapic[count].iommu == iommu &&
877 ir_ioapic[count].id == scope->enumeration_id)
878 return 0;
879 else if (ir_ioapic[count].iommu == NULL && free == -1)
880 free = count;
881 }
882 if (free == -1) {
883 pr_warn("Exceeded Max IO APICS\n");
884 return -ENOSPC;
885 }
886
887 ir_ioapic[free].bus = bus;
888 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
889 ir_ioapic[free].iommu = iommu;
890 ir_ioapic[free].id = scope->enumeration_id;
891 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
892 scope->enumeration_id, drhd->address, iommu->seq_id);
893
894 return 0;
895 }
896
897 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
898 struct intel_iommu *iommu)
899 {
900 int ret = 0;
901 struct acpi_dmar_hardware_unit *drhd;
902 struct acpi_dmar_device_scope *scope;
903 void *start, *end;
904
905 drhd = (struct acpi_dmar_hardware_unit *)header;
906 start = (void *)(drhd + 1);
907 end = ((void *)drhd) + header->length;
908
909 while (start < end && ret == 0) {
910 scope = start;
911 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
912 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
913 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
914 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
915 start += scope->length;
916 }
917
918 return ret;
919 }
920
921 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
922 {
923 int i;
924
925 for (i = 0; i < MAX_HPET_TBS; i++)
926 if (ir_hpet[i].iommu == iommu)
927 ir_hpet[i].iommu = NULL;
928
929 for (i = 0; i < MAX_IO_APICS; i++)
930 if (ir_ioapic[i].iommu == iommu)
931 ir_ioapic[i].iommu = NULL;
932 }
933
934 /*
935 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
936 * hardware unit.
937 */
938 static int __init parse_ioapics_under_ir(void)
939 {
940 struct dmar_drhd_unit *drhd;
941 struct intel_iommu *iommu;
942 bool ir_supported = false;
943 int ioapic_idx;
944
945 for_each_iommu(iommu, drhd) {
946 int ret;
947
948 if (!ecap_ir_support(iommu->ecap))
949 continue;
950
951 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
952 if (ret)
953 return ret;
954
955 ir_supported = true;
956 }
957
958 if (!ir_supported)
959 return -ENODEV;
960
961 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
962 int ioapic_id = mpc_ioapic_id(ioapic_idx);
963 if (!map_ioapic_to_ir(ioapic_id)) {
964 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
965 "interrupt remapping will be disabled\n",
966 ioapic_id);
967 return -1;
968 }
969 }
970
971 return 0;
972 }
973
974 static int __init ir_dev_scope_init(void)
975 {
976 int ret;
977
978 if (!irq_remapping_enabled)
979 return 0;
980
981 down_write(&dmar_global_lock);
982 ret = dmar_dev_scope_init();
983 up_write(&dmar_global_lock);
984
985 return ret;
986 }
987 rootfs_initcall(ir_dev_scope_init);
988
989 static void disable_irq_remapping(void)
990 {
991 struct dmar_drhd_unit *drhd;
992 struct intel_iommu *iommu = NULL;
993
994 /*
995 * Disable Interrupt-remapping for all the DRHD's now.
996 */
997 for_each_iommu(iommu, drhd) {
998 if (!ecap_ir_support(iommu->ecap))
999 continue;
1000
1001 iommu_disable_irq_remapping(iommu);
1002 }
1003
1004 /*
1005 * Clear Posted-Interrupts capability.
1006 */
1007 if (!disable_irq_post)
1008 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
1009 }
1010
1011 static int reenable_irq_remapping(int eim)
1012 {
1013 struct dmar_drhd_unit *drhd;
1014 bool setup = false;
1015 struct intel_iommu *iommu = NULL;
1016
1017 for_each_iommu(iommu, drhd)
1018 if (iommu->qi)
1019 dmar_reenable_qi(iommu);
1020
1021 /*
1022 * Setup Interrupt-remapping for all the DRHD's now.
1023 */
1024 for_each_iommu(iommu, drhd) {
1025 if (!ecap_ir_support(iommu->ecap))
1026 continue;
1027
1028 /* Set up interrupt remapping for iommu.*/
1029 iommu_set_irq_remapping(iommu, eim);
1030 iommu_enable_irq_remapping(iommu);
1031 setup = true;
1032 }
1033
1034 if (!setup)
1035 goto error;
1036
1037 set_irq_posting_cap();
1038
1039 return 0;
1040
1041 error:
1042 /*
1043 * handle error condition gracefully here!
1044 */
1045 return -1;
1046 }
1047
1048 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1049 {
1050 memset(irte, 0, sizeof(*irte));
1051
1052 irte->present = 1;
1053 irte->dst_mode = apic->irq_dest_mode;
1054 /*
1055 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1056 * actual level or edge trigger will be setup in the IO-APIC
1057 * RTE. This will help simplify level triggered irq migration.
1058 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1059 * irq migration in the presence of interrupt-remapping.
1060 */
1061 irte->trigger_mode = 0;
1062 irte->dlvry_mode = apic->irq_delivery_mode;
1063 irte->vector = vector;
1064 irte->dest_id = IRTE_DEST(dest);
1065 irte->redir_hint = 1;
1066 }
1067
1068 static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
1069 {
1070 struct intel_iommu *iommu = NULL;
1071
1072 if (!info)
1073 return NULL;
1074
1075 switch (info->type) {
1076 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1077 iommu = map_ioapic_to_ir(info->ioapic_id);
1078 break;
1079 case X86_IRQ_ALLOC_TYPE_HPET:
1080 iommu = map_hpet_to_ir(info->hpet_id);
1081 break;
1082 case X86_IRQ_ALLOC_TYPE_MSI:
1083 case X86_IRQ_ALLOC_TYPE_MSIX:
1084 iommu = map_dev_to_ir(info->msi_dev);
1085 break;
1086 default:
1087 BUG_ON(1);
1088 break;
1089 }
1090
1091 return iommu ? iommu->ir_domain : NULL;
1092 }
1093
1094 static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
1095 {
1096 struct intel_iommu *iommu;
1097
1098 if (!info)
1099 return NULL;
1100
1101 switch (info->type) {
1102 case X86_IRQ_ALLOC_TYPE_MSI:
1103 case X86_IRQ_ALLOC_TYPE_MSIX:
1104 iommu = map_dev_to_ir(info->msi_dev);
1105 if (iommu)
1106 return iommu->ir_msi_domain;
1107 break;
1108 default:
1109 break;
1110 }
1111
1112 return NULL;
1113 }
1114
1115 struct irq_remap_ops intel_irq_remap_ops = {
1116 .prepare = intel_prepare_irq_remapping,
1117 .enable = intel_enable_irq_remapping,
1118 .disable = disable_irq_remapping,
1119 .reenable = reenable_irq_remapping,
1120 .enable_faulting = enable_drhd_fault_handling,
1121 .get_ir_irq_domain = intel_get_ir_irq_domain,
1122 .get_irq_domain = intel_get_irq_domain,
1123 };
1124
1125 /*
1126 * Migrate the IO-APIC irq in the presence of intr-remapping.
1127 *
1128 * For both level and edge triggered, irq migration is a simple atomic
1129 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1130 *
1131 * For level triggered, we eliminate the io-apic RTE modification (with the
1132 * updated vector information), by using a virtual vector (io-apic pin number).
1133 * Real vector that is used for interrupting cpu will be coming from
1134 * the interrupt-remapping table entry.
1135 *
1136 * As the migration is a simple atomic update of IRTE, the same mechanism
1137 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1138 */
1139 static int
1140 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1141 bool force)
1142 {
1143 struct intel_ir_data *ir_data = data->chip_data;
1144 struct irte *irte = &ir_data->irte_entry;
1145 struct irq_cfg *cfg = irqd_cfg(data);
1146 struct irq_data *parent = data->parent_data;
1147 int ret;
1148
1149 ret = parent->chip->irq_set_affinity(parent, mask, force);
1150 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1151 return ret;
1152
1153 /*
1154 * Atomically updates the IRTE with the new destination, vector
1155 * and flushes the interrupt entry cache.
1156 */
1157 irte->vector = cfg->vector;
1158 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1159
1160 /* Update the hardware only if the interrupt is in remapped mode. */
1161 if (ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1162 modify_irte(&ir_data->irq_2_iommu, irte);
1163
1164 /*
1165 * After this point, all the interrupts will start arriving
1166 * at the new destination. So, time to cleanup the previous
1167 * vector allocation.
1168 */
1169 send_cleanup_vector(cfg);
1170
1171 return IRQ_SET_MASK_OK_DONE;
1172 }
1173
1174 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1175 struct msi_msg *msg)
1176 {
1177 struct intel_ir_data *ir_data = irq_data->chip_data;
1178
1179 *msg = ir_data->msi_entry;
1180 }
1181
1182 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1183 {
1184 struct intel_ir_data *ir_data = data->chip_data;
1185 struct vcpu_data *vcpu_pi_info = info;
1186
1187 /* stop posting interrupts, back to remapping mode */
1188 if (!vcpu_pi_info) {
1189 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1190 } else {
1191 struct irte irte_pi;
1192
1193 /*
1194 * We are not caching the posted interrupt entry. We
1195 * copy the data from the remapped entry and modify
1196 * the fields which are relevant for posted mode. The
1197 * cached remapped entry is used for switching back to
1198 * remapped mode.
1199 */
1200 memset(&irte_pi, 0, sizeof(irte_pi));
1201 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1202
1203 /* Update the posted mode fields */
1204 irte_pi.p_pst = 1;
1205 irte_pi.p_urgent = 0;
1206 irte_pi.p_vector = vcpu_pi_info->vector;
1207 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1208 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1209 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1210 ~(-1UL << PDA_HIGH_BIT);
1211
1212 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1213 }
1214
1215 return 0;
1216 }
1217
1218 static struct irq_chip intel_ir_chip = {
1219 .name = "INTEL-IR",
1220 .irq_ack = ir_ack_apic_edge,
1221 .irq_set_affinity = intel_ir_set_affinity,
1222 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1223 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1224 };
1225
1226 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1227 struct irq_cfg *irq_cfg,
1228 struct irq_alloc_info *info,
1229 int index, int sub_handle)
1230 {
1231 struct IR_IO_APIC_route_entry *entry;
1232 struct irte *irte = &data->irte_entry;
1233 struct msi_msg *msg = &data->msi_entry;
1234
1235 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1236 switch (info->type) {
1237 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1238 /* Set source-id of interrupt request */
1239 set_ioapic_sid(irte, info->ioapic_id);
1240 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1241 info->ioapic_id, irte->present, irte->fpd,
1242 irte->dst_mode, irte->redir_hint,
1243 irte->trigger_mode, irte->dlvry_mode,
1244 irte->avail, irte->vector, irte->dest_id,
1245 irte->sid, irte->sq, irte->svt);
1246
1247 entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
1248 info->ioapic_entry = NULL;
1249 memset(entry, 0, sizeof(*entry));
1250 entry->index2 = (index >> 15) & 0x1;
1251 entry->zero = 0;
1252 entry->format = 1;
1253 entry->index = (index & 0x7fff);
1254 /*
1255 * IO-APIC RTE will be configured with virtual vector.
1256 * irq handler will do the explicit EOI to the io-apic.
1257 */
1258 entry->vector = info->ioapic_pin;
1259 entry->mask = 0; /* enable IRQ */
1260 entry->trigger = info->ioapic_trigger;
1261 entry->polarity = info->ioapic_polarity;
1262 if (info->ioapic_trigger)
1263 entry->mask = 1; /* Mask level triggered irqs. */
1264 break;
1265
1266 case X86_IRQ_ALLOC_TYPE_HPET:
1267 case X86_IRQ_ALLOC_TYPE_MSI:
1268 case X86_IRQ_ALLOC_TYPE_MSIX:
1269 if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
1270 set_hpet_sid(irte, info->hpet_id);
1271 else
1272 set_msi_sid(irte, info->msi_dev);
1273
1274 msg->address_hi = MSI_ADDR_BASE_HI;
1275 msg->data = sub_handle;
1276 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1277 MSI_ADDR_IR_SHV |
1278 MSI_ADDR_IR_INDEX1(index) |
1279 MSI_ADDR_IR_INDEX2(index);
1280 break;
1281
1282 default:
1283 BUG_ON(1);
1284 break;
1285 }
1286 }
1287
1288 static void intel_free_irq_resources(struct irq_domain *domain,
1289 unsigned int virq, unsigned int nr_irqs)
1290 {
1291 struct irq_data *irq_data;
1292 struct intel_ir_data *data;
1293 struct irq_2_iommu *irq_iommu;
1294 unsigned long flags;
1295 int i;
1296 for (i = 0; i < nr_irqs; i++) {
1297 irq_data = irq_domain_get_irq_data(domain, virq + i);
1298 if (irq_data && irq_data->chip_data) {
1299 data = irq_data->chip_data;
1300 irq_iommu = &data->irq_2_iommu;
1301 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1302 clear_entries(irq_iommu);
1303 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1304 irq_domain_reset_irq_data(irq_data);
1305 kfree(data);
1306 }
1307 }
1308 }
1309
1310 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1311 unsigned int virq, unsigned int nr_irqs,
1312 void *arg)
1313 {
1314 struct intel_iommu *iommu = domain->host_data;
1315 struct irq_alloc_info *info = arg;
1316 struct intel_ir_data *data, *ird;
1317 struct irq_data *irq_data;
1318 struct irq_cfg *irq_cfg;
1319 int i, ret, index;
1320
1321 if (!info || !iommu)
1322 return -EINVAL;
1323 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
1324 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
1325 return -EINVAL;
1326
1327 /*
1328 * With IRQ remapping enabled, don't need contiguous CPU vectors
1329 * to support multiple MSI interrupts.
1330 */
1331 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
1332 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1333
1334 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1335 if (ret < 0)
1336 return ret;
1337
1338 ret = -ENOMEM;
1339 data = kzalloc(sizeof(*data), GFP_KERNEL);
1340 if (!data)
1341 goto out_free_parent;
1342
1343 down_read(&dmar_global_lock);
1344 index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs);
1345 up_read(&dmar_global_lock);
1346 if (index < 0) {
1347 pr_warn("Failed to allocate IRTE\n");
1348 kfree(data);
1349 goto out_free_parent;
1350 }
1351
1352 for (i = 0; i < nr_irqs; i++) {
1353 irq_data = irq_domain_get_irq_data(domain, virq + i);
1354 irq_cfg = irqd_cfg(irq_data);
1355 if (!irq_data || !irq_cfg) {
1356 ret = -EINVAL;
1357 goto out_free_data;
1358 }
1359
1360 if (i > 0) {
1361 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1362 if (!ird)
1363 goto out_free_data;
1364 /* Initialize the common data */
1365 ird->irq_2_iommu = data->irq_2_iommu;
1366 ird->irq_2_iommu.sub_handle = i;
1367 } else {
1368 ird = data;
1369 }
1370
1371 irq_data->hwirq = (index << 16) + i;
1372 irq_data->chip_data = ird;
1373 irq_data->chip = &intel_ir_chip;
1374 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1375 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1376 }
1377 return 0;
1378
1379 out_free_data:
1380 intel_free_irq_resources(domain, virq, i);
1381 out_free_parent:
1382 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1383 return ret;
1384 }
1385
1386 static void intel_irq_remapping_free(struct irq_domain *domain,
1387 unsigned int virq, unsigned int nr_irqs)
1388 {
1389 intel_free_irq_resources(domain, virq, nr_irqs);
1390 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1391 }
1392
1393 static void intel_irq_remapping_activate(struct irq_domain *domain,
1394 struct irq_data *irq_data)
1395 {
1396 struct intel_ir_data *data = irq_data->chip_data;
1397
1398 modify_irte(&data->irq_2_iommu, &data->irte_entry);
1399 }
1400
1401 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1402 struct irq_data *irq_data)
1403 {
1404 struct intel_ir_data *data = irq_data->chip_data;
1405 struct irte entry;
1406
1407 memset(&entry, 0, sizeof(entry));
1408 modify_irte(&data->irq_2_iommu, &entry);
1409 }
1410
1411 static const struct irq_domain_ops intel_ir_domain_ops = {
1412 .alloc = intel_irq_remapping_alloc,
1413 .free = intel_irq_remapping_free,
1414 .activate = intel_irq_remapping_activate,
1415 .deactivate = intel_irq_remapping_deactivate,
1416 };
1417
1418 /*
1419 * Support of Interrupt Remapping Unit Hotplug
1420 */
1421 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1422 {
1423 int ret;
1424 int eim = x2apic_enabled();
1425
1426 if (eim && !ecap_eim_support(iommu->ecap)) {
1427 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1428 iommu->reg_phys, iommu->ecap);
1429 return -ENODEV;
1430 }
1431
1432 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1433 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1434 iommu->reg_phys);
1435 return -ENODEV;
1436 }
1437
1438 /* TODO: check all IOAPICs are covered by IOMMU */
1439
1440 /* Setup Interrupt-remapping now. */
1441 ret = intel_setup_irq_remapping(iommu);
1442 if (ret) {
1443 pr_err("Failed to setup irq remapping for %s\n",
1444 iommu->name);
1445 intel_teardown_irq_remapping(iommu);
1446 ir_remove_ioapic_hpet_scope(iommu);
1447 } else {
1448 iommu_enable_irq_remapping(iommu);
1449 }
1450
1451 return ret;
1452 }
1453
1454 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1455 {
1456 int ret = 0;
1457 struct intel_iommu *iommu = dmaru->iommu;
1458
1459 if (!irq_remapping_enabled)
1460 return 0;
1461 if (iommu == NULL)
1462 return -EINVAL;
1463 if (!ecap_ir_support(iommu->ecap))
1464 return 0;
1465 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1466 !cap_pi_support(iommu->cap))
1467 return -EBUSY;
1468
1469 if (insert) {
1470 if (!iommu->ir_table)
1471 ret = dmar_ir_add(dmaru, iommu);
1472 } else {
1473 if (iommu->ir_table) {
1474 if (!bitmap_empty(iommu->ir_table->bitmap,
1475 INTR_REMAP_TABLE_ENTRIES)) {
1476 ret = -EBUSY;
1477 } else {
1478 iommu_disable_irq_remapping(iommu);
1479 intel_teardown_irq_remapping(iommu);
1480 ir_remove_ioapic_hpet_scope(iommu);
1481 }
1482 }
1483 }
1484
1485 return ret;
1486 }
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