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serial: fix race between flush_to_ldisc and tty_open
[linux-stable.git] / drivers / iommu / amd_iommu_init.c
blobb97984a5ddad24ff56e4f79a957788470d6859cf
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/interrupt.h>
27 #include <linux/msi.h>
28 #include <linux/amd-iommu.h>
29 #include <linux/export.h>
30 #include <linux/iommu.h>
31 #include <linux/kmemleak.h>
32 #include <linux/mem_encrypt.h>
33 #include <asm/pci-direct.h>
34 #include <asm/iommu.h>
35 #include <asm/gart.h>
36 #include <asm/x86_init.h>
37 #include <asm/iommu_table.h>
38 #include <asm/io_apic.h>
39 #include <asm/irq_remapping.h>
40
41 #include <linux/crash_dump.h>
42 #include "amd_iommu_proto.h"
43 #include "amd_iommu_types.h"
44 #include "irq_remapping.h"
45
46 /*
47 * definitions for the ACPI scanning code
48 */
49 #define IVRS_HEADER_LENGTH 48
50
51 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
52 #define ACPI_IVMD_TYPE_ALL 0x20
53 #define ACPI_IVMD_TYPE 0x21
54 #define ACPI_IVMD_TYPE_RANGE 0x22
55
56 #define IVHD_DEV_ALL 0x01
57 #define IVHD_DEV_SELECT 0x02
58 #define IVHD_DEV_SELECT_RANGE_START 0x03
59 #define IVHD_DEV_RANGE_END 0x04
60 #define IVHD_DEV_ALIAS 0x42
61 #define IVHD_DEV_ALIAS_RANGE 0x43
62 #define IVHD_DEV_EXT_SELECT 0x46
63 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
64 #define IVHD_DEV_SPECIAL 0x48
65 #define IVHD_DEV_ACPI_HID 0xf0
66
67 #define UID_NOT_PRESENT 0
68 #define UID_IS_INTEGER 1
69 #define UID_IS_CHARACTER 2
70
71 #define IVHD_SPECIAL_IOAPIC 1
72 #define IVHD_SPECIAL_HPET 2
73
74 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
75 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
76 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
77 #define IVHD_FLAG_ISOC_EN_MASK 0x08
78
79 #define IVMD_FLAG_EXCL_RANGE 0x08
80 #define IVMD_FLAG_UNITY_MAP 0x01
81
82 #define ACPI_DEVFLAG_INITPASS 0x01
83 #define ACPI_DEVFLAG_EXTINT 0x02
84 #define ACPI_DEVFLAG_NMI 0x04
85 #define ACPI_DEVFLAG_SYSMGT1 0x10
86 #define ACPI_DEVFLAG_SYSMGT2 0x20
87 #define ACPI_DEVFLAG_LINT0 0x40
88 #define ACPI_DEVFLAG_LINT1 0x80
89 #define ACPI_DEVFLAG_ATSDIS 0x10000000
90
91 #define LOOP_TIMEOUT 100000
92 /*
93 * ACPI table definitions
94 *
95 * These data structures are laid over the table to parse the important values
96 * out of it.
97 */
98
99 extern const struct iommu_ops amd_iommu_ops;
100
101 /*
102 * structure describing one IOMMU in the ACPI table. Typically followed by one
103 * or more ivhd_entrys.
104 */
105 struct ivhd_header {
106 u8 type;
107 u8 flags;
108 u16 length;
109 u16 devid;
110 u16 cap_ptr;
111 u64 mmio_phys;
112 u16 pci_seg;
113 u16 info;
114 u32 efr_attr;
115
116 /* Following only valid on IVHD type 11h and 40h */
117 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
118 u64 res;
119 } __attribute__((packed));
120
121 /*
122 * A device entry describing which devices a specific IOMMU translates and
123 * which requestor ids they use.
124 */
125 struct ivhd_entry {
126 u8 type;
127 u16 devid;
128 u8 flags;
129 u32 ext;
130 u32 hidh;
131 u64 cid;
132 u8 uidf;
133 u8 uidl;
134 u8 uid;
135 } __attribute__((packed));
136
137 /*
138 * An AMD IOMMU memory definition structure. It defines things like exclusion
139 * ranges for devices and regions that should be unity mapped.
140 */
141 struct ivmd_header {
142 u8 type;
143 u8 flags;
144 u16 length;
145 u16 devid;
146 u16 aux;
147 u64 resv;
148 u64 range_start;
149 u64 range_length;
150 } __attribute__((packed));
151
152 bool amd_iommu_dump;
153 bool amd_iommu_irq_remap __read_mostly;
154
155 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
156
157 static bool amd_iommu_detected;
158 static bool __initdata amd_iommu_disabled;
159 static int amd_iommu_target_ivhd_type;
160
161 u16 amd_iommu_last_bdf; /* largest PCI device id we have
162 to handle */
163 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
164 we find in ACPI */
165 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
166
167 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
168 system */
169
170 /* Array to assign indices to IOMMUs*/
171 struct amd_iommu *amd_iommus[MAX_IOMMUS];
172
173 /* Number of IOMMUs present in the system */
174 static int amd_iommus_present;
175
176 /* IOMMUs have a non-present cache? */
177 bool amd_iommu_np_cache __read_mostly;
178 bool amd_iommu_iotlb_sup __read_mostly = true;
179
180 u32 amd_iommu_max_pasid __read_mostly = ~0;
181
182 bool amd_iommu_v2_present __read_mostly;
183 static bool amd_iommu_pc_present __read_mostly;
184
185 bool amd_iommu_force_isolation __read_mostly;
186
187 /*
188 * List of protection domains - used during resume
189 */
190 LIST_HEAD(amd_iommu_pd_list);
191 spinlock_t amd_iommu_pd_lock;
192
193 /*
194 * Pointer to the device table which is shared by all AMD IOMMUs
195 * it is indexed by the PCI device id or the HT unit id and contains
196 * information about the domain the device belongs to as well as the
197 * page table root pointer.
198 */
199 struct dev_table_entry *amd_iommu_dev_table;
200 /*
201 * Pointer to a device table which the content of old device table
202 * will be copied to. It's only be used in kdump kernel.
203 */
204 static struct dev_table_entry *old_dev_tbl_cpy;
205
206 /*
207 * The alias table is a driver specific data structure which contains the
208 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
209 * More than one device can share the same requestor id.
210 */
211 u16 *amd_iommu_alias_table;
212
213 /*
214 * The rlookup table is used to find the IOMMU which is responsible
215 * for a specific device. It is also indexed by the PCI device id.
216 */
217 struct amd_iommu **amd_iommu_rlookup_table;
218 EXPORT_SYMBOL(amd_iommu_rlookup_table);
219
220 /*
221 * This table is used to find the irq remapping table for a given device id
222 * quickly.
223 */
224 struct irq_remap_table **irq_lookup_table;
225
226 /*
227 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
228 * to know which ones are already in use.
229 */
230 unsigned long *amd_iommu_pd_alloc_bitmap;
231
232 static u32 dev_table_size; /* size of the device table */
233 static u32 alias_table_size; /* size of the alias table */
234 static u32 rlookup_table_size; /* size if the rlookup table */
235
236 enum iommu_init_state {
237 IOMMU_START_STATE,
238 IOMMU_IVRS_DETECTED,
239 IOMMU_ACPI_FINISHED,
240 IOMMU_ENABLED,
241 IOMMU_PCI_INIT,
242 IOMMU_INTERRUPTS_EN,
243 IOMMU_DMA_OPS,
244 IOMMU_INITIALIZED,
245 IOMMU_NOT_FOUND,
246 IOMMU_INIT_ERROR,
247 IOMMU_CMDLINE_DISABLED,
248 };
249
250 /* Early ioapic and hpet maps from kernel command line */
251 #define EARLY_MAP_SIZE 4
252 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
253 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
254 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
255
256 static int __initdata early_ioapic_map_size;
257 static int __initdata early_hpet_map_size;
258 static int __initdata early_acpihid_map_size;
259
260 static bool __initdata cmdline_maps;
261
262 static enum iommu_init_state init_state = IOMMU_START_STATE;
263
264 static int amd_iommu_enable_interrupts(void);
265 static int __init iommu_go_to_state(enum iommu_init_state state);
266 static void init_device_table_dma(void);
267
268 static bool amd_iommu_pre_enabled = true;
269
270 bool translation_pre_enabled(struct amd_iommu *iommu)
271 {
272 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED);
273 }
274 EXPORT_SYMBOL(translation_pre_enabled);
275
276 static void clear_translation_pre_enabled(struct amd_iommu *iommu)
277 {
278 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
279 }
280
281 static void init_translation_status(struct amd_iommu *iommu)
282 {
283 u32 ctrl;
284
285 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
286 if (ctrl & (1<<CONTROL_IOMMU_EN))
287 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
288 }
289
290 static inline void update_last_devid(u16 devid)
291 {
292 if (devid > amd_iommu_last_bdf)
293 amd_iommu_last_bdf = devid;
294 }
295
296 static inline unsigned long tbl_size(int entry_size)
297 {
298 unsigned shift = PAGE_SHIFT +
299 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
300
301 return 1UL << shift;
302 }
303
304 int amd_iommu_get_num_iommus(void)
305 {
306 return amd_iommus_present;
307 }
308
309 /* Access to l1 and l2 indexed register spaces */
310
311 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
312 {
313 u32 val;
314
315 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
316 pci_read_config_dword(iommu->dev, 0xfc, &val);
317 return val;
318 }
319
320 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
321 {
322 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
323 pci_write_config_dword(iommu->dev, 0xfc, val);
324 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
325 }
326
327 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
328 {
329 u32 val;
330
331 pci_write_config_dword(iommu->dev, 0xf0, address);
332 pci_read_config_dword(iommu->dev, 0xf4, &val);
333 return val;
334 }
335
336 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
337 {
338 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
339 pci_write_config_dword(iommu->dev, 0xf4, val);
340 }
341
342 /****************************************************************************
343 *
344 * AMD IOMMU MMIO register space handling functions
345 *
346 * These functions are used to program the IOMMU device registers in
347 * MMIO space required for that driver.
348 *
349 ****************************************************************************/
350
351 /*
352 * This function set the exclusion range in the IOMMU. DMA accesses to the
353 * exclusion range are passed through untranslated
354 */
355 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
356 {
357 u64 start = iommu->exclusion_start & PAGE_MASK;
358 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
359 u64 entry;
360
361 if (!iommu->exclusion_start)
362 return;
363
364 entry = start | MMIO_EXCL_ENABLE_MASK;
365 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
366 &entry, sizeof(entry));
367
368 entry = limit;
369 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
370 &entry, sizeof(entry));
371 }
372
373 /* Programs the physical address of the device table into the IOMMU hardware */
374 static void iommu_set_device_table(struct amd_iommu *iommu)
375 {
376 u64 entry;
377
378 BUG_ON(iommu->mmio_base == NULL);
379
380 entry = iommu_virt_to_phys(amd_iommu_dev_table);
381 entry |= (dev_table_size >> 12) - 1;
382 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
383 &entry, sizeof(entry));
384 }
385
386 /* Generic functions to enable/disable certain features of the IOMMU. */
387 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
388 {
389 u32 ctrl;
390
391 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
392 ctrl |= (1 << bit);
393 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
394 }
395
396 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
397 {
398 u32 ctrl;
399
400 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
401 ctrl &= ~(1 << bit);
402 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
403 }
404
405 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
406 {
407 u32 ctrl;
408
409 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
410 ctrl &= ~CTRL_INV_TO_MASK;
411 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
412 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
413 }
414
415 /* Function to enable the hardware */
416 static void iommu_enable(struct amd_iommu *iommu)
417 {
418 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
419 }
420
421 static void iommu_disable(struct amd_iommu *iommu)
422 {
423 /* Disable command buffer */
424 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
425
426 /* Disable event logging and event interrupts */
427 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
428 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
429
430 /* Disable IOMMU GA_LOG */
431 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
432 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
433
434 /* Disable IOMMU hardware itself */
435 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
436 }
437
438 /*
439 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
440 * the system has one.
441 */
442 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
443 {
444 if (!request_mem_region(address, end, "amd_iommu")) {
445 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
446 address, end);
447 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
448 return NULL;
449 }
450
451 return (u8 __iomem *)ioremap_nocache(address, end);
452 }
453
454 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
455 {
456 if (iommu->mmio_base)
457 iounmap(iommu->mmio_base);
458 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
459 }
460
461 static inline u32 get_ivhd_header_size(struct ivhd_header *h)
462 {
463 u32 size = 0;
464
465 switch (h->type) {
466 case 0x10:
467 size = 24;
468 break;
469 case 0x11:
470 case 0x40:
471 size = 40;
472 break;
473 }
474 return size;
475 }
476
477 /****************************************************************************
478 *
479 * The functions below belong to the first pass of AMD IOMMU ACPI table
480 * parsing. In this pass we try to find out the highest device id this
481 * code has to handle. Upon this information the size of the shared data
482 * structures is determined later.
483 *
484 ****************************************************************************/
485
486 /*
487 * This function calculates the length of a given IVHD entry
488 */
489 static inline int ivhd_entry_length(u8 *ivhd)
490 {
491 u32 type = ((struct ivhd_entry *)ivhd)->type;
492
493 if (type < 0x80) {
494 return 0x04 << (*ivhd >> 6);
495 } else if (type == IVHD_DEV_ACPI_HID) {
496 /* For ACPI_HID, offset 21 is uid len */
497 return *((u8 *)ivhd + 21) + 22;
498 }
499 return 0;
500 }
501
502 /*
503 * After reading the highest device id from the IOMMU PCI capability header
504 * this function looks if there is a higher device id defined in the ACPI table
505 */
506 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
507 {
508 u8 *p = (void *)h, *end = (void *)h;
509 struct ivhd_entry *dev;
510
511 u32 ivhd_size = get_ivhd_header_size(h);
512
513 if (!ivhd_size) {
514 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
515 return -EINVAL;
516 }
517
518 p += ivhd_size;
519 end += h->length;
520
521 while (p < end) {
522 dev = (struct ivhd_entry *)p;
523 switch (dev->type) {
524 case IVHD_DEV_ALL:
525 /* Use maximum BDF value for DEV_ALL */
526 update_last_devid(0xffff);
527 break;
528 case IVHD_DEV_SELECT:
529 case IVHD_DEV_RANGE_END:
530 case IVHD_DEV_ALIAS:
531 case IVHD_DEV_EXT_SELECT:
532 /* all the above subfield types refer to device ids */
533 update_last_devid(dev->devid);
534 break;
535 default:
536 break;
537 }
538 p += ivhd_entry_length(p);
539 }
540
541 WARN_ON(p != end);
542
543 return 0;
544 }
545
546 static int __init check_ivrs_checksum(struct acpi_table_header *table)
547 {
548 int i;
549 u8 checksum = 0, *p = (u8 *)table;
550
551 for (i = 0; i < table->length; ++i)
552 checksum += p[i];
553 if (checksum != 0) {
554 /* ACPI table corrupt */
555 pr_err(FW_BUG "AMD-Vi: IVRS invalid checksum\n");
556 return -ENODEV;
557 }
558
559 return 0;
560 }
561
562 /*
563 * Iterate over all IVHD entries in the ACPI table and find the highest device
564 * id which we need to handle. This is the first of three functions which parse
565 * the ACPI table. So we check the checksum here.
566 */
567 static int __init find_last_devid_acpi(struct acpi_table_header *table)
568 {
569 u8 *p = (u8 *)table, *end = (u8 *)table;
570 struct ivhd_header *h;
571
572 p += IVRS_HEADER_LENGTH;
573
574 end += table->length;
575 while (p < end) {
576 h = (struct ivhd_header *)p;
577 if (h->type == amd_iommu_target_ivhd_type) {
578 int ret = find_last_devid_from_ivhd(h);
579
580 if (ret)
581 return ret;
582 }
583 p += h->length;
584 }
585 WARN_ON(p != end);
586
587 return 0;
588 }
589
590 /****************************************************************************
591 *
592 * The following functions belong to the code path which parses the ACPI table
593 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
594 * data structures, initialize the device/alias/rlookup table and also
595 * basically initialize the hardware.
596 *
597 ****************************************************************************/
598
599 /*
600 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
601 * write commands to that buffer later and the IOMMU will execute them
602 * asynchronously
603 */
604 static int __init alloc_command_buffer(struct amd_iommu *iommu)
605 {
606 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
607 get_order(CMD_BUFFER_SIZE));
608
609 return iommu->cmd_buf ? 0 : -ENOMEM;
610 }
611
612 /*
613 * This function resets the command buffer if the IOMMU stopped fetching
614 * commands from it.
615 */
616 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
617 {
618 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
619
620 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
621 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
622 iommu->cmd_buf_head = 0;
623 iommu->cmd_buf_tail = 0;
624
625 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
626 }
627
628 /*
629 * This function writes the command buffer address to the hardware and
630 * enables it.
631 */
632 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
633 {
634 u64 entry;
635
636 BUG_ON(iommu->cmd_buf == NULL);
637
638 entry = iommu_virt_to_phys(iommu->cmd_buf);
639 entry |= MMIO_CMD_SIZE_512;
640
641 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
642 &entry, sizeof(entry));
643
644 amd_iommu_reset_cmd_buffer(iommu);
645 }
646
647 /*
648 * This function disables the command buffer
649 */
650 static void iommu_disable_command_buffer(struct amd_iommu *iommu)
651 {
652 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
653 }
654
655 static void __init free_command_buffer(struct amd_iommu *iommu)
656 {
657 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
658 }
659
660 /* allocates the memory where the IOMMU will log its events to */
661 static int __init alloc_event_buffer(struct amd_iommu *iommu)
662 {
663 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
664 get_order(EVT_BUFFER_SIZE));
665
666 return iommu->evt_buf ? 0 : -ENOMEM;
667 }
668
669 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
670 {
671 u64 entry;
672
673 BUG_ON(iommu->evt_buf == NULL);
674
675 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
676
677 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
678 &entry, sizeof(entry));
679
680 /* set head and tail to zero manually */
681 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
682 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
683
684 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
685 }
686
687 /*
688 * This function disables the event log buffer
689 */
690 static void iommu_disable_event_buffer(struct amd_iommu *iommu)
691 {
692 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
693 }
694
695 static void __init free_event_buffer(struct amd_iommu *iommu)
696 {
697 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
698 }
699
700 /* allocates the memory where the IOMMU will log its events to */
701 static int __init alloc_ppr_log(struct amd_iommu *iommu)
702 {
703 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
704 get_order(PPR_LOG_SIZE));
705
706 return iommu->ppr_log ? 0 : -ENOMEM;
707 }
708
709 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
710 {
711 u64 entry;
712
713 if (iommu->ppr_log == NULL)
714 return;
715
716 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
717
718 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
719 &entry, sizeof(entry));
720
721 /* set head and tail to zero manually */
722 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
723 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
724
725 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
726 iommu_feature_enable(iommu, CONTROL_PPR_EN);
727 }
728
729 static void __init free_ppr_log(struct amd_iommu *iommu)
730 {
731 if (iommu->ppr_log == NULL)
732 return;
733
734 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
735 }
736
737 static void free_ga_log(struct amd_iommu *iommu)
738 {
739 #ifdef CONFIG_IRQ_REMAP
740 if (iommu->ga_log)
741 free_pages((unsigned long)iommu->ga_log,
742 get_order(GA_LOG_SIZE));
743 if (iommu->ga_log_tail)
744 free_pages((unsigned long)iommu->ga_log_tail,
745 get_order(8));
746 #endif
747 }
748
749 static int iommu_ga_log_enable(struct amd_iommu *iommu)
750 {
751 #ifdef CONFIG_IRQ_REMAP
752 u32 status, i;
753
754 if (!iommu->ga_log)
755 return -EINVAL;
756
757 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
758
759 /* Check if already running */
760 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
761 return 0;
762
763 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
764 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
765
766 for (i = 0; i < LOOP_TIMEOUT; ++i) {
767 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
768 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
769 break;
770 }
771
772 if (i >= LOOP_TIMEOUT)
773 return -EINVAL;
774 #endif /* CONFIG_IRQ_REMAP */
775 return 0;
776 }
777
778 #ifdef CONFIG_IRQ_REMAP
779 static int iommu_init_ga_log(struct amd_iommu *iommu)
780 {
781 u64 entry;
782
783 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
784 return 0;
785
786 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
787 get_order(GA_LOG_SIZE));
788 if (!iommu->ga_log)
789 goto err_out;
790
791 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
792 get_order(8));
793 if (!iommu->ga_log_tail)
794 goto err_out;
795
796 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
797 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
798 &entry, sizeof(entry));
799 entry = (iommu_virt_to_phys(iommu->ga_log_tail) &
800 (BIT_ULL(52)-1)) & ~7ULL;
801 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
802 &entry, sizeof(entry));
803 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
804 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
805
806 return 0;
807 err_out:
808 free_ga_log(iommu);
809 return -EINVAL;
810 }
811 #endif /* CONFIG_IRQ_REMAP */
812
813 static int iommu_init_ga(struct amd_iommu *iommu)
814 {
815 int ret = 0;
816
817 #ifdef CONFIG_IRQ_REMAP
818 /* Note: We have already checked GASup from IVRS table.
819 * Now, we need to make sure that GAMSup is set.
820 */
821 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
822 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
823 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
824
825 ret = iommu_init_ga_log(iommu);
826 #endif /* CONFIG_IRQ_REMAP */
827
828 return ret;
829 }
830
831 static void iommu_enable_gt(struct amd_iommu *iommu)
832 {
833 if (!iommu_feature(iommu, FEATURE_GT))
834 return;
835
836 iommu_feature_enable(iommu, CONTROL_GT_EN);
837 }
838
839 /* sets a specific bit in the device table entry. */
840 static void set_dev_entry_bit(u16 devid, u8 bit)
841 {
842 int i = (bit >> 6) & 0x03;
843 int _bit = bit & 0x3f;
844
845 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
846 }
847
848 static int get_dev_entry_bit(u16 devid, u8 bit)
849 {
850 int i = (bit >> 6) & 0x03;
851 int _bit = bit & 0x3f;
852
853 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
854 }
855
856
857 static bool copy_device_table(void)
858 {
859 u64 int_ctl, int_tab_len, entry = 0, last_entry = 0;
860 struct dev_table_entry *old_devtb = NULL;
861 u32 lo, hi, devid, old_devtb_size;
862 phys_addr_t old_devtb_phys;
863 struct amd_iommu *iommu;
864 u16 dom_id, dte_v, irq_v;
865 gfp_t gfp_flag;
866 u64 tmp;
867
868 if (!amd_iommu_pre_enabled)
869 return false;
870
871 pr_warn("Translation is already enabled - trying to copy translation structures\n");
872 for_each_iommu(iommu) {
873 /* All IOMMUs should use the same device table with the same size */
874 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET);
875 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4);
876 entry = (((u64) hi) << 32) + lo;
877 if (last_entry && last_entry != entry) {
878 pr_err("IOMMU:%d should use the same dev table as others!\n",
879 iommu->index);
880 return false;
881 }
882 last_entry = entry;
883
884 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12;
885 if (old_devtb_size != dev_table_size) {
886 pr_err("The device table size of IOMMU:%d is not expected!\n",
887 iommu->index);
888 return false;
889 }
890 }
891
892 old_devtb_phys = entry & PAGE_MASK;
893 if (old_devtb_phys >= 0x100000000ULL) {
894 pr_err("The address of old device table is above 4G, not trustworthy!\n");
895 return false;
896 }
897 old_devtb = memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB);
898 if (!old_devtb)
899 return false;
900
901 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32;
902 old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag,
903 get_order(dev_table_size));
904 if (old_dev_tbl_cpy == NULL) {
905 pr_err("Failed to allocate memory for copying old device table!\n");
906 return false;
907 }
908
909 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
910 old_dev_tbl_cpy[devid] = old_devtb[devid];
911 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK;
912 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V;
913
914 if (dte_v && dom_id) {
915 old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0];
916 old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1];
917 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap);
918 /* If gcr3 table existed, mask it out */
919 if (old_devtb[devid].data[0] & DTE_FLAG_GV) {
920 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
921 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
922 old_dev_tbl_cpy[devid].data[1] &= ~tmp;
923 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A;
924 tmp |= DTE_FLAG_GV;
925 old_dev_tbl_cpy[devid].data[0] &= ~tmp;
926 }
927 }
928
929 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE;
930 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK;
931 int_tab_len = old_devtb[devid].data[2] & DTE_IRQ_TABLE_LEN_MASK;
932 if (irq_v && (int_ctl || int_tab_len)) {
933 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) ||
934 (int_tab_len != DTE_IRQ_TABLE_LEN)) {
935 pr_err("Wrong old irq remapping flag: %#x\n", devid);
936 return false;
937 }
938
939 old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2];
940 }
941 }
942 memunmap(old_devtb);
943
944 return true;
945 }
946
947 void amd_iommu_apply_erratum_63(u16 devid)
948 {
949 int sysmgt;
950
951 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
952 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
953
954 if (sysmgt == 0x01)
955 set_dev_entry_bit(devid, DEV_ENTRY_IW);
956 }
957
958 /* Writes the specific IOMMU for a device into the rlookup table */
959 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
960 {
961 amd_iommu_rlookup_table[devid] = iommu;
962 }
963
964 /*
965 * This function takes the device specific flags read from the ACPI
966 * table and sets up the device table entry with that information
967 */
968 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
969 u16 devid, u32 flags, u32 ext_flags)
970 {
971 if (flags & ACPI_DEVFLAG_INITPASS)
972 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
973 if (flags & ACPI_DEVFLAG_EXTINT)
974 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
975 if (flags & ACPI_DEVFLAG_NMI)
976 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
977 if (flags & ACPI_DEVFLAG_SYSMGT1)
978 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
979 if (flags & ACPI_DEVFLAG_SYSMGT2)
980 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
981 if (flags & ACPI_DEVFLAG_LINT0)
982 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
983 if (flags & ACPI_DEVFLAG_LINT1)
984 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
985
986 amd_iommu_apply_erratum_63(devid);
987
988 set_iommu_for_device(iommu, devid);
989 }
990
991 static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
992 {
993 struct devid_map *entry;
994 struct list_head *list;
995
996 if (type == IVHD_SPECIAL_IOAPIC)
997 list = &ioapic_map;
998 else if (type == IVHD_SPECIAL_HPET)
999 list = &hpet_map;
1000 else
1001 return -EINVAL;
1002
1003 list_for_each_entry(entry, list, list) {
1004 if (!(entry->id == id && entry->cmd_line))
1005 continue;
1006
1007 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
1008 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
1009
1010 *devid = entry->devid;
1011
1012 return 0;
1013 }
1014
1015 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1016 if (!entry)
1017 return -ENOMEM;
1018
1019 entry->id = id;
1020 entry->devid = *devid;
1021 entry->cmd_line = cmd_line;
1022
1023 list_add_tail(&entry->list, list);
1024
1025 return 0;
1026 }
1027
1028 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
1029 bool cmd_line)
1030 {
1031 struct acpihid_map_entry *entry;
1032 struct list_head *list = &acpihid_map;
1033
1034 list_for_each_entry(entry, list, list) {
1035 if (strcmp(entry->hid, hid) ||
1036 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
1037 !entry->cmd_line)
1038 continue;
1039
1040 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
1041 hid, uid);
1042 *devid = entry->devid;
1043 return 0;
1044 }
1045
1046 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1047 if (!entry)
1048 return -ENOMEM;
1049
1050 memcpy(entry->uid, uid, strlen(uid));
1051 memcpy(entry->hid, hid, strlen(hid));
1052 entry->devid = *devid;
1053 entry->cmd_line = cmd_line;
1054 entry->root_devid = (entry->devid & (~0x7));
1055
1056 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
1057 entry->cmd_line ? "cmd" : "ivrs",
1058 entry->hid, entry->uid, entry->root_devid);
1059
1060 list_add_tail(&entry->list, list);
1061 return 0;
1062 }
1063
1064 static int __init add_early_maps(void)
1065 {
1066 int i, ret;
1067
1068 for (i = 0; i < early_ioapic_map_size; ++i) {
1069 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
1070 early_ioapic_map[i].id,
1071 &early_ioapic_map[i].devid,
1072 early_ioapic_map[i].cmd_line);
1073 if (ret)
1074 return ret;
1075 }
1076
1077 for (i = 0; i < early_hpet_map_size; ++i) {
1078 ret = add_special_device(IVHD_SPECIAL_HPET,
1079 early_hpet_map[i].id,
1080 &early_hpet_map[i].devid,
1081 early_hpet_map[i].cmd_line);
1082 if (ret)
1083 return ret;
1084 }
1085
1086 for (i = 0; i < early_acpihid_map_size; ++i) {
1087 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
1088 early_acpihid_map[i].uid,
1089 &early_acpihid_map[i].devid,
1090 early_acpihid_map[i].cmd_line);
1091 if (ret)
1092 return ret;
1093 }
1094
1095 return 0;
1096 }
1097
1098 /*
1099 * Reads the device exclusion range from ACPI and initializes the IOMMU with
1100 * it
1101 */
1102 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
1103 {
1104 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1105
1106 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
1107 return;
1108
1109 if (iommu) {
1110 /*
1111 * We only can configure exclusion ranges per IOMMU, not
1112 * per device. But we can enable the exclusion range per
1113 * device. This is done here
1114 */
1115 set_dev_entry_bit(devid, DEV_ENTRY_EX);
1116 iommu->exclusion_start = m->range_start;
1117 iommu->exclusion_length = m->range_length;
1118 }
1119 }
1120
1121 /*
1122 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1123 * initializes the hardware and our data structures with it.
1124 */
1125 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
1126 struct ivhd_header *h)
1127 {
1128 u8 *p = (u8 *)h;
1129 u8 *end = p, flags = 0;
1130 u16 devid = 0, devid_start = 0, devid_to = 0;
1131 u32 dev_i, ext_flags = 0;
1132 bool alias = false;
1133 struct ivhd_entry *e;
1134 u32 ivhd_size;
1135 int ret;
1136
1137
1138 ret = add_early_maps();
1139 if (ret)
1140 return ret;
1141
1142 /*
1143 * First save the recommended feature enable bits from ACPI
1144 */
1145 iommu->acpi_flags = h->flags;
1146
1147 /*
1148 * Done. Now parse the device entries
1149 */
1150 ivhd_size = get_ivhd_header_size(h);
1151 if (!ivhd_size) {
1152 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
1153 return -EINVAL;
1154 }
1155
1156 p += ivhd_size;
1157
1158 end += h->length;
1159
1160
1161 while (p < end) {
1162 e = (struct ivhd_entry *)p;
1163 switch (e->type) {
1164 case IVHD_DEV_ALL:
1165
1166 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1167
1168 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1169 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1170 break;
1171 case IVHD_DEV_SELECT:
1172
1173 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1174 "flags: %02x\n",
1175 PCI_BUS_NUM(e->devid),
1176 PCI_SLOT(e->devid),
1177 PCI_FUNC(e->devid),
1178 e->flags);
1179
1180 devid = e->devid;
1181 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1182 break;
1183 case IVHD_DEV_SELECT_RANGE_START:
1184
1185 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1186 "devid: %02x:%02x.%x flags: %02x\n",
1187 PCI_BUS_NUM(e->devid),
1188 PCI_SLOT(e->devid),
1189 PCI_FUNC(e->devid),
1190 e->flags);
1191
1192 devid_start = e->devid;
1193 flags = e->flags;
1194 ext_flags = 0;
1195 alias = false;
1196 break;
1197 case IVHD_DEV_ALIAS:
1198
1199 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1200 "flags: %02x devid_to: %02x:%02x.%x\n",
1201 PCI_BUS_NUM(e->devid),
1202 PCI_SLOT(e->devid),
1203 PCI_FUNC(e->devid),
1204 e->flags,
1205 PCI_BUS_NUM(e->ext >> 8),
1206 PCI_SLOT(e->ext >> 8),
1207 PCI_FUNC(e->ext >> 8));
1208
1209 devid = e->devid;
1210 devid_to = e->ext >> 8;
1211 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1212 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1213 amd_iommu_alias_table[devid] = devid_to;
1214 break;
1215 case IVHD_DEV_ALIAS_RANGE:
1216
1217 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1218 "devid: %02x:%02x.%x flags: %02x "
1219 "devid_to: %02x:%02x.%x\n",
1220 PCI_BUS_NUM(e->devid),
1221 PCI_SLOT(e->devid),
1222 PCI_FUNC(e->devid),
1223 e->flags,
1224 PCI_BUS_NUM(e->ext >> 8),
1225 PCI_SLOT(e->ext >> 8),
1226 PCI_FUNC(e->ext >> 8));
1227
1228 devid_start = e->devid;
1229 flags = e->flags;
1230 devid_to = e->ext >> 8;
1231 ext_flags = 0;
1232 alias = true;
1233 break;
1234 case IVHD_DEV_EXT_SELECT:
1235
1236 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1237 "flags: %02x ext: %08x\n",
1238 PCI_BUS_NUM(e->devid),
1239 PCI_SLOT(e->devid),
1240 PCI_FUNC(e->devid),
1241 e->flags, e->ext);
1242
1243 devid = e->devid;
1244 set_dev_entry_from_acpi(iommu, devid, e->flags,
1245 e->ext);
1246 break;
1247 case IVHD_DEV_EXT_SELECT_RANGE:
1248
1249 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1250 "%02x:%02x.%x flags: %02x ext: %08x\n",
1251 PCI_BUS_NUM(e->devid),
1252 PCI_SLOT(e->devid),
1253 PCI_FUNC(e->devid),
1254 e->flags, e->ext);
1255
1256 devid_start = e->devid;
1257 flags = e->flags;
1258 ext_flags = e->ext;
1259 alias = false;
1260 break;
1261 case IVHD_DEV_RANGE_END:
1262
1263 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1264 PCI_BUS_NUM(e->devid),
1265 PCI_SLOT(e->devid),
1266 PCI_FUNC(e->devid));
1267
1268 devid = e->devid;
1269 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1270 if (alias) {
1271 amd_iommu_alias_table[dev_i] = devid_to;
1272 set_dev_entry_from_acpi(iommu,
1273 devid_to, flags, ext_flags);
1274 }
1275 set_dev_entry_from_acpi(iommu, dev_i,
1276 flags, ext_flags);
1277 }
1278 break;
1279 case IVHD_DEV_SPECIAL: {
1280 u8 handle, type;
1281 const char *var;
1282 u16 devid;
1283 int ret;
1284
1285 handle = e->ext & 0xff;
1286 devid = (e->ext >> 8) & 0xffff;
1287 type = (e->ext >> 24) & 0xff;
1288
1289 if (type == IVHD_SPECIAL_IOAPIC)
1290 var = "IOAPIC";
1291 else if (type == IVHD_SPECIAL_HPET)
1292 var = "HPET";
1293 else
1294 var = "UNKNOWN";
1295
1296 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1297 var, (int)handle,
1298 PCI_BUS_NUM(devid),
1299 PCI_SLOT(devid),
1300 PCI_FUNC(devid));
1301
1302 ret = add_special_device(type, handle, &devid, false);
1303 if (ret)
1304 return ret;
1305
1306 /*
1307 * add_special_device might update the devid in case a
1308 * command-line override is present. So call
1309 * set_dev_entry_from_acpi after add_special_device.
1310 */
1311 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1312
1313 break;
1314 }
1315 case IVHD_DEV_ACPI_HID: {
1316 u16 devid;
1317 u8 hid[ACPIHID_HID_LEN] = {0};
1318 u8 uid[ACPIHID_UID_LEN] = {0};
1319 int ret;
1320
1321 if (h->type != 0x40) {
1322 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1323 e->type);
1324 break;
1325 }
1326
1327 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1328 hid[ACPIHID_HID_LEN - 1] = '\0';
1329
1330 if (!(*hid)) {
1331 pr_err(FW_BUG "Invalid HID.\n");
1332 break;
1333 }
1334
1335 switch (e->uidf) {
1336 case UID_NOT_PRESENT:
1337
1338 if (e->uidl != 0)
1339 pr_warn(FW_BUG "Invalid UID length.\n");
1340
1341 break;
1342 case UID_IS_INTEGER:
1343
1344 sprintf(uid, "%d", e->uid);
1345
1346 break;
1347 case UID_IS_CHARACTER:
1348
1349 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1350 uid[ACPIHID_UID_LEN - 1] = '\0';
1351
1352 break;
1353 default:
1354 break;
1355 }
1356
1357 devid = e->devid;
1358 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1359 hid, uid,
1360 PCI_BUS_NUM(devid),
1361 PCI_SLOT(devid),
1362 PCI_FUNC(devid));
1363
1364 flags = e->flags;
1365
1366 ret = add_acpi_hid_device(hid, uid, &devid, false);
1367 if (ret)
1368 return ret;
1369
1370 /*
1371 * add_special_device might update the devid in case a
1372 * command-line override is present. So call
1373 * set_dev_entry_from_acpi after add_special_device.
1374 */
1375 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1376
1377 break;
1378 }
1379 default:
1380 break;
1381 }
1382
1383 p += ivhd_entry_length(p);
1384 }
1385
1386 return 0;
1387 }
1388
1389 static void __init free_iommu_one(struct amd_iommu *iommu)
1390 {
1391 free_command_buffer(iommu);
1392 free_event_buffer(iommu);
1393 free_ppr_log(iommu);
1394 free_ga_log(iommu);
1395 iommu_unmap_mmio_space(iommu);
1396 }
1397
1398 static void __init free_iommu_all(void)
1399 {
1400 struct amd_iommu *iommu, *next;
1401
1402 for_each_iommu_safe(iommu, next) {
1403 list_del(&iommu->list);
1404 free_iommu_one(iommu);
1405 kfree(iommu);
1406 }
1407 }
1408
1409 /*
1410 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1411 * Workaround:
1412 * BIOS should disable L2B micellaneous clock gating by setting
1413 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1414 */
1415 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1416 {
1417 u32 value;
1418
1419 if ((boot_cpu_data.x86 != 0x15) ||
1420 (boot_cpu_data.x86_model < 0x10) ||
1421 (boot_cpu_data.x86_model > 0x1f))
1422 return;
1423
1424 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1425 pci_read_config_dword(iommu->dev, 0xf4, &value);
1426
1427 if (value & BIT(2))
1428 return;
1429
1430 /* Select NB indirect register 0x90 and enable writing */
1431 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1432
1433 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1434 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1435 dev_name(&iommu->dev->dev));
1436
1437 /* Clear the enable writing bit */
1438 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1439 }
1440
1441 /*
1442 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1443 * Workaround:
1444 * BIOS should enable ATS write permission check by setting
1445 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1446 */
1447 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1448 {
1449 u32 value;
1450
1451 if ((boot_cpu_data.x86 != 0x15) ||
1452 (boot_cpu_data.x86_model < 0x30) ||
1453 (boot_cpu_data.x86_model > 0x3f))
1454 return;
1455
1456 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1457 value = iommu_read_l2(iommu, 0x47);
1458
1459 if (value & BIT(0))
1460 return;
1461
1462 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1463 iommu_write_l2(iommu, 0x47, value | BIT(0));
1464
1465 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1466 dev_name(&iommu->dev->dev));
1467 }
1468
1469 /*
1470 * This function clues the initialization function for one IOMMU
1471 * together and also allocates the command buffer and programs the
1472 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1473 */
1474 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1475 {
1476 int ret;
1477
1478 spin_lock_init(&iommu->lock);
1479
1480 /* Add IOMMU to internal data structures */
1481 list_add_tail(&iommu->list, &amd_iommu_list);
1482 iommu->index = amd_iommus_present++;
1483
1484 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1485 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1486 return -ENOSYS;
1487 }
1488
1489 /* Index is fine - add IOMMU to the array */
1490 amd_iommus[iommu->index] = iommu;
1491
1492 /*
1493 * Copy data from ACPI table entry to the iommu struct
1494 */
1495 iommu->devid = h->devid;
1496 iommu->cap_ptr = h->cap_ptr;
1497 iommu->pci_seg = h->pci_seg;
1498 iommu->mmio_phys = h->mmio_phys;
1499
1500 switch (h->type) {
1501 case 0x10:
1502 /* Check if IVHD EFR contains proper max banks/counters */
1503 if ((h->efr_attr != 0) &&
1504 ((h->efr_attr & (0xF << 13)) != 0) &&
1505 ((h->efr_attr & (0x3F << 17)) != 0))
1506 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1507 else
1508 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1509 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1510 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1511 break;
1512 case 0x11:
1513 case 0x40:
1514 if (h->efr_reg & (1 << 9))
1515 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1516 else
1517 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1518 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1519 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1520 break;
1521 default:
1522 return -EINVAL;
1523 }
1524
1525 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1526 iommu->mmio_phys_end);
1527 if (!iommu->mmio_base)
1528 return -ENOMEM;
1529
1530 if (alloc_command_buffer(iommu))
1531 return -ENOMEM;
1532
1533 if (alloc_event_buffer(iommu))
1534 return -ENOMEM;
1535
1536 iommu->int_enabled = false;
1537
1538 init_translation_status(iommu);
1539 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) {
1540 iommu_disable(iommu);
1541 clear_translation_pre_enabled(iommu);
1542 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n",
1543 iommu->index);
1544 }
1545 if (amd_iommu_pre_enabled)
1546 amd_iommu_pre_enabled = translation_pre_enabled(iommu);
1547
1548 ret = init_iommu_from_acpi(iommu, h);
1549 if (ret)
1550 return ret;
1551
1552 ret = amd_iommu_create_irq_domain(iommu);
1553 if (ret)
1554 return ret;
1555
1556 /*
1557 * Make sure IOMMU is not considered to translate itself. The IVRS
1558 * table tells us so, but this is a lie!
1559 */
1560 amd_iommu_rlookup_table[iommu->devid] = NULL;
1561
1562 return 0;
1563 }
1564
1565 /**
1566 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1567 * @ivrs Pointer to the IVRS header
1568 *
1569 * This function search through all IVDB of the maximum supported IVHD
1570 */
1571 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1572 {
1573 u8 *base = (u8 *)ivrs;
1574 struct ivhd_header *ivhd = (struct ivhd_header *)
1575 (base + IVRS_HEADER_LENGTH);
1576 u8 last_type = ivhd->type;
1577 u16 devid = ivhd->devid;
1578
1579 while (((u8 *)ivhd - base < ivrs->length) &&
1580 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1581 u8 *p = (u8 *) ivhd;
1582
1583 if (ivhd->devid == devid)
1584 last_type = ivhd->type;
1585 ivhd = (struct ivhd_header *)(p + ivhd->length);
1586 }
1587
1588 return last_type;
1589 }
1590
1591 /*
1592 * Iterates over all IOMMU entries in the ACPI table, allocates the
1593 * IOMMU structure and initializes it with init_iommu_one()
1594 */
1595 static int __init init_iommu_all(struct acpi_table_header *table)
1596 {
1597 u8 *p = (u8 *)table, *end = (u8 *)table;
1598 struct ivhd_header *h;
1599 struct amd_iommu *iommu;
1600 int ret;
1601
1602 end += table->length;
1603 p += IVRS_HEADER_LENGTH;
1604
1605 while (p < end) {
1606 h = (struct ivhd_header *)p;
1607 if (*p == amd_iommu_target_ivhd_type) {
1608
1609 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1610 "seg: %d flags: %01x info %04x\n",
1611 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1612 PCI_FUNC(h->devid), h->cap_ptr,
1613 h->pci_seg, h->flags, h->info);
1614 DUMP_printk(" mmio-addr: %016llx\n",
1615 h->mmio_phys);
1616
1617 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1618 if (iommu == NULL)
1619 return -ENOMEM;
1620
1621 ret = init_iommu_one(iommu, h);
1622 if (ret)
1623 return ret;
1624 }
1625 p += h->length;
1626
1627 }
1628 WARN_ON(p != end);
1629
1630 return 0;
1631 }
1632
1633 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
1634 u8 fxn, u64 *value, bool is_write);
1635
1636 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1637 {
1638 u64 val = 0xabcd, val2 = 0;
1639
1640 if (!iommu_feature(iommu, FEATURE_PC))
1641 return;
1642
1643 amd_iommu_pc_present = true;
1644
1645 /* Check if the performance counters can be written to */
1646 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
1647 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
1648 (val != val2)) {
1649 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1650 amd_iommu_pc_present = false;
1651 return;
1652 }
1653
1654 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1655
1656 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1657 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1658 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1659 }
1660
1661 static ssize_t amd_iommu_show_cap(struct device *dev,
1662 struct device_attribute *attr,
1663 char *buf)
1664 {
1665 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1666 return sprintf(buf, "%x\n", iommu->cap);
1667 }
1668 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1669
1670 static ssize_t amd_iommu_show_features(struct device *dev,
1671 struct device_attribute *attr,
1672 char *buf)
1673 {
1674 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1675 return sprintf(buf, "%llx\n", iommu->features);
1676 }
1677 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1678
1679 static struct attribute *amd_iommu_attrs[] = {
1680 &dev_attr_cap.attr,
1681 &dev_attr_features.attr,
1682 NULL,
1683 };
1684
1685 static struct attribute_group amd_iommu_group = {
1686 .name = "amd-iommu",
1687 .attrs = amd_iommu_attrs,
1688 };
1689
1690 static const struct attribute_group *amd_iommu_groups[] = {
1691 &amd_iommu_group,
1692 NULL,
1693 };
1694
1695 static int iommu_init_pci(struct amd_iommu *iommu)
1696 {
1697 int cap_ptr = iommu->cap_ptr;
1698 u32 range, misc, low, high;
1699 int ret;
1700
1701 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1702 iommu->devid & 0xff);
1703 if (!iommu->dev)
1704 return -ENODEV;
1705
1706 /* Prevent binding other PCI device drivers to IOMMU devices */
1707 iommu->dev->match_driver = false;
1708
1709 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1710 &iommu->cap);
1711 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1712 &range);
1713 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1714 &misc);
1715
1716 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1717 amd_iommu_iotlb_sup = false;
1718
1719 /* read extended feature bits */
1720 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1721 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1722
1723 iommu->features = ((u64)high << 32) | low;
1724
1725 if (iommu_feature(iommu, FEATURE_GT)) {
1726 int glxval;
1727 u32 max_pasid;
1728 u64 pasmax;
1729
1730 pasmax = iommu->features & FEATURE_PASID_MASK;
1731 pasmax >>= FEATURE_PASID_SHIFT;
1732 max_pasid = (1 << (pasmax + 1)) - 1;
1733
1734 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1735
1736 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1737
1738 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1739 glxval >>= FEATURE_GLXVAL_SHIFT;
1740
1741 if (amd_iommu_max_glx_val == -1)
1742 amd_iommu_max_glx_val = glxval;
1743 else
1744 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1745 }
1746
1747 if (iommu_feature(iommu, FEATURE_GT) &&
1748 iommu_feature(iommu, FEATURE_PPR)) {
1749 iommu->is_iommu_v2 = true;
1750 amd_iommu_v2_present = true;
1751 }
1752
1753 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1754 return -ENOMEM;
1755
1756 ret = iommu_init_ga(iommu);
1757 if (ret)
1758 return ret;
1759
1760 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1761 amd_iommu_np_cache = true;
1762
1763 init_iommu_perf_ctr(iommu);
1764
1765 if (is_rd890_iommu(iommu->dev)) {
1766 int i, j;
1767
1768 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1769 PCI_DEVFN(0, 0));
1770
1771 /*
1772 * Some rd890 systems may not be fully reconfigured by the
1773 * BIOS, so it's necessary for us to store this information so
1774 * it can be reprogrammed on resume
1775 */
1776 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1777 &iommu->stored_addr_lo);
1778 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1779 &iommu->stored_addr_hi);
1780
1781 /* Low bit locks writes to configuration space */
1782 iommu->stored_addr_lo &= ~1;
1783
1784 for (i = 0; i < 6; i++)
1785 for (j = 0; j < 0x12; j++)
1786 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1787
1788 for (i = 0; i < 0x83; i++)
1789 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1790 }
1791
1792 amd_iommu_erratum_746_workaround(iommu);
1793 amd_iommu_ats_write_check_workaround(iommu);
1794
1795 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1796 amd_iommu_groups, "ivhd%d", iommu->index);
1797 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops);
1798 iommu_device_register(&iommu->iommu);
1799
1800 return pci_enable_device(iommu->dev);
1801 }
1802
1803 static void print_iommu_info(void)
1804 {
1805 static const char * const feat_str[] = {
1806 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1807 "IA", "GA", "HE", "PC"
1808 };
1809 struct amd_iommu *iommu;
1810
1811 for_each_iommu(iommu) {
1812 int i;
1813
1814 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1815 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1816
1817 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1818 pr_info("AMD-Vi: Extended features (%#llx):\n",
1819 iommu->features);
1820 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1821 if (iommu_feature(iommu, (1ULL << i)))
1822 pr_cont(" %s", feat_str[i]);
1823 }
1824
1825 if (iommu->features & FEATURE_GAM_VAPIC)
1826 pr_cont(" GA_vAPIC");
1827
1828 pr_cont("\n");
1829 }
1830 }
1831 if (irq_remapping_enabled) {
1832 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1833 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1834 pr_info("AMD-Vi: virtual APIC enabled\n");
1835 }
1836 }
1837
1838 static int __init amd_iommu_init_pci(void)
1839 {
1840 struct amd_iommu *iommu;
1841 int ret = 0;
1842
1843 for_each_iommu(iommu) {
1844 ret = iommu_init_pci(iommu);
1845 if (ret)
1846 break;
1847 }
1848
1849 /*
1850 * Order is important here to make sure any unity map requirements are
1851 * fulfilled. The unity mappings are created and written to the device
1852 * table during the amd_iommu_init_api() call.
1853 *
1854 * After that we call init_device_table_dma() to make sure any
1855 * uninitialized DTE will block DMA, and in the end we flush the caches
1856 * of all IOMMUs to make sure the changes to the device table are
1857 * active.
1858 */
1859 ret = amd_iommu_init_api();
1860
1861 init_device_table_dma();
1862
1863 for_each_iommu(iommu)
1864 iommu_flush_all_caches(iommu);
1865
1866 if (!ret)
1867 print_iommu_info();
1868
1869 return ret;
1870 }
1871
1872 /****************************************************************************
1873 *
1874 * The following functions initialize the MSI interrupts for all IOMMUs
1875 * in the system. It's a bit challenging because there could be multiple
1876 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1877 * pci_dev.
1878 *
1879 ****************************************************************************/
1880
1881 static int iommu_setup_msi(struct amd_iommu *iommu)
1882 {
1883 int r;
1884
1885 r = pci_enable_msi(iommu->dev);
1886 if (r)
1887 return r;
1888
1889 r = request_threaded_irq(iommu->dev->irq,
1890 amd_iommu_int_handler,
1891 amd_iommu_int_thread,
1892 0, "AMD-Vi",
1893 iommu);
1894
1895 if (r) {
1896 pci_disable_msi(iommu->dev);
1897 return r;
1898 }
1899
1900 iommu->int_enabled = true;
1901
1902 return 0;
1903 }
1904
1905 static int iommu_init_msi(struct amd_iommu *iommu)
1906 {
1907 int ret;
1908
1909 if (iommu->int_enabled)
1910 goto enable_faults;
1911
1912 if (iommu->dev->msi_cap)
1913 ret = iommu_setup_msi(iommu);
1914 else
1915 ret = -ENODEV;
1916
1917 if (ret)
1918 return ret;
1919
1920 enable_faults:
1921 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1922
1923 if (iommu->ppr_log != NULL)
1924 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1925
1926 iommu_ga_log_enable(iommu);
1927
1928 return 0;
1929 }
1930
1931 /****************************************************************************
1932 *
1933 * The next functions belong to the third pass of parsing the ACPI
1934 * table. In this last pass the memory mapping requirements are
1935 * gathered (like exclusion and unity mapping ranges).
1936 *
1937 ****************************************************************************/
1938
1939 static void __init free_unity_maps(void)
1940 {
1941 struct unity_map_entry *entry, *next;
1942
1943 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1944 list_del(&entry->list);
1945 kfree(entry);
1946 }
1947 }
1948
1949 /* called when we find an exclusion range definition in ACPI */
1950 static int __init init_exclusion_range(struct ivmd_header *m)
1951 {
1952 int i;
1953
1954 switch (m->type) {
1955 case ACPI_IVMD_TYPE:
1956 set_device_exclusion_range(m->devid, m);
1957 break;
1958 case ACPI_IVMD_TYPE_ALL:
1959 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1960 set_device_exclusion_range(i, m);
1961 break;
1962 case ACPI_IVMD_TYPE_RANGE:
1963 for (i = m->devid; i <= m->aux; ++i)
1964 set_device_exclusion_range(i, m);
1965 break;
1966 default:
1967 break;
1968 }
1969
1970 return 0;
1971 }
1972
1973 /* called for unity map ACPI definition */
1974 static int __init init_unity_map_range(struct ivmd_header *m)
1975 {
1976 struct unity_map_entry *e = NULL;
1977 char *s;
1978
1979 e = kzalloc(sizeof(*e), GFP_KERNEL);
1980 if (e == NULL)
1981 return -ENOMEM;
1982
1983 switch (m->type) {
1984 default:
1985 kfree(e);
1986 return 0;
1987 case ACPI_IVMD_TYPE:
1988 s = "IVMD_TYPEi\t\t\t";
1989 e->devid_start = e->devid_end = m->devid;
1990 break;
1991 case ACPI_IVMD_TYPE_ALL:
1992 s = "IVMD_TYPE_ALL\t\t";
1993 e->devid_start = 0;
1994 e->devid_end = amd_iommu_last_bdf;
1995 break;
1996 case ACPI_IVMD_TYPE_RANGE:
1997 s = "IVMD_TYPE_RANGE\t\t";
1998 e->devid_start = m->devid;
1999 e->devid_end = m->aux;
2000 break;
2001 }
2002 e->address_start = PAGE_ALIGN(m->range_start);
2003 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
2004 e->prot = m->flags >> 1;
2005
2006 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
2007 " range_start: %016llx range_end: %016llx flags: %x\n", s,
2008 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
2009 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
2010 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
2011 e->address_start, e->address_end, m->flags);
2012
2013 list_add_tail(&e->list, &amd_iommu_unity_map);
2014
2015 return 0;
2016 }
2017
2018 /* iterates over all memory definitions we find in the ACPI table */
2019 static int __init init_memory_definitions(struct acpi_table_header *table)
2020 {
2021 u8 *p = (u8 *)table, *end = (u8 *)table;
2022 struct ivmd_header *m;
2023
2024 end += table->length;
2025 p += IVRS_HEADER_LENGTH;
2026
2027 while (p < end) {
2028 m = (struct ivmd_header *)p;
2029 if (m->flags & IVMD_FLAG_EXCL_RANGE)
2030 init_exclusion_range(m);
2031 else if (m->flags & IVMD_FLAG_UNITY_MAP)
2032 init_unity_map_range(m);
2033
2034 p += m->length;
2035 }
2036
2037 return 0;
2038 }
2039
2040 /*
2041 * Init the device table to not allow DMA access for devices
2042 */
2043 static void init_device_table_dma(void)
2044 {
2045 u32 devid;
2046
2047 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2048 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
2049 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
2050 }
2051 }
2052
2053 static void __init uninit_device_table_dma(void)
2054 {
2055 u32 devid;
2056
2057 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2058 amd_iommu_dev_table[devid].data[0] = 0ULL;
2059 amd_iommu_dev_table[devid].data[1] = 0ULL;
2060 }
2061 }
2062
2063 static void init_device_table(void)
2064 {
2065 u32 devid;
2066
2067 if (!amd_iommu_irq_remap)
2068 return;
2069
2070 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2071 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
2072 }
2073
2074 static void iommu_init_flags(struct amd_iommu *iommu)
2075 {
2076 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
2077 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
2078 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
2079
2080 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
2081 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
2082 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
2083
2084 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
2085 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
2086 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
2087
2088 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
2089 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
2090 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
2091
2092 /*
2093 * make IOMMU memory accesses cache coherent
2094 */
2095 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
2096
2097 /* Set IOTLB invalidation timeout to 1s */
2098 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
2099 }
2100
2101 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
2102 {
2103 int i, j;
2104 u32 ioc_feature_control;
2105 struct pci_dev *pdev = iommu->root_pdev;
2106
2107 /* RD890 BIOSes may not have completely reconfigured the iommu */
2108 if (!is_rd890_iommu(iommu->dev) || !pdev)
2109 return;
2110
2111 /*
2112 * First, we need to ensure that the iommu is enabled. This is
2113 * controlled by a register in the northbridge
2114 */
2115
2116 /* Select Northbridge indirect register 0x75 and enable writing */
2117 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
2118 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
2119
2120 /* Enable the iommu */
2121 if (!(ioc_feature_control & 0x1))
2122 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
2123
2124 /* Restore the iommu BAR */
2125 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2126 iommu->stored_addr_lo);
2127 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
2128 iommu->stored_addr_hi);
2129
2130 /* Restore the l1 indirect regs for each of the 6 l1s */
2131 for (i = 0; i < 6; i++)
2132 for (j = 0; j < 0x12; j++)
2133 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
2134
2135 /* Restore the l2 indirect regs */
2136 for (i = 0; i < 0x83; i++)
2137 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
2138
2139 /* Lock PCI setup registers */
2140 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2141 iommu->stored_addr_lo | 1);
2142 }
2143
2144 static void iommu_enable_ga(struct amd_iommu *iommu)
2145 {
2146 #ifdef CONFIG_IRQ_REMAP
2147 switch (amd_iommu_guest_ir) {
2148 case AMD_IOMMU_GUEST_IR_VAPIC:
2149 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2150 /* Fall through */
2151 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2152 iommu_feature_enable(iommu, CONTROL_GA_EN);
2153 iommu->irte_ops = &irte_128_ops;
2154 break;
2155 default:
2156 iommu->irte_ops = &irte_32_ops;
2157 break;
2158 }
2159 #endif
2160 }
2161
2162 static void early_enable_iommu(struct amd_iommu *iommu)
2163 {
2164 iommu_disable(iommu);
2165 iommu_init_flags(iommu);
2166 iommu_set_device_table(iommu);
2167 iommu_enable_command_buffer(iommu);
2168 iommu_enable_event_buffer(iommu);
2169 iommu_set_exclusion_range(iommu);
2170 iommu_enable_ga(iommu);
2171 iommu_enable(iommu);
2172 iommu_flush_all_caches(iommu);
2173 }
2174
2175 /*
2176 * This function finally enables all IOMMUs found in the system after
2177 * they have been initialized.
2178 *
2179 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy
2180 * the old content of device table entries. Not this case or copy failed,
2181 * just continue as normal kernel does.
2182 */
2183 static void early_enable_iommus(void)
2184 {
2185 struct amd_iommu *iommu;
2186
2187
2188 if (!copy_device_table()) {
2189 /*
2190 * If come here because of failure in copying device table from old
2191 * kernel with all IOMMUs enabled, print error message and try to
2192 * free allocated old_dev_tbl_cpy.
2193 */
2194 if (amd_iommu_pre_enabled)
2195 pr_err("Failed to copy DEV table from previous kernel.\n");
2196 if (old_dev_tbl_cpy != NULL)
2197 free_pages((unsigned long)old_dev_tbl_cpy,
2198 get_order(dev_table_size));
2199
2200 for_each_iommu(iommu) {
2201 clear_translation_pre_enabled(iommu);
2202 early_enable_iommu(iommu);
2203 }
2204 } else {
2205 pr_info("Copied DEV table from previous kernel.\n");
2206 free_pages((unsigned long)amd_iommu_dev_table,
2207 get_order(dev_table_size));
2208 amd_iommu_dev_table = old_dev_tbl_cpy;
2209 for_each_iommu(iommu) {
2210 iommu_disable_command_buffer(iommu);
2211 iommu_disable_event_buffer(iommu);
2212 iommu_enable_command_buffer(iommu);
2213 iommu_enable_event_buffer(iommu);
2214 iommu_enable_ga(iommu);
2215 iommu_set_device_table(iommu);
2216 iommu_flush_all_caches(iommu);
2217 }
2218 }
2219
2220 #ifdef CONFIG_IRQ_REMAP
2221 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2222 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2223 #endif
2224 }
2225
2226 static void enable_iommus_v2(void)
2227 {
2228 struct amd_iommu *iommu;
2229
2230 for_each_iommu(iommu) {
2231 iommu_enable_ppr_log(iommu);
2232 iommu_enable_gt(iommu);
2233 }
2234 }
2235
2236 static void enable_iommus(void)
2237 {
2238 early_enable_iommus();
2239
2240 enable_iommus_v2();
2241 }
2242
2243 static void disable_iommus(void)
2244 {
2245 struct amd_iommu *iommu;
2246
2247 for_each_iommu(iommu)
2248 iommu_disable(iommu);
2249
2250 #ifdef CONFIG_IRQ_REMAP
2251 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2252 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2253 #endif
2254 }
2255
2256 /*
2257 * Suspend/Resume support
2258 * disable suspend until real resume implemented
2259 */
2260
2261 static void amd_iommu_resume(void)
2262 {
2263 struct amd_iommu *iommu;
2264
2265 for_each_iommu(iommu)
2266 iommu_apply_resume_quirks(iommu);
2267
2268 /* re-load the hardware */
2269 enable_iommus();
2270
2271 amd_iommu_enable_interrupts();
2272 }
2273
2274 static int amd_iommu_suspend(void)
2275 {
2276 /* disable IOMMUs to go out of the way for BIOS */
2277 disable_iommus();
2278
2279 return 0;
2280 }
2281
2282 static struct syscore_ops amd_iommu_syscore_ops = {
2283 .suspend = amd_iommu_suspend,
2284 .resume = amd_iommu_resume,
2285 };
2286
2287 static void __init free_iommu_resources(void)
2288 {
2289 kmemleak_free(irq_lookup_table);
2290 free_pages((unsigned long)irq_lookup_table,
2291 get_order(rlookup_table_size));
2292 irq_lookup_table = NULL;
2293
2294 kmem_cache_destroy(amd_iommu_irq_cache);
2295 amd_iommu_irq_cache = NULL;
2296
2297 free_pages((unsigned long)amd_iommu_rlookup_table,
2298 get_order(rlookup_table_size));
2299 amd_iommu_rlookup_table = NULL;
2300
2301 free_pages((unsigned long)amd_iommu_alias_table,
2302 get_order(alias_table_size));
2303 amd_iommu_alias_table = NULL;
2304
2305 free_pages((unsigned long)amd_iommu_dev_table,
2306 get_order(dev_table_size));
2307 amd_iommu_dev_table = NULL;
2308
2309 free_iommu_all();
2310
2311 #ifdef CONFIG_GART_IOMMU
2312 /*
2313 * We failed to initialize the AMD IOMMU - try fallback to GART
2314 * if possible.
2315 */
2316 gart_iommu_init();
2317
2318 #endif
2319 }
2320
2321 /* SB IOAPIC is always on this device in AMD systems */
2322 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2323
2324 static bool __init check_ioapic_information(void)
2325 {
2326 const char *fw_bug = FW_BUG;
2327 bool ret, has_sb_ioapic;
2328 int idx;
2329
2330 has_sb_ioapic = false;
2331 ret = false;
2332
2333 /*
2334 * If we have map overrides on the kernel command line the
2335 * messages in this function might not describe firmware bugs
2336 * anymore - so be careful
2337 */
2338 if (cmdline_maps)
2339 fw_bug = "";
2340
2341 for (idx = 0; idx < nr_ioapics; idx++) {
2342 int devid, id = mpc_ioapic_id(idx);
2343
2344 devid = get_ioapic_devid(id);
2345 if (devid < 0) {
2346 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
2347 fw_bug, id);
2348 ret = false;
2349 } else if (devid == IOAPIC_SB_DEVID) {
2350 has_sb_ioapic = true;
2351 ret = true;
2352 }
2353 }
2354
2355 if (!has_sb_ioapic) {
2356 /*
2357 * We expect the SB IOAPIC to be listed in the IVRS
2358 * table. The system timer is connected to the SB IOAPIC
2359 * and if we don't have it in the list the system will
2360 * panic at boot time. This situation usually happens
2361 * when the BIOS is buggy and provides us the wrong
2362 * device id for the IOAPIC in the system.
2363 */
2364 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
2365 }
2366
2367 if (!ret)
2368 pr_err("AMD-Vi: Disabling interrupt remapping\n");
2369
2370 return ret;
2371 }
2372
2373 static void __init free_dma_resources(void)
2374 {
2375 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2376 get_order(MAX_DOMAIN_ID/8));
2377 amd_iommu_pd_alloc_bitmap = NULL;
2378
2379 free_unity_maps();
2380 }
2381
2382 /*
2383 * This is the hardware init function for AMD IOMMU in the system.
2384 * This function is called either from amd_iommu_init or from the interrupt
2385 * remapping setup code.
2386 *
2387 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2388 * four times:
2389 *
2390 * 1 pass) Discover the most comprehensive IVHD type to use.
2391 *
2392 * 2 pass) Find the highest PCI device id the driver has to handle.
2393 * Upon this information the size of the data structures is
2394 * determined that needs to be allocated.
2395 *
2396 * 3 pass) Initialize the data structures just allocated with the
2397 * information in the ACPI table about available AMD IOMMUs
2398 * in the system. It also maps the PCI devices in the
2399 * system to specific IOMMUs
2400 *
2401 * 4 pass) After the basic data structures are allocated and
2402 * initialized we update them with information about memory
2403 * remapping requirements parsed out of the ACPI table in
2404 * this last pass.
2405 *
2406 * After everything is set up the IOMMUs are enabled and the necessary
2407 * hotplug and suspend notifiers are registered.
2408 */
2409 static int __init early_amd_iommu_init(void)
2410 {
2411 struct acpi_table_header *ivrs_base;
2412 acpi_status status;
2413 int i, remap_cache_sz, ret = 0;
2414
2415 if (!amd_iommu_detected)
2416 return -ENODEV;
2417
2418 status = acpi_get_table("IVRS", 0, &ivrs_base);
2419 if (status == AE_NOT_FOUND)
2420 return -ENODEV;
2421 else if (ACPI_FAILURE(status)) {
2422 const char *err = acpi_format_exception(status);
2423 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2424 return -EINVAL;
2425 }
2426
2427 /*
2428 * Validate checksum here so we don't need to do it when
2429 * we actually parse the table
2430 */
2431 ret = check_ivrs_checksum(ivrs_base);
2432 if (ret)
2433 goto out;
2434
2435 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2436 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2437
2438 /*
2439 * First parse ACPI tables to find the largest Bus/Dev/Func
2440 * we need to handle. Upon this information the shared data
2441 * structures for the IOMMUs in the system will be allocated
2442 */
2443 ret = find_last_devid_acpi(ivrs_base);
2444 if (ret)
2445 goto out;
2446
2447 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2448 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2449 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2450
2451 /* Device table - directly used by all IOMMUs */
2452 ret = -ENOMEM;
2453 amd_iommu_dev_table = (void *)__get_free_pages(
2454 GFP_KERNEL | __GFP_ZERO | GFP_DMA32,
2455 get_order(dev_table_size));
2456 if (amd_iommu_dev_table == NULL)
2457 goto out;
2458
2459 /*
2460 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2461 * IOMMU see for that device
2462 */
2463 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2464 get_order(alias_table_size));
2465 if (amd_iommu_alias_table == NULL)
2466 goto out;
2467
2468 /* IOMMU rlookup table - find the IOMMU for a specific device */
2469 amd_iommu_rlookup_table = (void *)__get_free_pages(
2470 GFP_KERNEL | __GFP_ZERO,
2471 get_order(rlookup_table_size));
2472 if (amd_iommu_rlookup_table == NULL)
2473 goto out;
2474
2475 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2476 GFP_KERNEL | __GFP_ZERO,
2477 get_order(MAX_DOMAIN_ID/8));
2478 if (amd_iommu_pd_alloc_bitmap == NULL)
2479 goto out;
2480
2481 /*
2482 * let all alias entries point to itself
2483 */
2484 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2485 amd_iommu_alias_table[i] = i;
2486
2487 /*
2488 * never allocate domain 0 because its used as the non-allocated and
2489 * error value placeholder
2490 */
2491 __set_bit(0, amd_iommu_pd_alloc_bitmap);
2492
2493 spin_lock_init(&amd_iommu_pd_lock);
2494
2495 /*
2496 * now the data structures are allocated and basically initialized
2497 * start the real acpi table scan
2498 */
2499 ret = init_iommu_all(ivrs_base);
2500 if (ret)
2501 goto out;
2502
2503 /* Disable any previously enabled IOMMUs */
2504 if (!is_kdump_kernel() || amd_iommu_disabled)
2505 disable_iommus();
2506
2507 if (amd_iommu_irq_remap)
2508 amd_iommu_irq_remap = check_ioapic_information();
2509
2510 if (amd_iommu_irq_remap) {
2511 /*
2512 * Interrupt remapping enabled, create kmem_cache for the
2513 * remapping tables.
2514 */
2515 ret = -ENOMEM;
2516 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2517 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2518 else
2519 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2520 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2521 remap_cache_sz,
2522 IRQ_TABLE_ALIGNMENT,
2523 0, NULL);
2524 if (!amd_iommu_irq_cache)
2525 goto out;
2526
2527 irq_lookup_table = (void *)__get_free_pages(
2528 GFP_KERNEL | __GFP_ZERO,
2529 get_order(rlookup_table_size));
2530 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2531 1, GFP_KERNEL);
2532 if (!irq_lookup_table)
2533 goto out;
2534 }
2535
2536 ret = init_memory_definitions(ivrs_base);
2537 if (ret)
2538 goto out;
2539
2540 /* init the device table */
2541 init_device_table();
2542
2543 out:
2544 /* Don't leak any ACPI memory */
2545 acpi_put_table(ivrs_base);
2546 ivrs_base = NULL;
2547
2548 return ret;
2549 }
2550
2551 static int amd_iommu_enable_interrupts(void)
2552 {
2553 struct amd_iommu *iommu;
2554 int ret = 0;
2555
2556 for_each_iommu(iommu) {
2557 ret = iommu_init_msi(iommu);
2558 if (ret)
2559 goto out;
2560 }
2561
2562 out:
2563 return ret;
2564 }
2565
2566 static bool detect_ivrs(void)
2567 {
2568 struct acpi_table_header *ivrs_base;
2569 acpi_status status;
2570
2571 status = acpi_get_table("IVRS", 0, &ivrs_base);
2572 if (status == AE_NOT_FOUND)
2573 return false;
2574 else if (ACPI_FAILURE(status)) {
2575 const char *err = acpi_format_exception(status);
2576 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2577 return false;
2578 }
2579
2580 acpi_put_table(ivrs_base);
2581
2582 /* Make sure ACS will be enabled during PCI probe */
2583 pci_request_acs();
2584
2585 return true;
2586 }
2587
2588 /****************************************************************************
2589 *
2590 * AMD IOMMU Initialization State Machine
2591 *
2592 ****************************************************************************/
2593
2594 static int __init state_next(void)
2595 {
2596 int ret = 0;
2597
2598 switch (init_state) {
2599 case IOMMU_START_STATE:
2600 if (!detect_ivrs()) {
2601 init_state = IOMMU_NOT_FOUND;
2602 ret = -ENODEV;
2603 } else {
2604 init_state = IOMMU_IVRS_DETECTED;
2605 }
2606 break;
2607 case IOMMU_IVRS_DETECTED:
2608 ret = early_amd_iommu_init();
2609 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2610 if (init_state == IOMMU_ACPI_FINISHED && amd_iommu_disabled) {
2611 pr_info("AMD-Vi: AMD IOMMU disabled on kernel command-line\n");
2612 free_dma_resources();
2613 free_iommu_resources();
2614 init_state = IOMMU_CMDLINE_DISABLED;
2615 ret = -EINVAL;
2616 }
2617 break;
2618 case IOMMU_ACPI_FINISHED:
2619 early_enable_iommus();
2620 x86_platform.iommu_shutdown = disable_iommus;
2621 init_state = IOMMU_ENABLED;
2622 break;
2623 case IOMMU_ENABLED:
2624 register_syscore_ops(&amd_iommu_syscore_ops);
2625 ret = amd_iommu_init_pci();
2626 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2627 enable_iommus_v2();
2628 break;
2629 case IOMMU_PCI_INIT:
2630 ret = amd_iommu_enable_interrupts();
2631 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2632 break;
2633 case IOMMU_INTERRUPTS_EN:
2634 ret = amd_iommu_init_dma_ops();
2635 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2636 break;
2637 case IOMMU_DMA_OPS:
2638 init_state = IOMMU_INITIALIZED;
2639 break;
2640 case IOMMU_INITIALIZED:
2641 /* Nothing to do */
2642 break;
2643 case IOMMU_NOT_FOUND:
2644 case IOMMU_INIT_ERROR:
2645 case IOMMU_CMDLINE_DISABLED:
2646 /* Error states => do nothing */
2647 ret = -EINVAL;
2648 break;
2649 default:
2650 /* Unknown state */
2651 BUG();
2652 }
2653
2654 return ret;
2655 }
2656
2657 static int __init iommu_go_to_state(enum iommu_init_state state)
2658 {
2659 int ret = -EINVAL;
2660
2661 while (init_state != state) {
2662 if (init_state == IOMMU_NOT_FOUND ||
2663 init_state == IOMMU_INIT_ERROR ||
2664 init_state == IOMMU_CMDLINE_DISABLED)
2665 break;
2666 ret = state_next();
2667 }
2668
2669 return ret;
2670 }
2671
2672 #ifdef CONFIG_IRQ_REMAP
2673 int __init amd_iommu_prepare(void)
2674 {
2675 int ret;
2676
2677 amd_iommu_irq_remap = true;
2678
2679 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2680 if (ret)
2681 return ret;
2682 return amd_iommu_irq_remap ? 0 : -ENODEV;
2683 }
2684
2685 int __init amd_iommu_enable(void)
2686 {
2687 int ret;
2688
2689 ret = iommu_go_to_state(IOMMU_ENABLED);
2690 if (ret)
2691 return ret;
2692
2693 irq_remapping_enabled = 1;
2694
2695 return 0;
2696 }
2697
2698 void amd_iommu_disable(void)
2699 {
2700 amd_iommu_suspend();
2701 }
2702
2703 int amd_iommu_reenable(int mode)
2704 {
2705 amd_iommu_resume();
2706
2707 return 0;
2708 }
2709
2710 int __init amd_iommu_enable_faulting(void)
2711 {
2712 /* We enable MSI later when PCI is initialized */
2713 return 0;
2714 }
2715 #endif
2716
2717 /*
2718 * This is the core init function for AMD IOMMU hardware in the system.
2719 * This function is called from the generic x86 DMA layer initialization
2720 * code.
2721 */
2722 static int __init amd_iommu_init(void)
2723 {
2724 int ret;
2725
2726 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2727 if (ret) {
2728 free_dma_resources();
2729 if (!irq_remapping_enabled) {
2730 disable_iommus();
2731 free_iommu_resources();
2732 } else {
2733 struct amd_iommu *iommu;
2734
2735 uninit_device_table_dma();
2736 for_each_iommu(iommu)
2737 iommu_flush_all_caches(iommu);
2738 }
2739 }
2740
2741 return ret;
2742 }
2743
2744 static bool amd_iommu_sme_check(void)
2745 {
2746 if (!sme_active() || (boot_cpu_data.x86 != 0x17))
2747 return true;
2748
2749 /* For Fam17h, a specific level of support is required */
2750 if (boot_cpu_data.microcode >= 0x08001205)
2751 return true;
2752
2753 if ((boot_cpu_data.microcode >= 0x08001126) &&
2754 (boot_cpu_data.microcode <= 0x080011ff))
2755 return true;
2756
2757 pr_notice("AMD-Vi: IOMMU not currently supported when SME is active\n");
2758
2759 return false;
2760 }
2761
2762 /****************************************************************************
2763 *
2764 * Early detect code. This code runs at IOMMU detection time in the DMA
2765 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2766 * IOMMUs
2767 *
2768 ****************************************************************************/
2769 int __init amd_iommu_detect(void)
2770 {
2771 int ret;
2772
2773 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2774 return -ENODEV;
2775
2776 if (!amd_iommu_sme_check())
2777 return -ENODEV;
2778
2779 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2780 if (ret)
2781 return ret;
2782
2783 amd_iommu_detected = true;
2784 iommu_detected = 1;
2785 x86_init.iommu.iommu_init = amd_iommu_init;
2786
2787 return 1;
2788 }
2789
2790 /****************************************************************************
2791 *
2792 * Parsing functions for the AMD IOMMU specific kernel command line
2793 * options.
2794 *
2795 ****************************************************************************/
2796
2797 static int __init parse_amd_iommu_dump(char *str)
2798 {
2799 amd_iommu_dump = true;
2800
2801 return 1;
2802 }
2803
2804 static int __init parse_amd_iommu_intr(char *str)
2805 {
2806 for (; *str; ++str) {
2807 if (strncmp(str, "legacy", 6) == 0) {
2808 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
2809 break;
2810 }
2811 if (strncmp(str, "vapic", 5) == 0) {
2812 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2813 break;
2814 }
2815 }
2816 return 1;
2817 }
2818
2819 static int __init parse_amd_iommu_options(char *str)
2820 {
2821 for (; *str; ++str) {
2822 if (strncmp(str, "fullflush", 9) == 0)
2823 amd_iommu_unmap_flush = true;
2824 if (strncmp(str, "off", 3) == 0)
2825 amd_iommu_disabled = true;
2826 if (strncmp(str, "force_isolation", 15) == 0)
2827 amd_iommu_force_isolation = true;
2828 }
2829
2830 return 1;
2831 }
2832
2833 static int __init parse_ivrs_ioapic(char *str)
2834 {
2835 unsigned int bus, dev, fn;
2836 int ret, id, i;
2837 u16 devid;
2838
2839 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2840
2841 if (ret != 4) {
2842 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2843 return 1;
2844 }
2845
2846 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2847 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2848 str);
2849 return 1;
2850 }
2851
2852 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2853
2854 cmdline_maps = true;
2855 i = early_ioapic_map_size++;
2856 early_ioapic_map[i].id = id;
2857 early_ioapic_map[i].devid = devid;
2858 early_ioapic_map[i].cmd_line = true;
2859
2860 return 1;
2861 }
2862
2863 static int __init parse_ivrs_hpet(char *str)
2864 {
2865 unsigned int bus, dev, fn;
2866 int ret, id, i;
2867 u16 devid;
2868
2869 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2870
2871 if (ret != 4) {
2872 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2873 return 1;
2874 }
2875
2876 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2877 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2878 str);
2879 return 1;
2880 }
2881
2882 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2883
2884 cmdline_maps = true;
2885 i = early_hpet_map_size++;
2886 early_hpet_map[i].id = id;
2887 early_hpet_map[i].devid = devid;
2888 early_hpet_map[i].cmd_line = true;
2889
2890 return 1;
2891 }
2892
2893 static int __init parse_ivrs_acpihid(char *str)
2894 {
2895 u32 bus, dev, fn;
2896 char *hid, *uid, *p;
2897 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2898 int ret, i;
2899
2900 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2901 if (ret != 4) {
2902 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str);
2903 return 1;
2904 }
2905
2906 p = acpiid;
2907 hid = strsep(&p, ":");
2908 uid = p;
2909
2910 if (!hid || !(*hid) || !uid) {
2911 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2912 return 1;
2913 }
2914
2915 i = early_acpihid_map_size++;
2916 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2917 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2918 early_acpihid_map[i].devid =
2919 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2920 early_acpihid_map[i].cmd_line = true;
2921
2922 return 1;
2923 }
2924
2925 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2926 __setup("amd_iommu=", parse_amd_iommu_options);
2927 __setup("amd_iommu_intr=", parse_amd_iommu_intr);
2928 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2929 __setup("ivrs_hpet", parse_ivrs_hpet);
2930 __setup("ivrs_acpihid", parse_ivrs_acpihid);
2931
2932 IOMMU_INIT_FINISH(amd_iommu_detect,
2933 gart_iommu_hole_init,
2934 NULL,
2935 NULL);
2936
2937 bool amd_iommu_v2_supported(void)
2938 {
2939 return amd_iommu_v2_present;
2940 }
2941 EXPORT_SYMBOL(amd_iommu_v2_supported);
2942
2943 struct amd_iommu *get_amd_iommu(unsigned int idx)
2944 {
2945 unsigned int i = 0;
2946 struct amd_iommu *iommu;
2947
2948 for_each_iommu(iommu)
2949 if (i++ == idx)
2950 return iommu;
2951 return NULL;
2952 }
2953 EXPORT_SYMBOL(get_amd_iommu);
2954
2955 /****************************************************************************
2956 *
2957 * IOMMU EFR Performance Counter support functionality. This code allows
2958 * access to the IOMMU PC functionality.
2959 *
2960 ****************************************************************************/
2961
2962 u8 amd_iommu_pc_get_max_banks(unsigned int idx)
2963 {
2964 struct amd_iommu *iommu = get_amd_iommu(idx);
2965
2966 if (iommu)
2967 return iommu->max_banks;
2968
2969 return 0;
2970 }
2971 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2972
2973 bool amd_iommu_pc_supported(void)
2974 {
2975 return amd_iommu_pc_present;
2976 }
2977 EXPORT_SYMBOL(amd_iommu_pc_supported);
2978
2979 u8 amd_iommu_pc_get_max_counters(unsigned int idx)
2980 {
2981 struct amd_iommu *iommu = get_amd_iommu(idx);
2982
2983 if (iommu)
2984 return iommu->max_counters;
2985
2986 return 0;
2987 }
2988 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2989
2990 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
2991 u8 fxn, u64 *value, bool is_write)
2992 {
2993 u32 offset;
2994 u32 max_offset_lim;
2995
2996 /* Make sure the IOMMU PC resource is available */
2997 if (!amd_iommu_pc_present)
2998 return -ENODEV;
2999
3000 /* Check for valid iommu and pc register indexing */
3001 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
3002 return -ENODEV;
3003
3004 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
3005
3006 /* Limit the offset to the hw defined mmio region aperture */
3007 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
3008 (iommu->max_counters << 8) | 0x28);
3009 if ((offset < MMIO_CNTR_REG_OFFSET) ||
3010 (offset > max_offset_lim))
3011 return -EINVAL;
3012
3013 if (is_write) {
3014 u64 val = *value & GENMASK_ULL(47, 0);
3015
3016 writel((u32)val, iommu->mmio_base + offset);
3017 writel((val >> 32), iommu->mmio_base + offset + 4);
3018 } else {
3019 *value = readl(iommu->mmio_base + offset + 4);
3020 *value <<= 32;
3021 *value |= readl(iommu->mmio_base + offset);
3022 *value &= GENMASK_ULL(47, 0);
3023 }
3024
3025 return 0;
3026 }
3027
3028 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3029 {
3030 if (!iommu)
3031 return -EINVAL;
3032
3033 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
3034 }
3035 EXPORT_SYMBOL(amd_iommu_pc_get_reg);
3036
3037 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3038 {
3039 if (!iommu)
3040 return -EINVAL;
3041
3042 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
3043 }
3044 EXPORT_SYMBOL(amd_iommu_pc_set_reg);
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