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net: remove mm.h inclusion from netdevice.h
[linux-stable.git] / drivers / net / wireless / ath / ath9k / xmit.c
blob7e79bbaf2ba76bc2bc39548c1d61e2d95b3fd63b
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34
35
36 static u16 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 };
47
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
49
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid,
52 struct list_head *bf_head);
53 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
54 struct ath_txq *txq, struct list_head *bf_q,
55 struct ath_tx_status *ts, int txok, int sendbar);
56 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
57 struct list_head *head, bool internal);
58 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
61 int txok, bool update_rc);
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
63 int seqno);
64
65 enum {
66 MCS_HT20,
67 MCS_HT20_SGI,
68 MCS_HT40,
69 MCS_HT40_SGI,
70 };
71
72 static int ath_max_4ms_framelen[4][32] = {
73 [MCS_HT20] = {
74 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
75 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
76 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
77 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
78 },
79 [MCS_HT20_SGI] = {
80 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
81 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
82 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
83 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
84 },
85 [MCS_HT40] = {
86 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
87 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
88 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
89 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
90 },
91 [MCS_HT40_SGI] = {
92 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
93 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
94 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
95 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
96 }
97 };
98
99 /*********************/
100 /* Aggregation logic */
101 /*********************/
102
103 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
104 {
105 struct ath_atx_ac *ac = tid->ac;
106
107 if (tid->paused)
108 return;
109
110 if (tid->sched)
111 return;
112
113 tid->sched = true;
114 list_add_tail(&tid->list, &ac->tid_q);
115
116 if (ac->sched)
117 return;
118
119 ac->sched = true;
120 list_add_tail(&ac->list, &txq->axq_acq);
121 }
122
123 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
124 {
125 struct ath_txq *txq = tid->ac->txq;
126
127 WARN_ON(!tid->paused);
128
129 spin_lock_bh(&txq->axq_lock);
130 tid->paused = false;
131
132 if (list_empty(&tid->buf_q))
133 goto unlock;
134
135 ath_tx_queue_tid(txq, tid);
136 ath_txq_schedule(sc, txq);
137 unlock:
138 spin_unlock_bh(&txq->axq_lock);
139 }
140
141 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
142 {
143 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
144 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
145 sizeof(tx_info->rate_driver_data));
146 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
147 }
148
149 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
150 {
151 struct ath_txq *txq = tid->ac->txq;
152 struct ath_buf *bf;
153 struct list_head bf_head;
154 struct ath_tx_status ts;
155 struct ath_frame_info *fi;
156
157 INIT_LIST_HEAD(&bf_head);
158
159 memset(&ts, 0, sizeof(ts));
160 spin_lock_bh(&txq->axq_lock);
161
162 while (!list_empty(&tid->buf_q)) {
163 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
164 list_move_tail(&bf->list, &bf_head);
165
166 spin_unlock_bh(&txq->axq_lock);
167 fi = get_frame_info(bf->bf_mpdu);
168 if (fi->retries) {
169 ath_tx_update_baw(sc, tid, fi->seqno);
170 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
171 } else {
172 ath_tx_send_normal(sc, txq, NULL, &bf_head);
173 }
174 spin_lock_bh(&txq->axq_lock);
175 }
176
177 spin_unlock_bh(&txq->axq_lock);
178 }
179
180 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
181 int seqno)
182 {
183 int index, cindex;
184
185 index = ATH_BA_INDEX(tid->seq_start, seqno);
186 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
187
188 __clear_bit(cindex, tid->tx_buf);
189
190 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
191 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
192 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
193 }
194 }
195
196 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
197 u16 seqno)
198 {
199 int index, cindex;
200
201 index = ATH_BA_INDEX(tid->seq_start, seqno);
202 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
203 __set_bit(cindex, tid->tx_buf);
204
205 if (index >= ((tid->baw_tail - tid->baw_head) &
206 (ATH_TID_MAX_BUFS - 1))) {
207 tid->baw_tail = cindex;
208 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
209 }
210 }
211
212 /*
213 * TODO: For frame(s) that are in the retry state, we will reuse the
214 * sequence number(s) without setting the retry bit. The
215 * alternative is to give up on these and BAR the receiver's window
216 * forward.
217 */
218 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
219 struct ath_atx_tid *tid)
220
221 {
222 struct ath_buf *bf;
223 struct list_head bf_head;
224 struct ath_tx_status ts;
225 struct ath_frame_info *fi;
226
227 memset(&ts, 0, sizeof(ts));
228 INIT_LIST_HEAD(&bf_head);
229
230 for (;;) {
231 if (list_empty(&tid->buf_q))
232 break;
233
234 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
235 list_move_tail(&bf->list, &bf_head);
236
237 fi = get_frame_info(bf->bf_mpdu);
238 if (fi->retries)
239 ath_tx_update_baw(sc, tid, fi->seqno);
240
241 spin_unlock(&txq->axq_lock);
242 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
243 spin_lock(&txq->axq_lock);
244 }
245
246 tid->seq_next = tid->seq_start;
247 tid->baw_tail = tid->baw_head;
248 }
249
250 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
251 struct sk_buff *skb)
252 {
253 struct ath_frame_info *fi = get_frame_info(skb);
254 struct ieee80211_hdr *hdr;
255
256 TX_STAT_INC(txq->axq_qnum, a_retries);
257 if (fi->retries++ > 0)
258 return;
259
260 hdr = (struct ieee80211_hdr *)skb->data;
261 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
262 }
263
264 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
265 {
266 struct ath_buf *bf = NULL;
267
268 spin_lock_bh(&sc->tx.txbuflock);
269
270 if (unlikely(list_empty(&sc->tx.txbuf))) {
271 spin_unlock_bh(&sc->tx.txbuflock);
272 return NULL;
273 }
274
275 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
276 list_del(&bf->list);
277
278 spin_unlock_bh(&sc->tx.txbuflock);
279
280 return bf;
281 }
282
283 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
284 {
285 spin_lock_bh(&sc->tx.txbuflock);
286 list_add_tail(&bf->list, &sc->tx.txbuf);
287 spin_unlock_bh(&sc->tx.txbuflock);
288 }
289
290 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
291 {
292 struct ath_buf *tbf;
293
294 tbf = ath_tx_get_buffer(sc);
295 if (WARN_ON(!tbf))
296 return NULL;
297
298 ATH_TXBUF_RESET(tbf);
299
300 tbf->bf_mpdu = bf->bf_mpdu;
301 tbf->bf_buf_addr = bf->bf_buf_addr;
302 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
303 tbf->bf_state = bf->bf_state;
304
305 return tbf;
306 }
307
308 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
309 struct ath_tx_status *ts, int txok,
310 int *nframes, int *nbad)
311 {
312 struct ath_frame_info *fi;
313 u16 seq_st = 0;
314 u32 ba[WME_BA_BMP_SIZE >> 5];
315 int ba_index;
316 int isaggr = 0;
317
318 *nbad = 0;
319 *nframes = 0;
320
321 isaggr = bf_isaggr(bf);
322 if (isaggr) {
323 seq_st = ts->ts_seqnum;
324 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
325 }
326
327 while (bf) {
328 fi = get_frame_info(bf->bf_mpdu);
329 ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
330
331 (*nframes)++;
332 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
333 (*nbad)++;
334
335 bf = bf->bf_next;
336 }
337 }
338
339
340 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
341 struct ath_buf *bf, struct list_head *bf_q,
342 struct ath_tx_status *ts, int txok, bool retry)
343 {
344 struct ath_node *an = NULL;
345 struct sk_buff *skb;
346 struct ieee80211_sta *sta;
347 struct ieee80211_hw *hw = sc->hw;
348 struct ieee80211_hdr *hdr;
349 struct ieee80211_tx_info *tx_info;
350 struct ath_atx_tid *tid = NULL;
351 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
352 struct list_head bf_head, bf_pending;
353 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
354 u32 ba[WME_BA_BMP_SIZE >> 5];
355 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
356 bool rc_update = true;
357 struct ieee80211_tx_rate rates[4];
358 struct ath_frame_info *fi;
359 int nframes;
360 u8 tidno;
361 bool clear_filter;
362
363 skb = bf->bf_mpdu;
364 hdr = (struct ieee80211_hdr *)skb->data;
365
366 tx_info = IEEE80211_SKB_CB(skb);
367
368 memcpy(rates, tx_info->control.rates, sizeof(rates));
369
370 rcu_read_lock();
371
372 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
373 if (!sta) {
374 rcu_read_unlock();
375
376 INIT_LIST_HEAD(&bf_head);
377 while (bf) {
378 bf_next = bf->bf_next;
379
380 bf->bf_state.bf_type |= BUF_XRETRY;
381 if (!bf->bf_stale || bf_next != NULL)
382 list_move_tail(&bf->list, &bf_head);
383
384 ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false);
385 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
386 0, 0);
387
388 bf = bf_next;
389 }
390 return;
391 }
392
393 an = (struct ath_node *)sta->drv_priv;
394 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
395 tid = ATH_AN_2_TID(an, tidno);
396
397 /*
398 * The hardware occasionally sends a tx status for the wrong TID.
399 * In this case, the BA status cannot be considered valid and all
400 * subframes need to be retransmitted
401 */
402 if (tidno != ts->tid)
403 txok = false;
404
405 isaggr = bf_isaggr(bf);
406 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
407
408 if (isaggr && txok) {
409 if (ts->ts_flags & ATH9K_TX_BA) {
410 seq_st = ts->ts_seqnum;
411 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
412 } else {
413 /*
414 * AR5416 can become deaf/mute when BA
415 * issue happens. Chip needs to be reset.
416 * But AP code may have sychronization issues
417 * when perform internal reset in this routine.
418 * Only enable reset in STA mode for now.
419 */
420 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
421 needreset = 1;
422 }
423 }
424
425 INIT_LIST_HEAD(&bf_pending);
426 INIT_LIST_HEAD(&bf_head);
427
428 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
429 while (bf) {
430 txfail = txpending = sendbar = 0;
431 bf_next = bf->bf_next;
432
433 skb = bf->bf_mpdu;
434 tx_info = IEEE80211_SKB_CB(skb);
435 fi = get_frame_info(skb);
436
437 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
438 /* transmit completion, subframe is
439 * acked by block ack */
440 acked_cnt++;
441 } else if (!isaggr && txok) {
442 /* transmit completion */
443 acked_cnt++;
444 } else {
445 if ((tid->state & AGGR_CLEANUP) || !retry) {
446 /*
447 * cleanup in progress, just fail
448 * the un-acked sub-frames
449 */
450 txfail = 1;
451 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
452 if (!(ts->ts_status & ATH9K_TXERR_FILT) ||
453 !an->sleeping)
454 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
455
456 clear_filter = true;
457 txpending = 1;
458 } else {
459 bf->bf_state.bf_type |= BUF_XRETRY;
460 txfail = 1;
461 sendbar = 1;
462 txfail_cnt++;
463 }
464 }
465
466 /*
467 * Make sure the last desc is reclaimed if it
468 * not a holding desc.
469 */
470 if (!bf_last->bf_stale || bf_next != NULL)
471 list_move_tail(&bf->list, &bf_head);
472 else
473 INIT_LIST_HEAD(&bf_head);
474
475 if (!txpending || (tid->state & AGGR_CLEANUP)) {
476 /*
477 * complete the acked-ones/xretried ones; update
478 * block-ack window
479 */
480 spin_lock_bh(&txq->axq_lock);
481 ath_tx_update_baw(sc, tid, fi->seqno);
482 spin_unlock_bh(&txq->axq_lock);
483
484 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
485 memcpy(tx_info->control.rates, rates, sizeof(rates));
486 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, true);
487 rc_update = false;
488 } else {
489 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, false);
490 }
491
492 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
493 !txfail, sendbar);
494 } else {
495 /* retry the un-acked ones */
496 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, false);
497 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
498 if (bf->bf_next == NULL && bf_last->bf_stale) {
499 struct ath_buf *tbf;
500
501 tbf = ath_clone_txbuf(sc, bf_last);
502 /*
503 * Update tx baw and complete the
504 * frame with failed status if we
505 * run out of tx buf.
506 */
507 if (!tbf) {
508 spin_lock_bh(&txq->axq_lock);
509 ath_tx_update_baw(sc, tid, fi->seqno);
510 spin_unlock_bh(&txq->axq_lock);
511
512 bf->bf_state.bf_type |=
513 BUF_XRETRY;
514 ath_tx_rc_status(sc, bf, ts, nframes,
515 nbad, 0, false);
516 ath_tx_complete_buf(sc, bf, txq,
517 &bf_head,
518 ts, 0, 0);
519 break;
520 }
521
522 ath9k_hw_cleartxdesc(sc->sc_ah,
523 tbf->bf_desc);
524 list_add_tail(&tbf->list, &bf_head);
525 } else {
526 /*
527 * Clear descriptor status words for
528 * software retry
529 */
530 ath9k_hw_cleartxdesc(sc->sc_ah,
531 bf->bf_desc);
532 }
533 }
534
535 /*
536 * Put this buffer to the temporary pending
537 * queue to retain ordering
538 */
539 list_splice_tail_init(&bf_head, &bf_pending);
540 }
541
542 bf = bf_next;
543 }
544
545 /* prepend un-acked frames to the beginning of the pending frame queue */
546 if (!list_empty(&bf_pending)) {
547 if (an->sleeping)
548 ieee80211_sta_set_tim(sta);
549
550 spin_lock_bh(&txq->axq_lock);
551 if (clear_filter)
552 tid->ac->clear_ps_filter = true;
553 list_splice(&bf_pending, &tid->buf_q);
554 ath_tx_queue_tid(txq, tid);
555 spin_unlock_bh(&txq->axq_lock);
556 }
557
558 if (tid->state & AGGR_CLEANUP) {
559 ath_tx_flush_tid(sc, tid);
560
561 if (tid->baw_head == tid->baw_tail) {
562 tid->state &= ~AGGR_ADDBA_COMPLETE;
563 tid->state &= ~AGGR_CLEANUP;
564 }
565 }
566
567 rcu_read_unlock();
568
569 if (needreset) {
570 spin_unlock_bh(&sc->sc_pcu_lock);
571 ath_reset(sc, false);
572 spin_lock_bh(&sc->sc_pcu_lock);
573 }
574 }
575
576 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
577 struct ath_atx_tid *tid)
578 {
579 struct sk_buff *skb;
580 struct ieee80211_tx_info *tx_info;
581 struct ieee80211_tx_rate *rates;
582 u32 max_4ms_framelen, frmlen;
583 u16 aggr_limit, legacy = 0;
584 int i;
585
586 skb = bf->bf_mpdu;
587 tx_info = IEEE80211_SKB_CB(skb);
588 rates = tx_info->control.rates;
589
590 /*
591 * Find the lowest frame length among the rate series that will have a
592 * 4ms transmit duration.
593 * TODO - TXOP limit needs to be considered.
594 */
595 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
596
597 for (i = 0; i < 4; i++) {
598 if (rates[i].count) {
599 int modeidx;
600 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
601 legacy = 1;
602 break;
603 }
604
605 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
606 modeidx = MCS_HT40;
607 else
608 modeidx = MCS_HT20;
609
610 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
611 modeidx++;
612
613 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
614 max_4ms_framelen = min(max_4ms_framelen, frmlen);
615 }
616 }
617
618 /*
619 * limit aggregate size by the minimum rate if rate selected is
620 * not a probe rate, if rate selected is a probe rate then
621 * avoid aggregation of this packet.
622 */
623 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
624 return 0;
625
626 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
627 aggr_limit = min((max_4ms_framelen * 3) / 8,
628 (u32)ATH_AMPDU_LIMIT_MAX);
629 else
630 aggr_limit = min(max_4ms_framelen,
631 (u32)ATH_AMPDU_LIMIT_MAX);
632
633 /*
634 * h/w can accept aggregates up to 16 bit lengths (65535).
635 * The IE, however can hold up to 65536, which shows up here
636 * as zero. Ignore 65536 since we are constrained by hw.
637 */
638 if (tid->an->maxampdu)
639 aggr_limit = min(aggr_limit, tid->an->maxampdu);
640
641 return aggr_limit;
642 }
643
644 /*
645 * Returns the number of delimiters to be added to
646 * meet the minimum required mpdudensity.
647 */
648 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
649 struct ath_buf *bf, u16 frmlen)
650 {
651 struct sk_buff *skb = bf->bf_mpdu;
652 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
653 u32 nsymbits, nsymbols;
654 u16 minlen;
655 u8 flags, rix;
656 int width, streams, half_gi, ndelim, mindelim;
657 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
658
659 /* Select standard number of delimiters based on frame length alone */
660 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
661
662 /*
663 * If encryption enabled, hardware requires some more padding between
664 * subframes.
665 * TODO - this could be improved to be dependent on the rate.
666 * The hardware can keep up at lower rates, but not higher rates
667 */
668 if (fi->keyix != ATH9K_TXKEYIX_INVALID)
669 ndelim += ATH_AGGR_ENCRYPTDELIM;
670
671 /*
672 * Convert desired mpdu density from microeconds to bytes based
673 * on highest rate in rate series (i.e. first rate) to determine
674 * required minimum length for subframe. Take into account
675 * whether high rate is 20 or 40Mhz and half or full GI.
676 *
677 * If there is no mpdu density restriction, no further calculation
678 * is needed.
679 */
680
681 if (tid->an->mpdudensity == 0)
682 return ndelim;
683
684 rix = tx_info->control.rates[0].idx;
685 flags = tx_info->control.rates[0].flags;
686 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
687 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
688
689 if (half_gi)
690 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
691 else
692 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
693
694 if (nsymbols == 0)
695 nsymbols = 1;
696
697 streams = HT_RC_2_STREAMS(rix);
698 nsymbits = bits_per_symbol[rix % 8][width] * streams;
699 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
700
701 if (frmlen < minlen) {
702 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
703 ndelim = max(mindelim, ndelim);
704 }
705
706 return ndelim;
707 }
708
709 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
710 struct ath_txq *txq,
711 struct ath_atx_tid *tid,
712 struct list_head *bf_q,
713 int *aggr_len)
714 {
715 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
716 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
717 int rl = 0, nframes = 0, ndelim, prev_al = 0;
718 u16 aggr_limit = 0, al = 0, bpad = 0,
719 al_delta, h_baw = tid->baw_size / 2;
720 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
721 struct ieee80211_tx_info *tx_info;
722 struct ath_frame_info *fi;
723
724 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
725
726 do {
727 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
728 fi = get_frame_info(bf->bf_mpdu);
729
730 /* do not step over block-ack window */
731 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
732 status = ATH_AGGR_BAW_CLOSED;
733 break;
734 }
735
736 if (!rl) {
737 aggr_limit = ath_lookup_rate(sc, bf, tid);
738 rl = 1;
739 }
740
741 /* do not exceed aggregation limit */
742 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
743
744 if (nframes &&
745 (aggr_limit < (al + bpad + al_delta + prev_al))) {
746 status = ATH_AGGR_LIMITED;
747 break;
748 }
749
750 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
751 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
752 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
753 break;
754
755 /* do not exceed subframe limit */
756 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
757 status = ATH_AGGR_LIMITED;
758 break;
759 }
760 nframes++;
761
762 /* add padding for previous frame to aggregation length */
763 al += bpad + al_delta;
764
765 /*
766 * Get the delimiters needed to meet the MPDU
767 * density for this node.
768 */
769 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
770 bpad = PADBYTES(al_delta) + (ndelim << 2);
771
772 bf->bf_next = NULL;
773 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
774
775 /* link buffers of this frame to the aggregate */
776 if (!fi->retries)
777 ath_tx_addto_baw(sc, tid, fi->seqno);
778 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
779 list_move_tail(&bf->list, bf_q);
780 if (bf_prev) {
781 bf_prev->bf_next = bf;
782 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
783 bf->bf_daddr);
784 }
785 bf_prev = bf;
786
787 } while (!list_empty(&tid->buf_q));
788
789 *aggr_len = al;
790
791 return status;
792 #undef PADBYTES
793 }
794
795 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
796 struct ath_atx_tid *tid)
797 {
798 struct ath_buf *bf;
799 enum ATH_AGGR_STATUS status;
800 struct ath_frame_info *fi;
801 struct list_head bf_q;
802 int aggr_len;
803
804 do {
805 if (list_empty(&tid->buf_q))
806 return;
807
808 INIT_LIST_HEAD(&bf_q);
809
810 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
811
812 /*
813 * no frames picked up to be aggregated;
814 * block-ack window is not open.
815 */
816 if (list_empty(&bf_q))
817 break;
818
819 bf = list_first_entry(&bf_q, struct ath_buf, list);
820 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
821
822 if (tid->ac->clear_ps_filter) {
823 tid->ac->clear_ps_filter = false;
824 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
825 }
826
827 /* if only one frame, send as non-aggregate */
828 if (bf == bf->bf_lastbf) {
829 fi = get_frame_info(bf->bf_mpdu);
830
831 bf->bf_state.bf_type &= ~BUF_AGGR;
832 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
833 ath_buf_set_rate(sc, bf, fi->framelen);
834 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
835 continue;
836 }
837
838 /* setup first desc of aggregate */
839 bf->bf_state.bf_type |= BUF_AGGR;
840 ath_buf_set_rate(sc, bf, aggr_len);
841 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
842
843 /* anchor last desc of aggregate */
844 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
845
846 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
847 TX_STAT_INC(txq->axq_qnum, a_aggr);
848
849 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
850 status != ATH_AGGR_BAW_CLOSED);
851 }
852
853 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
854 u16 tid, u16 *ssn)
855 {
856 struct ath_atx_tid *txtid;
857 struct ath_node *an;
858
859 an = (struct ath_node *)sta->drv_priv;
860 txtid = ATH_AN_2_TID(an, tid);
861
862 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
863 return -EAGAIN;
864
865 txtid->state |= AGGR_ADDBA_PROGRESS;
866 txtid->paused = true;
867 *ssn = txtid->seq_start = txtid->seq_next;
868
869 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
870 txtid->baw_head = txtid->baw_tail = 0;
871
872 return 0;
873 }
874
875 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
876 {
877 struct ath_node *an = (struct ath_node *)sta->drv_priv;
878 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
879 struct ath_txq *txq = txtid->ac->txq;
880
881 if (txtid->state & AGGR_CLEANUP)
882 return;
883
884 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
885 txtid->state &= ~AGGR_ADDBA_PROGRESS;
886 return;
887 }
888
889 spin_lock_bh(&txq->axq_lock);
890 txtid->paused = true;
891
892 /*
893 * If frames are still being transmitted for this TID, they will be
894 * cleaned up during tx completion. To prevent race conditions, this
895 * TID can only be reused after all in-progress subframes have been
896 * completed.
897 */
898 if (txtid->baw_head != txtid->baw_tail)
899 txtid->state |= AGGR_CLEANUP;
900 else
901 txtid->state &= ~AGGR_ADDBA_COMPLETE;
902 spin_unlock_bh(&txq->axq_lock);
903
904 ath_tx_flush_tid(sc, txtid);
905 }
906
907 bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an)
908 {
909 struct ath_atx_tid *tid;
910 struct ath_atx_ac *ac;
911 struct ath_txq *txq;
912 bool buffered = false;
913 int tidno;
914
915 for (tidno = 0, tid = &an->tid[tidno];
916 tidno < WME_NUM_TID; tidno++, tid++) {
917
918 if (!tid->sched)
919 continue;
920
921 ac = tid->ac;
922 txq = ac->txq;
923
924 spin_lock_bh(&txq->axq_lock);
925
926 if (!list_empty(&tid->buf_q))
927 buffered = true;
928
929 tid->sched = false;
930 list_del(&tid->list);
931
932 if (ac->sched) {
933 ac->sched = false;
934 list_del(&ac->list);
935 }
936
937 spin_unlock_bh(&txq->axq_lock);
938 }
939
940 return buffered;
941 }
942
943 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
944 {
945 struct ath_atx_tid *tid;
946 struct ath_atx_ac *ac;
947 struct ath_txq *txq;
948 int tidno;
949
950 for (tidno = 0, tid = &an->tid[tidno];
951 tidno < WME_NUM_TID; tidno++, tid++) {
952
953 ac = tid->ac;
954 txq = ac->txq;
955
956 spin_lock_bh(&txq->axq_lock);
957 ac->clear_ps_filter = true;
958
959 if (!list_empty(&tid->buf_q) && !tid->paused) {
960 ath_tx_queue_tid(txq, tid);
961 ath_txq_schedule(sc, txq);
962 }
963
964 spin_unlock_bh(&txq->axq_lock);
965 }
966 }
967
968 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
969 {
970 struct ath_atx_tid *txtid;
971 struct ath_node *an;
972
973 an = (struct ath_node *)sta->drv_priv;
974
975 if (sc->sc_flags & SC_OP_TXAGGR) {
976 txtid = ATH_AN_2_TID(an, tid);
977 txtid->baw_size =
978 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
979 txtid->state |= AGGR_ADDBA_COMPLETE;
980 txtid->state &= ~AGGR_ADDBA_PROGRESS;
981 ath_tx_resume_tid(sc, txtid);
982 }
983 }
984
985 /********************/
986 /* Queue Management */
987 /********************/
988
989 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
990 struct ath_txq *txq)
991 {
992 struct ath_atx_ac *ac, *ac_tmp;
993 struct ath_atx_tid *tid, *tid_tmp;
994
995 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
996 list_del(&ac->list);
997 ac->sched = false;
998 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
999 list_del(&tid->list);
1000 tid->sched = false;
1001 ath_tid_drain(sc, txq, tid);
1002 }
1003 }
1004 }
1005
1006 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1007 {
1008 struct ath_hw *ah = sc->sc_ah;
1009 struct ath_common *common = ath9k_hw_common(ah);
1010 struct ath9k_tx_queue_info qi;
1011 static const int subtype_txq_to_hwq[] = {
1012 [WME_AC_BE] = ATH_TXQ_AC_BE,
1013 [WME_AC_BK] = ATH_TXQ_AC_BK,
1014 [WME_AC_VI] = ATH_TXQ_AC_VI,
1015 [WME_AC_VO] = ATH_TXQ_AC_VO,
1016 };
1017 int axq_qnum, i;
1018
1019 memset(&qi, 0, sizeof(qi));
1020 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1021 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1022 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1023 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1024 qi.tqi_physCompBuf = 0;
1025
1026 /*
1027 * Enable interrupts only for EOL and DESC conditions.
1028 * We mark tx descriptors to receive a DESC interrupt
1029 * when a tx queue gets deep; otherwise waiting for the
1030 * EOL to reap descriptors. Note that this is done to
1031 * reduce interrupt load and this only defers reaping
1032 * descriptors, never transmitting frames. Aside from
1033 * reducing interrupts this also permits more concurrency.
1034 * The only potential downside is if the tx queue backs
1035 * up in which case the top half of the kernel may backup
1036 * due to a lack of tx descriptors.
1037 *
1038 * The UAPSD queue is an exception, since we take a desc-
1039 * based intr on the EOSP frames.
1040 */
1041 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1042 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1043 TXQ_FLAG_TXERRINT_ENABLE;
1044 } else {
1045 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1046 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1047 else
1048 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1049 TXQ_FLAG_TXDESCINT_ENABLE;
1050 }
1051 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1052 if (axq_qnum == -1) {
1053 /*
1054 * NB: don't print a message, this happens
1055 * normally on parts with too few tx queues
1056 */
1057 return NULL;
1058 }
1059 if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
1060 ath_err(common, "qnum %u out of range, max %zu!\n",
1061 axq_qnum, ARRAY_SIZE(sc->tx.txq));
1062 ath9k_hw_releasetxqueue(ah, axq_qnum);
1063 return NULL;
1064 }
1065 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1066 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1067
1068 txq->axq_qnum = axq_qnum;
1069 txq->mac80211_qnum = -1;
1070 txq->axq_link = NULL;
1071 INIT_LIST_HEAD(&txq->axq_q);
1072 INIT_LIST_HEAD(&txq->axq_acq);
1073 spin_lock_init(&txq->axq_lock);
1074 txq->axq_depth = 0;
1075 txq->axq_ampdu_depth = 0;
1076 txq->axq_tx_inprogress = false;
1077 sc->tx.txqsetup |= 1<<axq_qnum;
1078
1079 txq->txq_headidx = txq->txq_tailidx = 0;
1080 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1081 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1082 }
1083 return &sc->tx.txq[axq_qnum];
1084 }
1085
1086 int ath_txq_update(struct ath_softc *sc, int qnum,
1087 struct ath9k_tx_queue_info *qinfo)
1088 {
1089 struct ath_hw *ah = sc->sc_ah;
1090 int error = 0;
1091 struct ath9k_tx_queue_info qi;
1092
1093 if (qnum == sc->beacon.beaconq) {
1094 /*
1095 * XXX: for beacon queue, we just save the parameter.
1096 * It will be picked up by ath_beaconq_config when
1097 * it's necessary.
1098 */
1099 sc->beacon.beacon_qi = *qinfo;
1100 return 0;
1101 }
1102
1103 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1104
1105 ath9k_hw_get_txq_props(ah, qnum, &qi);
1106 qi.tqi_aifs = qinfo->tqi_aifs;
1107 qi.tqi_cwmin = qinfo->tqi_cwmin;
1108 qi.tqi_cwmax = qinfo->tqi_cwmax;
1109 qi.tqi_burstTime = qinfo->tqi_burstTime;
1110 qi.tqi_readyTime = qinfo->tqi_readyTime;
1111
1112 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1113 ath_err(ath9k_hw_common(sc->sc_ah),
1114 "Unable to update hardware queue %u!\n", qnum);
1115 error = -EIO;
1116 } else {
1117 ath9k_hw_resettxqueue(ah, qnum);
1118 }
1119
1120 return error;
1121 }
1122
1123 int ath_cabq_update(struct ath_softc *sc)
1124 {
1125 struct ath9k_tx_queue_info qi;
1126 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1127 int qnum = sc->beacon.cabq->axq_qnum;
1128
1129 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1130 /*
1131 * Ensure the readytime % is within the bounds.
1132 */
1133 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1134 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1135 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1136 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1137
1138 qi.tqi_readyTime = (cur_conf->beacon_interval *
1139 sc->config.cabqReadytime) / 100;
1140 ath_txq_update(sc, qnum, &qi);
1141
1142 return 0;
1143 }
1144
1145 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1146 {
1147 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1148 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1149 }
1150
1151 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1152 struct list_head *list, bool retry_tx)
1153 {
1154 struct ath_buf *bf, *lastbf;
1155 struct list_head bf_head;
1156 struct ath_tx_status ts;
1157
1158 memset(&ts, 0, sizeof(ts));
1159 INIT_LIST_HEAD(&bf_head);
1160
1161 while (!list_empty(list)) {
1162 bf = list_first_entry(list, struct ath_buf, list);
1163
1164 if (bf->bf_stale) {
1165 list_del(&bf->list);
1166
1167 ath_tx_return_buffer(sc, bf);
1168 continue;
1169 }
1170
1171 lastbf = bf->bf_lastbf;
1172 list_cut_position(&bf_head, list, &lastbf->list);
1173
1174 txq->axq_depth--;
1175 if (bf_is_ampdu_not_probing(bf))
1176 txq->axq_ampdu_depth--;
1177
1178 spin_unlock_bh(&txq->axq_lock);
1179 if (bf_isampdu(bf))
1180 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1181 retry_tx);
1182 else
1183 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1184 spin_lock_bh(&txq->axq_lock);
1185 }
1186 }
1187
1188 /*
1189 * Drain a given TX queue (could be Beacon or Data)
1190 *
1191 * This assumes output has been stopped and
1192 * we do not need to block ath_tx_tasklet.
1193 */
1194 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1195 {
1196 spin_lock_bh(&txq->axq_lock);
1197 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1198 int idx = txq->txq_tailidx;
1199
1200 while (!list_empty(&txq->txq_fifo[idx])) {
1201 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1202 retry_tx);
1203
1204 INCR(idx, ATH_TXFIFO_DEPTH);
1205 }
1206 txq->txq_tailidx = idx;
1207 }
1208
1209 txq->axq_link = NULL;
1210 txq->axq_tx_inprogress = false;
1211 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1212
1213 /* flush any pending frames if aggregation is enabled */
1214 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1215 ath_txq_drain_pending_buffers(sc, txq);
1216
1217 spin_unlock_bh(&txq->axq_lock);
1218 }
1219
1220 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1221 {
1222 struct ath_hw *ah = sc->sc_ah;
1223 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1224 struct ath_txq *txq;
1225 int i, npend = 0;
1226
1227 if (sc->sc_flags & SC_OP_INVALID)
1228 return true;
1229
1230 ath9k_hw_abort_tx_dma(ah);
1231
1232 /* Check if any queue remains active */
1233 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1234 if (!ATH_TXQ_SETUP(sc, i))
1235 continue;
1236
1237 npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
1238 }
1239
1240 if (npend)
1241 ath_err(common, "Failed to stop TX DMA!\n");
1242
1243 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1244 if (!ATH_TXQ_SETUP(sc, i))
1245 continue;
1246
1247 /*
1248 * The caller will resume queues with ieee80211_wake_queues.
1249 * Mark the queue as not stopped to prevent ath_tx_complete
1250 * from waking the queue too early.
1251 */
1252 txq = &sc->tx.txq[i];
1253 txq->stopped = false;
1254 ath_draintxq(sc, txq, retry_tx);
1255 }
1256
1257 return !npend;
1258 }
1259
1260 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1261 {
1262 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1263 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1264 }
1265
1266 /* For each axq_acq entry, for each tid, try to schedule packets
1267 * for transmit until ampdu_depth has reached min Q depth.
1268 */
1269 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1270 {
1271 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1272 struct ath_atx_tid *tid, *last_tid;
1273
1274 if (list_empty(&txq->axq_acq) ||
1275 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1276 return;
1277
1278 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1279 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1280
1281 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1282 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1283 list_del(&ac->list);
1284 ac->sched = false;
1285
1286 while (!list_empty(&ac->tid_q)) {
1287 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1288 list);
1289 list_del(&tid->list);
1290 tid->sched = false;
1291
1292 if (tid->paused)
1293 continue;
1294
1295 ath_tx_sched_aggr(sc, txq, tid);
1296
1297 /*
1298 * add tid to round-robin queue if more frames
1299 * are pending for the tid
1300 */
1301 if (!list_empty(&tid->buf_q))
1302 ath_tx_queue_tid(txq, tid);
1303
1304 if (tid == last_tid ||
1305 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1306 break;
1307 }
1308
1309 if (!list_empty(&ac->tid_q)) {
1310 if (!ac->sched) {
1311 ac->sched = true;
1312 list_add_tail(&ac->list, &txq->axq_acq);
1313 }
1314 }
1315
1316 if (ac == last_ac ||
1317 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1318 return;
1319 }
1320 }
1321
1322 /***********/
1323 /* TX, DMA */
1324 /***********/
1325
1326 /*
1327 * Insert a chain of ath_buf (descriptors) on a txq and
1328 * assume the descriptors are already chained together by caller.
1329 */
1330 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1331 struct list_head *head, bool internal)
1332 {
1333 struct ath_hw *ah = sc->sc_ah;
1334 struct ath_common *common = ath9k_hw_common(ah);
1335 struct ath_buf *bf, *bf_last;
1336 bool puttxbuf = false;
1337 bool edma;
1338
1339 /*
1340 * Insert the frame on the outbound list and
1341 * pass it on to the hardware.
1342 */
1343
1344 if (list_empty(head))
1345 return;
1346
1347 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1348 bf = list_first_entry(head, struct ath_buf, list);
1349 bf_last = list_entry(head->prev, struct ath_buf, list);
1350
1351 ath_dbg(common, ATH_DBG_QUEUE,
1352 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1353
1354 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1355 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1356 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1357 puttxbuf = true;
1358 } else {
1359 list_splice_tail_init(head, &txq->axq_q);
1360
1361 if (txq->axq_link) {
1362 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1363 ath_dbg(common, ATH_DBG_XMIT,
1364 "link[%u] (%p)=%llx (%p)\n",
1365 txq->axq_qnum, txq->axq_link,
1366 ito64(bf->bf_daddr), bf->bf_desc);
1367 } else if (!edma)
1368 puttxbuf = true;
1369
1370 txq->axq_link = bf_last->bf_desc;
1371 }
1372
1373 if (puttxbuf) {
1374 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1375 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1376 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1377 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1378 }
1379
1380 if (!edma) {
1381 TX_STAT_INC(txq->axq_qnum, txstart);
1382 ath9k_hw_txstart(ah, txq->axq_qnum);
1383 }
1384
1385 if (!internal) {
1386 txq->axq_depth++;
1387 if (bf_is_ampdu_not_probing(bf))
1388 txq->axq_ampdu_depth++;
1389 }
1390 }
1391
1392 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1393 struct ath_buf *bf, struct ath_tx_control *txctl)
1394 {
1395 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1396 struct list_head bf_head;
1397
1398 bf->bf_state.bf_type |= BUF_AMPDU;
1399
1400 /*
1401 * Do not queue to h/w when any of the following conditions is true:
1402 * - there are pending frames in software queue
1403 * - the TID is currently paused for ADDBA/BAR request
1404 * - seqno is not within block-ack window
1405 * - h/w queue depth exceeds low water mark
1406 */
1407 if (!list_empty(&tid->buf_q) || tid->paused ||
1408 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
1409 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1410 /*
1411 * Add this frame to software queue for scheduling later
1412 * for aggregation.
1413 */
1414 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1415 list_add_tail(&bf->list, &tid->buf_q);
1416 ath_tx_queue_tid(txctl->txq, tid);
1417 return;
1418 }
1419
1420 INIT_LIST_HEAD(&bf_head);
1421 list_add(&bf->list, &bf_head);
1422
1423 /* Add sub-frame to BAW */
1424 if (!fi->retries)
1425 ath_tx_addto_baw(sc, tid, fi->seqno);
1426
1427 /* Queue to h/w without aggregation */
1428 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1429 bf->bf_lastbf = bf;
1430 ath_buf_set_rate(sc, bf, fi->framelen);
1431 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1432 }
1433
1434 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1435 struct ath_atx_tid *tid,
1436 struct list_head *bf_head)
1437 {
1438 struct ath_frame_info *fi;
1439 struct ath_buf *bf;
1440
1441 bf = list_first_entry(bf_head, struct ath_buf, list);
1442 bf->bf_state.bf_type &= ~BUF_AMPDU;
1443
1444 /* update starting sequence number for subsequent ADDBA request */
1445 if (tid)
1446 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1447
1448 bf->bf_lastbf = bf;
1449 fi = get_frame_info(bf->bf_mpdu);
1450 ath_buf_set_rate(sc, bf, fi->framelen);
1451 ath_tx_txqaddbuf(sc, txq, bf_head, false);
1452 TX_STAT_INC(txq->axq_qnum, queued);
1453 }
1454
1455 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1456 {
1457 struct ieee80211_hdr *hdr;
1458 enum ath9k_pkt_type htype;
1459 __le16 fc;
1460
1461 hdr = (struct ieee80211_hdr *)skb->data;
1462 fc = hdr->frame_control;
1463
1464 if (ieee80211_is_beacon(fc))
1465 htype = ATH9K_PKT_TYPE_BEACON;
1466 else if (ieee80211_is_probe_resp(fc))
1467 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1468 else if (ieee80211_is_atim(fc))
1469 htype = ATH9K_PKT_TYPE_ATIM;
1470 else if (ieee80211_is_pspoll(fc))
1471 htype = ATH9K_PKT_TYPE_PSPOLL;
1472 else
1473 htype = ATH9K_PKT_TYPE_NORMAL;
1474
1475 return htype;
1476 }
1477
1478 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1479 int framelen)
1480 {
1481 struct ath_softc *sc = hw->priv;
1482 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1483 struct ieee80211_sta *sta = tx_info->control.sta;
1484 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1485 struct ieee80211_hdr *hdr;
1486 struct ath_frame_info *fi = get_frame_info(skb);
1487 struct ath_node *an = NULL;
1488 struct ath_atx_tid *tid;
1489 enum ath9k_key_type keytype;
1490 u16 seqno = 0;
1491 u8 tidno;
1492
1493 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1494
1495 if (sta)
1496 an = (struct ath_node *) sta->drv_priv;
1497
1498 hdr = (struct ieee80211_hdr *)skb->data;
1499 if (an && ieee80211_is_data_qos(hdr->frame_control) &&
1500 conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
1501
1502 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
1503
1504 /*
1505 * Override seqno set by upper layer with the one
1506 * in tx aggregation state.
1507 */
1508 tid = ATH_AN_2_TID(an, tidno);
1509 seqno = tid->seq_next;
1510 hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
1511 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1512 }
1513
1514 memset(fi, 0, sizeof(*fi));
1515 if (hw_key)
1516 fi->keyix = hw_key->hw_key_idx;
1517 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1518 fi->keyix = an->ps_key;
1519 else
1520 fi->keyix = ATH9K_TXKEYIX_INVALID;
1521 fi->keytype = keytype;
1522 fi->framelen = framelen;
1523 fi->seqno = seqno;
1524 }
1525
1526 static int setup_tx_flags(struct sk_buff *skb)
1527 {
1528 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1529 int flags = 0;
1530
1531 flags |= ATH9K_TXDESC_INTREQ;
1532
1533 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1534 flags |= ATH9K_TXDESC_NOACK;
1535
1536 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1537 flags |= ATH9K_TXDESC_LDPC;
1538
1539 return flags;
1540 }
1541
1542 /*
1543 * rix - rate index
1544 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1545 * width - 0 for 20 MHz, 1 for 40 MHz
1546 * half_gi - to use 4us v/s 3.6 us for symbol time
1547 */
1548 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1549 int width, int half_gi, bool shortPreamble)
1550 {
1551 u32 nbits, nsymbits, duration, nsymbols;
1552 int streams;
1553
1554 /* find number of symbols: PLCP + data */
1555 streams = HT_RC_2_STREAMS(rix);
1556 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1557 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1558 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1559
1560 if (!half_gi)
1561 duration = SYMBOL_TIME(nsymbols);
1562 else
1563 duration = SYMBOL_TIME_HALFGI(nsymbols);
1564
1565 /* addup duration for legacy/ht training and signal fields */
1566 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1567
1568 return duration;
1569 }
1570
1571 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1572 {
1573 struct ath_hw *ah = sc->sc_ah;
1574 struct ath9k_channel *curchan = ah->curchan;
1575 if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
1576 (curchan->channelFlags & CHANNEL_5GHZ) &&
1577 (chainmask == 0x7) && (rate < 0x90))
1578 return 0x3;
1579 else
1580 return chainmask;
1581 }
1582
1583 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1584 {
1585 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1586 struct ath9k_11n_rate_series series[4];
1587 struct sk_buff *skb;
1588 struct ieee80211_tx_info *tx_info;
1589 struct ieee80211_tx_rate *rates;
1590 const struct ieee80211_rate *rate;
1591 struct ieee80211_hdr *hdr;
1592 int i, flags = 0;
1593 u8 rix = 0, ctsrate = 0;
1594 bool is_pspoll;
1595
1596 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1597
1598 skb = bf->bf_mpdu;
1599 tx_info = IEEE80211_SKB_CB(skb);
1600 rates = tx_info->control.rates;
1601 hdr = (struct ieee80211_hdr *)skb->data;
1602 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1603
1604 /*
1605 * We check if Short Preamble is needed for the CTS rate by
1606 * checking the BSS's global flag.
1607 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1608 */
1609 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1610 ctsrate = rate->hw_value;
1611 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1612 ctsrate |= rate->hw_value_short;
1613
1614 for (i = 0; i < 4; i++) {
1615 bool is_40, is_sgi, is_sp;
1616 int phy;
1617
1618 if (!rates[i].count || (rates[i].idx < 0))
1619 continue;
1620
1621 rix = rates[i].idx;
1622 series[i].Tries = rates[i].count;
1623
1624 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1625 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1626 flags |= ATH9K_TXDESC_RTSENA;
1627 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1628 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1629 flags |= ATH9K_TXDESC_CTSENA;
1630 }
1631
1632 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1633 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1634 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1635 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1636
1637 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1638 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1639 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1640
1641 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1642 /* MCS rates */
1643 series[i].Rate = rix | 0x80;
1644 series[i].ChSel = ath_txchainmask_reduction(sc,
1645 common->tx_chainmask, series[i].Rate);
1646 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1647 is_40, is_sgi, is_sp);
1648 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1649 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1650 continue;
1651 }
1652
1653 /* legacy rates */
1654 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1655 !(rate->flags & IEEE80211_RATE_ERP_G))
1656 phy = WLAN_RC_PHY_CCK;
1657 else
1658 phy = WLAN_RC_PHY_OFDM;
1659
1660 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1661 series[i].Rate = rate->hw_value;
1662 if (rate->hw_value_short) {
1663 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1664 series[i].Rate |= rate->hw_value_short;
1665 } else {
1666 is_sp = false;
1667 }
1668
1669 if (bf->bf_state.bfs_paprd)
1670 series[i].ChSel = common->tx_chainmask;
1671 else
1672 series[i].ChSel = ath_txchainmask_reduction(sc,
1673 common->tx_chainmask, series[i].Rate);
1674
1675 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1676 phy, rate->bitrate * 100, len, rix, is_sp);
1677 }
1678
1679 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1680 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1681 flags &= ~ATH9K_TXDESC_RTSENA;
1682
1683 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1684 if (flags & ATH9K_TXDESC_RTSENA)
1685 flags &= ~ATH9K_TXDESC_CTSENA;
1686
1687 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1688 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1689 bf->bf_lastbf->bf_desc,
1690 !is_pspoll, ctsrate,
1691 0, series, 4, flags);
1692
1693 }
1694
1695 static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1696 struct ath_txq *txq,
1697 struct sk_buff *skb)
1698 {
1699 struct ath_softc *sc = hw->priv;
1700 struct ath_hw *ah = sc->sc_ah;
1701 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1702 struct ath_frame_info *fi = get_frame_info(skb);
1703 struct ath_buf *bf;
1704 struct ath_desc *ds;
1705 int frm_type;
1706
1707 bf = ath_tx_get_buffer(sc);
1708 if (!bf) {
1709 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1710 return NULL;
1711 }
1712
1713 ATH_TXBUF_RESET(bf);
1714
1715 bf->bf_flags = setup_tx_flags(skb);
1716 bf->bf_mpdu = skb;
1717
1718 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1719 skb->len, DMA_TO_DEVICE);
1720 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1721 bf->bf_mpdu = NULL;
1722 bf->bf_buf_addr = 0;
1723 ath_err(ath9k_hw_common(sc->sc_ah),
1724 "dma_mapping_error() on TX\n");
1725 ath_tx_return_buffer(sc, bf);
1726 return NULL;
1727 }
1728
1729 frm_type = get_hw_packet_type(skb);
1730
1731 ds = bf->bf_desc;
1732 ath9k_hw_set_desc_link(ah, ds, 0);
1733
1734 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1735 fi->keyix, fi->keytype, bf->bf_flags);
1736
1737 ath9k_hw_filltxdesc(ah, ds,
1738 skb->len, /* segment length */
1739 true, /* first segment */
1740 true, /* last segment */
1741 ds, /* first descriptor */
1742 bf->bf_buf_addr,
1743 txq->axq_qnum);
1744
1745
1746 return bf;
1747 }
1748
1749 /* FIXME: tx power */
1750 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1751 struct ath_tx_control *txctl)
1752 {
1753 struct sk_buff *skb = bf->bf_mpdu;
1754 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1755 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1756 struct list_head bf_head;
1757 struct ath_atx_tid *tid = NULL;
1758 u8 tidno;
1759
1760 spin_lock_bh(&txctl->txq->axq_lock);
1761 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1762 ieee80211_is_data_qos(hdr->frame_control)) {
1763 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1764 IEEE80211_QOS_CTL_TID_MASK;
1765 tid = ATH_AN_2_TID(txctl->an, tidno);
1766
1767 WARN_ON(tid->ac->txq != txctl->txq);
1768 }
1769
1770 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1771 /*
1772 * Try aggregation if it's a unicast data frame
1773 * and the destination is HT capable.
1774 */
1775 ath_tx_send_ampdu(sc, tid, bf, txctl);
1776 } else {
1777 INIT_LIST_HEAD(&bf_head);
1778 list_add_tail(&bf->list, &bf_head);
1779
1780 bf->bf_state.bfs_ftype = txctl->frame_type;
1781 bf->bf_state.bfs_paprd = txctl->paprd;
1782
1783 if (bf->bf_state.bfs_paprd)
1784 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1785 bf->bf_state.bfs_paprd);
1786
1787 if (txctl->paprd)
1788 bf->bf_state.bfs_paprd_timestamp = jiffies;
1789
1790 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1791 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
1792
1793 ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
1794 }
1795
1796 spin_unlock_bh(&txctl->txq->axq_lock);
1797 }
1798
1799 /* Upon failure caller should free skb */
1800 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1801 struct ath_tx_control *txctl)
1802 {
1803 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1804 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1805 struct ieee80211_sta *sta = info->control.sta;
1806 struct ieee80211_vif *vif = info->control.vif;
1807 struct ath_softc *sc = hw->priv;
1808 struct ath_txq *txq = txctl->txq;
1809 struct ath_buf *bf;
1810 int padpos, padsize;
1811 int frmlen = skb->len + FCS_LEN;
1812 int q;
1813
1814 /* NOTE: sta can be NULL according to net/mac80211.h */
1815 if (sta)
1816 txctl->an = (struct ath_node *)sta->drv_priv;
1817
1818 if (info->control.hw_key)
1819 frmlen += info->control.hw_key->icv_len;
1820
1821 /*
1822 * As a temporary workaround, assign seq# here; this will likely need
1823 * to be cleaned up to work better with Beacon transmission and virtual
1824 * BSSes.
1825 */
1826 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1827 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1828 sc->tx.seq_no += 0x10;
1829 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1830 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1831 }
1832
1833 /* Add the padding after the header if this is not already done */
1834 padpos = ath9k_cmn_padpos(hdr->frame_control);
1835 padsize = padpos & 3;
1836 if (padsize && skb->len > padpos) {
1837 if (skb_headroom(skb) < padsize)
1838 return -ENOMEM;
1839
1840 skb_push(skb, padsize);
1841 memmove(skb->data, skb->data + padsize, padpos);
1842 }
1843
1844 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1845 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1846 !ieee80211_is_data(hdr->frame_control))
1847 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1848
1849 setup_frame_info(hw, skb, frmlen);
1850
1851 /*
1852 * At this point, the vif, hw_key and sta pointers in the tx control
1853 * info are no longer valid (overwritten by the ath_frame_info data.
1854 */
1855
1856 bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
1857 if (unlikely(!bf))
1858 return -ENOMEM;
1859
1860 q = skb_get_queue_mapping(skb);
1861 spin_lock_bh(&txq->axq_lock);
1862 if (txq == sc->tx.txq_map[q] &&
1863 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1864 ieee80211_stop_queue(sc->hw, q);
1865 txq->stopped = 1;
1866 }
1867 spin_unlock_bh(&txq->axq_lock);
1868
1869 ath_tx_start_dma(sc, bf, txctl);
1870
1871 return 0;
1872 }
1873
1874 /*****************/
1875 /* TX Completion */
1876 /*****************/
1877
1878 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1879 int tx_flags, int ftype, struct ath_txq *txq)
1880 {
1881 struct ieee80211_hw *hw = sc->hw;
1882 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1883 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1884 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1885 int q, padpos, padsize;
1886
1887 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1888
1889 if (tx_flags & ATH_TX_BAR)
1890 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1891
1892 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1893 /* Frame was ACKed */
1894 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1895 }
1896
1897 padpos = ath9k_cmn_padpos(hdr->frame_control);
1898 padsize = padpos & 3;
1899 if (padsize && skb->len>padpos+padsize) {
1900 /*
1901 * Remove MAC header padding before giving the frame back to
1902 * mac80211.
1903 */
1904 memmove(skb->data + padsize, skb->data, padpos);
1905 skb_pull(skb, padsize);
1906 }
1907
1908 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1909 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1910 ath_dbg(common, ATH_DBG_PS,
1911 "Going back to sleep after having received TX status (0x%lx)\n",
1912 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1913 PS_WAIT_FOR_CAB |
1914 PS_WAIT_FOR_PSPOLL_DATA |
1915 PS_WAIT_FOR_TX_ACK));
1916 }
1917
1918 q = skb_get_queue_mapping(skb);
1919 if (txq == sc->tx.txq_map[q]) {
1920 spin_lock_bh(&txq->axq_lock);
1921 if (WARN_ON(--txq->pending_frames < 0))
1922 txq->pending_frames = 0;
1923
1924 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1925 ieee80211_wake_queue(sc->hw, q);
1926 txq->stopped = 0;
1927 }
1928 spin_unlock_bh(&txq->axq_lock);
1929 }
1930
1931 ieee80211_tx_status(hw, skb);
1932 }
1933
1934 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1935 struct ath_txq *txq, struct list_head *bf_q,
1936 struct ath_tx_status *ts, int txok, int sendbar)
1937 {
1938 struct sk_buff *skb = bf->bf_mpdu;
1939 unsigned long flags;
1940 int tx_flags = 0;
1941
1942 if (sendbar)
1943 tx_flags = ATH_TX_BAR;
1944
1945 if (!txok) {
1946 tx_flags |= ATH_TX_ERROR;
1947
1948 if (bf_isxretried(bf))
1949 tx_flags |= ATH_TX_XRETRY;
1950 }
1951
1952 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1953 bf->bf_buf_addr = 0;
1954
1955 if (bf->bf_state.bfs_paprd) {
1956 if (time_after(jiffies,
1957 bf->bf_state.bfs_paprd_timestamp +
1958 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
1959 dev_kfree_skb_any(skb);
1960 else
1961 complete(&sc->paprd_complete);
1962 } else {
1963 ath_debug_stat_tx(sc, bf, ts, txq);
1964 ath_tx_complete(sc, skb, tx_flags,
1965 bf->bf_state.bfs_ftype, txq);
1966 }
1967 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
1968 * accidentally reference it later.
1969 */
1970 bf->bf_mpdu = NULL;
1971
1972 /*
1973 * Return the list of ath_buf of this mpdu to free queue
1974 */
1975 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1976 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1977 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1978 }
1979
1980 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
1981 struct ath_tx_status *ts, int nframes, int nbad,
1982 int txok, bool update_rc)
1983 {
1984 struct sk_buff *skb = bf->bf_mpdu;
1985 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1986 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1987 struct ieee80211_hw *hw = sc->hw;
1988 struct ath_hw *ah = sc->sc_ah;
1989 u8 i, tx_rateindex;
1990
1991 if (txok)
1992 tx_info->status.ack_signal = ts->ts_rssi;
1993
1994 tx_rateindex = ts->ts_rateindex;
1995 WARN_ON(tx_rateindex >= hw->max_rates);
1996
1997 if (ts->ts_status & ATH9K_TXERR_FILT)
1998 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1999 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
2000 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2001
2002 BUG_ON(nbad > nframes);
2003
2004 tx_info->status.ampdu_len = nframes;
2005 tx_info->status.ampdu_ack_len = nframes - nbad;
2006 }
2007
2008 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2009 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
2010 /*
2011 * If an underrun error is seen assume it as an excessive
2012 * retry only if max frame trigger level has been reached
2013 * (2 KB for single stream, and 4 KB for dual stream).
2014 * Adjust the long retry as if the frame was tried
2015 * hw->max_rate_tries times to affect how rate control updates
2016 * PER for the failed rate.
2017 * In case of congestion on the bus penalizing this type of
2018 * underruns should help hardware actually transmit new frames
2019 * successfully by eventually preferring slower rates.
2020 * This itself should also alleviate congestion on the bus.
2021 */
2022 if (ieee80211_is_data(hdr->frame_control) &&
2023 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2024 ATH9K_TX_DELIM_UNDERRUN)) &&
2025 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2026 tx_info->status.rates[tx_rateindex].count =
2027 hw->max_rate_tries;
2028 }
2029
2030 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2031 tx_info->status.rates[i].count = 0;
2032 tx_info->status.rates[i].idx = -1;
2033 }
2034
2035 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2036 }
2037
2038 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2039 struct ath_tx_status *ts, struct ath_buf *bf,
2040 struct list_head *bf_head)
2041 {
2042 int txok;
2043
2044 txq->axq_depth--;
2045 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2046 txq->axq_tx_inprogress = false;
2047 if (bf_is_ampdu_not_probing(bf))
2048 txq->axq_ampdu_depth--;
2049
2050 spin_unlock_bh(&txq->axq_lock);
2051
2052 if (!bf_isampdu(bf)) {
2053 /*
2054 * This frame is sent out as a single frame.
2055 * Use hardware retry status for this frame.
2056 */
2057 if (ts->ts_status & ATH9K_TXERR_XRETRY)
2058 bf->bf_state.bf_type |= BUF_XRETRY;
2059 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok, true);
2060 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2061 } else
2062 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2063
2064 spin_lock_bh(&txq->axq_lock);
2065
2066 if (sc->sc_flags & SC_OP_TXAGGR)
2067 ath_txq_schedule(sc, txq);
2068 }
2069
2070 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2071 {
2072 struct ath_hw *ah = sc->sc_ah;
2073 struct ath_common *common = ath9k_hw_common(ah);
2074 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2075 struct list_head bf_head;
2076 struct ath_desc *ds;
2077 struct ath_tx_status ts;
2078 int status;
2079
2080 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2081 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2082 txq->axq_link);
2083
2084 spin_lock_bh(&txq->axq_lock);
2085 for (;;) {
2086 if (list_empty(&txq->axq_q)) {
2087 txq->axq_link = NULL;
2088 if (sc->sc_flags & SC_OP_TXAGGR)
2089 ath_txq_schedule(sc, txq);
2090 break;
2091 }
2092 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2093
2094 /*
2095 * There is a race condition that a BH gets scheduled
2096 * after sw writes TxE and before hw re-load the last
2097 * descriptor to get the newly chained one.
2098 * Software must keep the last DONE descriptor as a
2099 * holding descriptor - software does so by marking
2100 * it with the STALE flag.
2101 */
2102 bf_held = NULL;
2103 if (bf->bf_stale) {
2104 bf_held = bf;
2105 if (list_is_last(&bf_held->list, &txq->axq_q))
2106 break;
2107
2108 bf = list_entry(bf_held->list.next, struct ath_buf,
2109 list);
2110 }
2111
2112 lastbf = bf->bf_lastbf;
2113 ds = lastbf->bf_desc;
2114
2115 memset(&ts, 0, sizeof(ts));
2116 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2117 if (status == -EINPROGRESS)
2118 break;
2119
2120 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2121
2122 /*
2123 * Remove ath_buf's of the same transmit unit from txq,
2124 * however leave the last descriptor back as the holding
2125 * descriptor for hw.
2126 */
2127 lastbf->bf_stale = true;
2128 INIT_LIST_HEAD(&bf_head);
2129 if (!list_is_singular(&lastbf->list))
2130 list_cut_position(&bf_head,
2131 &txq->axq_q, lastbf->list.prev);
2132
2133 if (bf_held) {
2134 list_del(&bf_held->list);
2135 ath_tx_return_buffer(sc, bf_held);
2136 }
2137
2138 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2139 }
2140 spin_unlock_bh(&txq->axq_lock);
2141 }
2142
2143 static void ath_tx_complete_poll_work(struct work_struct *work)
2144 {
2145 struct ath_softc *sc = container_of(work, struct ath_softc,
2146 tx_complete_work.work);
2147 struct ath_txq *txq;
2148 int i;
2149 bool needreset = false;
2150 #ifdef CONFIG_ATH9K_DEBUGFS
2151 sc->tx_complete_poll_work_seen++;
2152 #endif
2153
2154 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2155 if (ATH_TXQ_SETUP(sc, i)) {
2156 txq = &sc->tx.txq[i];
2157 spin_lock_bh(&txq->axq_lock);
2158 if (txq->axq_depth) {
2159 if (txq->axq_tx_inprogress) {
2160 needreset = true;
2161 spin_unlock_bh(&txq->axq_lock);
2162 break;
2163 } else {
2164 txq->axq_tx_inprogress = true;
2165 }
2166 }
2167 spin_unlock_bh(&txq->axq_lock);
2168 }
2169
2170 if (needreset) {
2171 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2172 "tx hung, resetting the chip\n");
2173 ath_reset(sc, true);
2174 }
2175
2176 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2177 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2178 }
2179
2180
2181
2182 void ath_tx_tasklet(struct ath_softc *sc)
2183 {
2184 int i;
2185 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2186
2187 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2188
2189 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2190 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2191 ath_tx_processq(sc, &sc->tx.txq[i]);
2192 }
2193 }
2194
2195 void ath_tx_edma_tasklet(struct ath_softc *sc)
2196 {
2197 struct ath_tx_status ts;
2198 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2199 struct ath_hw *ah = sc->sc_ah;
2200 struct ath_txq *txq;
2201 struct ath_buf *bf, *lastbf;
2202 struct list_head bf_head;
2203 int status;
2204
2205 for (;;) {
2206 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2207 if (status == -EINPROGRESS)
2208 break;
2209 if (status == -EIO) {
2210 ath_dbg(common, ATH_DBG_XMIT,
2211 "Error processing tx status\n");
2212 break;
2213 }
2214
2215 /* Skip beacon completions */
2216 if (ts.qid == sc->beacon.beaconq)
2217 continue;
2218
2219 txq = &sc->tx.txq[ts.qid];
2220
2221 spin_lock_bh(&txq->axq_lock);
2222
2223 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2224 spin_unlock_bh(&txq->axq_lock);
2225 return;
2226 }
2227
2228 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2229 struct ath_buf, list);
2230 lastbf = bf->bf_lastbf;
2231
2232 INIT_LIST_HEAD(&bf_head);
2233 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2234 &lastbf->list);
2235
2236 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2237 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2238
2239 if (!list_empty(&txq->axq_q)) {
2240 struct list_head bf_q;
2241
2242 INIT_LIST_HEAD(&bf_q);
2243 txq->axq_link = NULL;
2244 list_splice_tail_init(&txq->axq_q, &bf_q);
2245 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2246 }
2247 }
2248
2249 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2250 spin_unlock_bh(&txq->axq_lock);
2251 }
2252 }
2253
2254 /*****************/
2255 /* Init, Cleanup */
2256 /*****************/
2257
2258 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2259 {
2260 struct ath_descdma *dd = &sc->txsdma;
2261 u8 txs_len = sc->sc_ah->caps.txs_len;
2262
2263 dd->dd_desc_len = size * txs_len;
2264 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2265 &dd->dd_desc_paddr, GFP_KERNEL);
2266 if (!dd->dd_desc)
2267 return -ENOMEM;
2268
2269 return 0;
2270 }
2271
2272 static int ath_tx_edma_init(struct ath_softc *sc)
2273 {
2274 int err;
2275
2276 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2277 if (!err)
2278 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2279 sc->txsdma.dd_desc_paddr,
2280 ATH_TXSTATUS_RING_SIZE);
2281
2282 return err;
2283 }
2284
2285 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2286 {
2287 struct ath_descdma *dd = &sc->txsdma;
2288
2289 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2290 dd->dd_desc_paddr);
2291 }
2292
2293 int ath_tx_init(struct ath_softc *sc, int nbufs)
2294 {
2295 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2296 int error = 0;
2297
2298 spin_lock_init(&sc->tx.txbuflock);
2299
2300 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2301 "tx", nbufs, 1, 1);
2302 if (error != 0) {
2303 ath_err(common,
2304 "Failed to allocate tx descriptors: %d\n", error);
2305 goto err;
2306 }
2307
2308 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2309 "beacon", ATH_BCBUF, 1, 1);
2310 if (error != 0) {
2311 ath_err(common,
2312 "Failed to allocate beacon descriptors: %d\n", error);
2313 goto err;
2314 }
2315
2316 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2317
2318 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2319 error = ath_tx_edma_init(sc);
2320 if (error)
2321 goto err;
2322 }
2323
2324 err:
2325 if (error != 0)
2326 ath_tx_cleanup(sc);
2327
2328 return error;
2329 }
2330
2331 void ath_tx_cleanup(struct ath_softc *sc)
2332 {
2333 if (sc->beacon.bdma.dd_desc_len != 0)
2334 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2335
2336 if (sc->tx.txdma.dd_desc_len != 0)
2337 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2338
2339 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2340 ath_tx_edma_cleanup(sc);
2341 }
2342
2343 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2344 {
2345 struct ath_atx_tid *tid;
2346 struct ath_atx_ac *ac;
2347 int tidno, acno;
2348
2349 for (tidno = 0, tid = &an->tid[tidno];
2350 tidno < WME_NUM_TID;
2351 tidno++, tid++) {
2352 tid->an = an;
2353 tid->tidno = tidno;
2354 tid->seq_start = tid->seq_next = 0;
2355 tid->baw_size = WME_MAX_BA;
2356 tid->baw_head = tid->baw_tail = 0;
2357 tid->sched = false;
2358 tid->paused = false;
2359 tid->state &= ~AGGR_CLEANUP;
2360 INIT_LIST_HEAD(&tid->buf_q);
2361 acno = TID_TO_WME_AC(tidno);
2362 tid->ac = &an->ac[acno];
2363 tid->state &= ~AGGR_ADDBA_COMPLETE;
2364 tid->state &= ~AGGR_ADDBA_PROGRESS;
2365 }
2366
2367 for (acno = 0, ac = &an->ac[acno];
2368 acno < WME_NUM_AC; acno++, ac++) {
2369 ac->sched = false;
2370 ac->txq = sc->tx.txq_map[acno];
2371 INIT_LIST_HEAD(&ac->tid_q);
2372 }
2373 }
2374
2375 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2376 {
2377 struct ath_atx_ac *ac;
2378 struct ath_atx_tid *tid;
2379 struct ath_txq *txq;
2380 int tidno;
2381
2382 for (tidno = 0, tid = &an->tid[tidno];
2383 tidno < WME_NUM_TID; tidno++, tid++) {
2384
2385 ac = tid->ac;
2386 txq = ac->txq;
2387
2388 spin_lock_bh(&txq->axq_lock);
2389
2390 if (tid->sched) {
2391 list_del(&tid->list);
2392 tid->sched = false;
2393 }
2394
2395 if (ac->sched) {
2396 list_del(&ac->list);
2397 tid->ac->sched = false;
2398 }
2399
2400 ath_tid_drain(sc, txq, tid);
2401 tid->state &= ~AGGR_ADDBA_COMPLETE;
2402 tid->state &= ~AGGR_CLEANUP;
2403
2404 spin_unlock_bh(&txq->axq_lock);
2405 }
2406 }
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