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ALSA: opl3: Hardening for potential Spectre v1
[linux-stable.git] / drivers / rtc / rtc-sh.c
blob6c2d3989f967baff96625ab39d0d19336b002def
1 /*
2 * SuperH On-Chip RTC Support
3 *
4 * Copyright (C) 2006 - 2009 Paul Mundt
5 * Copyright (C) 2006 Jamie Lenehan
6 * Copyright (C) 2008 Angelo Castello
7 *
8 * Based on the old arch/sh/kernel/cpu/rtc.c by:
9 *
10 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
11 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 */
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/bcd.h>
20 #include <linux/rtc.h>
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/seq_file.h>
24 #include <linux/interrupt.h>
25 #include <linux/spinlock.h>
26 #include <linux/io.h>
27 #include <linux/log2.h>
28 #include <linux/clk.h>
29 #include <linux/slab.h>
30 #ifdef CONFIG_SUPERH
31 #include <asm/rtc.h>
32 #else
33 /* Default values for RZ/A RTC */
34 #define rtc_reg_size sizeof(u16)
35 #define RTC_BIT_INVERTED 0 /* no chip bugs */
36 #define RTC_CAP_4_DIGIT_YEAR (1 << 0)
37 #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
38 #endif
39
40 #define DRV_NAME "sh-rtc"
41
42 #define RTC_REG(r) ((r) * rtc_reg_size)
43
44 #define R64CNT RTC_REG(0)
45
46 #define RSECCNT RTC_REG(1) /* RTC sec */
47 #define RMINCNT RTC_REG(2) /* RTC min */
48 #define RHRCNT RTC_REG(3) /* RTC hour */
49 #define RWKCNT RTC_REG(4) /* RTC week */
50 #define RDAYCNT RTC_REG(5) /* RTC day */
51 #define RMONCNT RTC_REG(6) /* RTC month */
52 #define RYRCNT RTC_REG(7) /* RTC year */
53 #define RSECAR RTC_REG(8) /* ALARM sec */
54 #define RMINAR RTC_REG(9) /* ALARM min */
55 #define RHRAR RTC_REG(10) /* ALARM hour */
56 #define RWKAR RTC_REG(11) /* ALARM week */
57 #define RDAYAR RTC_REG(12) /* ALARM day */
58 #define RMONAR RTC_REG(13) /* ALARM month */
59 #define RCR1 RTC_REG(14) /* Control */
60 #define RCR2 RTC_REG(15) /* Control */
61
62 /*
63 * Note on RYRAR and RCR3: Up until this point most of the register
64 * definitions are consistent across all of the available parts. However,
65 * the placement of the optional RYRAR and RCR3 (the RYRAR control
66 * register used to control RYRCNT/RYRAR compare) varies considerably
67 * across various parts, occasionally being mapped in to a completely
68 * unrelated address space. For proper RYRAR support a separate resource
69 * would have to be handed off, but as this is purely optional in
70 * practice, we simply opt not to support it, thereby keeping the code
71 * quite a bit more simplified.
72 */
73
74 /* ALARM Bits - or with BCD encoded value */
75 #define AR_ENB 0x80 /* Enable for alarm cmp */
76
77 /* Period Bits */
78 #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
79 #define PF_COUNT 0x200 /* Half periodic counter */
80 #define PF_OXS 0x400 /* Periodic One x Second */
81 #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */
82 #define PF_MASK 0xf00
83
84 /* RCR1 Bits */
85 #define RCR1_CF 0x80 /* Carry Flag */
86 #define RCR1_CIE 0x10 /* Carry Interrupt Enable */
87 #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
88 #define RCR1_AF 0x01 /* Alarm Flag */
89
90 /* RCR2 Bits */
91 #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
92 #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
93 #define RCR2_RTCEN 0x08 /* ENable RTC */
94 #define RCR2_ADJ 0x04 /* ADJustment (30-second) */
95 #define RCR2_RESET 0x02 /* Reset bit */
96 #define RCR2_START 0x01 /* Start bit */
97
98 struct sh_rtc {
99 void __iomem *regbase;
100 unsigned long regsize;
101 struct resource *res;
102 int alarm_irq;
103 int periodic_irq;
104 int carry_irq;
105 struct clk *clk;
106 struct rtc_device *rtc_dev;
107 spinlock_t lock;
108 unsigned long capabilities; /* See asm/rtc.h for cap bits */
109 unsigned short periodic_freq;
110 };
111
112 static int __sh_rtc_interrupt(struct sh_rtc *rtc)
113 {
114 unsigned int tmp, pending;
115
116 tmp = readb(rtc->regbase + RCR1);
117 pending = tmp & RCR1_CF;
118 tmp &= ~RCR1_CF;
119 writeb(tmp, rtc->regbase + RCR1);
120
121 /* Users have requested One x Second IRQ */
122 if (pending && rtc->periodic_freq & PF_OXS)
123 rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
124
125 return pending;
126 }
127
128 static int __sh_rtc_alarm(struct sh_rtc *rtc)
129 {
130 unsigned int tmp, pending;
131
132 tmp = readb(rtc->regbase + RCR1);
133 pending = tmp & RCR1_AF;
134 tmp &= ~(RCR1_AF | RCR1_AIE);
135 writeb(tmp, rtc->regbase + RCR1);
136
137 if (pending)
138 rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
139
140 return pending;
141 }
142
143 static int __sh_rtc_periodic(struct sh_rtc *rtc)
144 {
145 struct rtc_device *rtc_dev = rtc->rtc_dev;
146 struct rtc_task *irq_task;
147 unsigned int tmp, pending;
148
149 tmp = readb(rtc->regbase + RCR2);
150 pending = tmp & RCR2_PEF;
151 tmp &= ~RCR2_PEF;
152 writeb(tmp, rtc->regbase + RCR2);
153
154 if (!pending)
155 return 0;
156
157 /* Half period enabled than one skipped and the next notified */
158 if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
159 rtc->periodic_freq &= ~PF_COUNT;
160 else {
161 if (rtc->periodic_freq & PF_HP)
162 rtc->periodic_freq |= PF_COUNT;
163 if (rtc->periodic_freq & PF_KOU) {
164 spin_lock(&rtc_dev->irq_task_lock);
165 irq_task = rtc_dev->irq_task;
166 if (irq_task)
167 irq_task->func(irq_task->private_data);
168 spin_unlock(&rtc_dev->irq_task_lock);
169 } else
170 rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
171 }
172
173 return pending;
174 }
175
176 static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
177 {
178 struct sh_rtc *rtc = dev_id;
179 int ret;
180
181 spin_lock(&rtc->lock);
182 ret = __sh_rtc_interrupt(rtc);
183 spin_unlock(&rtc->lock);
184
185 return IRQ_RETVAL(ret);
186 }
187
188 static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
189 {
190 struct sh_rtc *rtc = dev_id;
191 int ret;
192
193 spin_lock(&rtc->lock);
194 ret = __sh_rtc_alarm(rtc);
195 spin_unlock(&rtc->lock);
196
197 return IRQ_RETVAL(ret);
198 }
199
200 static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
201 {
202 struct sh_rtc *rtc = dev_id;
203 int ret;
204
205 spin_lock(&rtc->lock);
206 ret = __sh_rtc_periodic(rtc);
207 spin_unlock(&rtc->lock);
208
209 return IRQ_RETVAL(ret);
210 }
211
212 static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
213 {
214 struct sh_rtc *rtc = dev_id;
215 int ret;
216
217 spin_lock(&rtc->lock);
218 ret = __sh_rtc_interrupt(rtc);
219 ret |= __sh_rtc_alarm(rtc);
220 ret |= __sh_rtc_periodic(rtc);
221 spin_unlock(&rtc->lock);
222
223 return IRQ_RETVAL(ret);
224 }
225
226 static int sh_rtc_irq_set_state(struct device *dev, int enable)
227 {
228 struct sh_rtc *rtc = dev_get_drvdata(dev);
229 unsigned int tmp;
230
231 spin_lock_irq(&rtc->lock);
232
233 tmp = readb(rtc->regbase + RCR2);
234
235 if (enable) {
236 rtc->periodic_freq |= PF_KOU;
237 tmp &= ~RCR2_PEF; /* Clear PES bit */
238 tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */
239 } else {
240 rtc->periodic_freq &= ~PF_KOU;
241 tmp &= ~(RCR2_PESMASK | RCR2_PEF);
242 }
243
244 writeb(tmp, rtc->regbase + RCR2);
245
246 spin_unlock_irq(&rtc->lock);
247
248 return 0;
249 }
250
251 static int sh_rtc_irq_set_freq(struct device *dev, int freq)
252 {
253 struct sh_rtc *rtc = dev_get_drvdata(dev);
254 int tmp, ret = 0;
255
256 spin_lock_irq(&rtc->lock);
257 tmp = rtc->periodic_freq & PF_MASK;
258
259 switch (freq) {
260 case 0:
261 rtc->periodic_freq = 0x00;
262 break;
263 case 1:
264 rtc->periodic_freq = 0x60;
265 break;
266 case 2:
267 rtc->periodic_freq = 0x50;
268 break;
269 case 4:
270 rtc->periodic_freq = 0x40;
271 break;
272 case 8:
273 rtc->periodic_freq = 0x30 | PF_HP;
274 break;
275 case 16:
276 rtc->periodic_freq = 0x30;
277 break;
278 case 32:
279 rtc->periodic_freq = 0x20 | PF_HP;
280 break;
281 case 64:
282 rtc->periodic_freq = 0x20;
283 break;
284 case 128:
285 rtc->periodic_freq = 0x10 | PF_HP;
286 break;
287 case 256:
288 rtc->periodic_freq = 0x10;
289 break;
290 default:
291 ret = -ENOTSUPP;
292 }
293
294 if (ret == 0)
295 rtc->periodic_freq |= tmp;
296
297 spin_unlock_irq(&rtc->lock);
298 return ret;
299 }
300
301 static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
302 {
303 struct sh_rtc *rtc = dev_get_drvdata(dev);
304 unsigned int tmp;
305
306 spin_lock_irq(&rtc->lock);
307
308 tmp = readb(rtc->regbase + RCR1);
309
310 if (enable)
311 tmp |= RCR1_AIE;
312 else
313 tmp &= ~RCR1_AIE;
314
315 writeb(tmp, rtc->regbase + RCR1);
316
317 spin_unlock_irq(&rtc->lock);
318 }
319
320 static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
321 {
322 struct sh_rtc *rtc = dev_get_drvdata(dev);
323 unsigned int tmp;
324
325 tmp = readb(rtc->regbase + RCR1);
326 seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
327
328 tmp = readb(rtc->regbase + RCR2);
329 seq_printf(seq, "periodic_IRQ\t: %s\n",
330 (tmp & RCR2_PESMASK) ? "yes" : "no");
331
332 return 0;
333 }
334
335 static inline void sh_rtc_setcie(struct device *dev, unsigned int enable)
336 {
337 struct sh_rtc *rtc = dev_get_drvdata(dev);
338 unsigned int tmp;
339
340 spin_lock_irq(&rtc->lock);
341
342 tmp = readb(rtc->regbase + RCR1);
343
344 if (!enable)
345 tmp &= ~RCR1_CIE;
346 else
347 tmp |= RCR1_CIE;
348
349 writeb(tmp, rtc->regbase + RCR1);
350
351 spin_unlock_irq(&rtc->lock);
352 }
353
354 static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
355 {
356 sh_rtc_setaie(dev, enabled);
357 return 0;
358 }
359
360 static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
361 {
362 struct platform_device *pdev = to_platform_device(dev);
363 struct sh_rtc *rtc = platform_get_drvdata(pdev);
364 unsigned int sec128, sec2, yr, yr100, cf_bit;
365
366 do {
367 unsigned int tmp;
368
369 spin_lock_irq(&rtc->lock);
370
371 tmp = readb(rtc->regbase + RCR1);
372 tmp &= ~RCR1_CF; /* Clear CF-bit */
373 tmp |= RCR1_CIE;
374 writeb(tmp, rtc->regbase + RCR1);
375
376 sec128 = readb(rtc->regbase + R64CNT);
377
378 tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT));
379 tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT));
380 tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT));
381 tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT));
382 tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT));
383 tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1;
384
385 if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
386 yr = readw(rtc->regbase + RYRCNT);
387 yr100 = bcd2bin(yr >> 8);
388 yr &= 0xff;
389 } else {
390 yr = readb(rtc->regbase + RYRCNT);
391 yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20);
392 }
393
394 tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900;
395
396 sec2 = readb(rtc->regbase + R64CNT);
397 cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
398
399 spin_unlock_irq(&rtc->lock);
400 } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);
401
402 #if RTC_BIT_INVERTED != 0
403 if ((sec128 & RTC_BIT_INVERTED))
404 tm->tm_sec--;
405 #endif
406
407 /* only keep the carry interrupt enabled if UIE is on */
408 if (!(rtc->periodic_freq & PF_OXS))
409 sh_rtc_setcie(dev, 0);
410
411 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
412 "mday=%d, mon=%d, year=%d, wday=%d\n",
413 __func__,
414 tm->tm_sec, tm->tm_min, tm->tm_hour,
415 tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
416
417 return rtc_valid_tm(tm);
418 }
419
420 static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
421 {
422 struct platform_device *pdev = to_platform_device(dev);
423 struct sh_rtc *rtc = platform_get_drvdata(pdev);
424 unsigned int tmp;
425 int year;
426
427 spin_lock_irq(&rtc->lock);
428
429 /* Reset pre-scaler & stop RTC */
430 tmp = readb(rtc->regbase + RCR2);
431 tmp |= RCR2_RESET;
432 tmp &= ~RCR2_START;
433 writeb(tmp, rtc->regbase + RCR2);
434
435 writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT);
436 writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT);
437 writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT);
438 writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT);
439 writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT);
440 writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT);
441
442 if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
443 year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) |
444 bin2bcd(tm->tm_year % 100);
445 writew(year, rtc->regbase + RYRCNT);
446 } else {
447 year = tm->tm_year % 100;
448 writeb(bin2bcd(year), rtc->regbase + RYRCNT);
449 }
450
451 /* Start RTC */
452 tmp = readb(rtc->regbase + RCR2);
453 tmp &= ~RCR2_RESET;
454 tmp |= RCR2_RTCEN | RCR2_START;
455 writeb(tmp, rtc->regbase + RCR2);
456
457 spin_unlock_irq(&rtc->lock);
458
459 return 0;
460 }
461
462 static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
463 {
464 unsigned int byte;
465 int value = 0xff; /* return 0xff for ignored values */
466
467 byte = readb(rtc->regbase + reg_off);
468 if (byte & AR_ENB) {
469 byte &= ~AR_ENB; /* strip the enable bit */
470 value = bcd2bin(byte);
471 }
472
473 return value;
474 }
475
476 static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
477 {
478 struct platform_device *pdev = to_platform_device(dev);
479 struct sh_rtc *rtc = platform_get_drvdata(pdev);
480 struct rtc_time *tm = &wkalrm->time;
481
482 spin_lock_irq(&rtc->lock);
483
484 tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR);
485 tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR);
486 tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR);
487 tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR);
488 tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR);
489 tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR);
490 if (tm->tm_mon > 0)
491 tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
492
493 wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0;
494
495 spin_unlock_irq(&rtc->lock);
496
497 return 0;
498 }
499
500 static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
501 int value, int reg_off)
502 {
503 /* < 0 for a value that is ignored */
504 if (value < 0)
505 writeb(0, rtc->regbase + reg_off);
506 else
507 writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off);
508 }
509
510 static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
511 {
512 struct platform_device *pdev = to_platform_device(dev);
513 struct sh_rtc *rtc = platform_get_drvdata(pdev);
514 unsigned int rcr1;
515 struct rtc_time *tm = &wkalrm->time;
516 int mon;
517
518 spin_lock_irq(&rtc->lock);
519
520 /* disable alarm interrupt and clear the alarm flag */
521 rcr1 = readb(rtc->regbase + RCR1);
522 rcr1 &= ~(RCR1_AF | RCR1_AIE);
523 writeb(rcr1, rtc->regbase + RCR1);
524
525 /* set alarm time */
526 sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR);
527 sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR);
528 sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR);
529 sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR);
530 sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR);
531 mon = tm->tm_mon;
532 if (mon >= 0)
533 mon += 1;
534 sh_rtc_write_alarm_value(rtc, mon, RMONAR);
535
536 if (wkalrm->enabled) {
537 rcr1 |= RCR1_AIE;
538 writeb(rcr1, rtc->regbase + RCR1);
539 }
540
541 spin_unlock_irq(&rtc->lock);
542
543 return 0;
544 }
545
546 static const struct rtc_class_ops sh_rtc_ops = {
547 .read_time = sh_rtc_read_time,
548 .set_time = sh_rtc_set_time,
549 .read_alarm = sh_rtc_read_alarm,
550 .set_alarm = sh_rtc_set_alarm,
551 .proc = sh_rtc_proc,
552 .alarm_irq_enable = sh_rtc_alarm_irq_enable,
553 };
554
555 static int __init sh_rtc_probe(struct platform_device *pdev)
556 {
557 struct sh_rtc *rtc;
558 struct resource *res;
559 struct rtc_time r;
560 char clk_name[6];
561 int clk_id, ret;
562
563 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
564 if (unlikely(!rtc))
565 return -ENOMEM;
566
567 spin_lock_init(&rtc->lock);
568
569 /* get periodic/carry/alarm irqs */
570 ret = platform_get_irq(pdev, 0);
571 if (unlikely(ret <= 0)) {
572 dev_err(&pdev->dev, "No IRQ resource\n");
573 return -ENOENT;
574 }
575
576 rtc->periodic_irq = ret;
577 rtc->carry_irq = platform_get_irq(pdev, 1);
578 rtc->alarm_irq = platform_get_irq(pdev, 2);
579
580 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
581 if (!res)
582 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
583 if (unlikely(res == NULL)) {
584 dev_err(&pdev->dev, "No IO resource\n");
585 return -ENOENT;
586 }
587
588 rtc->regsize = resource_size(res);
589
590 rtc->res = devm_request_mem_region(&pdev->dev, res->start,
591 rtc->regsize, pdev->name);
592 if (unlikely(!rtc->res))
593 return -EBUSY;
594
595 rtc->regbase = devm_ioremap_nocache(&pdev->dev, rtc->res->start,
596 rtc->regsize);
597 if (unlikely(!rtc->regbase))
598 return -EINVAL;
599
600 if (!pdev->dev.of_node) {
601 clk_id = pdev->id;
602 /* With a single device, the clock id is still "rtc0" */
603 if (clk_id < 0)
604 clk_id = 0;
605
606 snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id);
607 } else
608 snprintf(clk_name, sizeof(clk_name), "fck");
609
610 rtc->clk = devm_clk_get(&pdev->dev, clk_name);
611 if (IS_ERR(rtc->clk)) {
612 /*
613 * No error handling for rtc->clk intentionally, not all
614 * platforms will have a unique clock for the RTC, and
615 * the clk API can handle the struct clk pointer being
616 * NULL.
617 */
618 rtc->clk = NULL;
619 }
620
621 clk_enable(rtc->clk);
622
623 rtc->capabilities = RTC_DEF_CAPABILITIES;
624
625 #ifdef CONFIG_SUPERH
626 if (dev_get_platdata(&pdev->dev)) {
627 struct sh_rtc_platform_info *pinfo =
628 dev_get_platdata(&pdev->dev);
629
630 /*
631 * Some CPUs have special capabilities in addition to the
632 * default set. Add those in here.
633 */
634 rtc->capabilities |= pinfo->capabilities;
635 }
636 #endif
637
638 if (rtc->carry_irq <= 0) {
639 /* register shared periodic/carry/alarm irq */
640 ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
641 sh_rtc_shared, 0, "sh-rtc", rtc);
642 if (unlikely(ret)) {
643 dev_err(&pdev->dev,
644 "request IRQ failed with %d, IRQ %d\n", ret,
645 rtc->periodic_irq);
646 goto err_unmap;
647 }
648 } else {
649 /* register periodic/carry/alarm irqs */
650 ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
651 sh_rtc_periodic, 0, "sh-rtc period", rtc);
652 if (unlikely(ret)) {
653 dev_err(&pdev->dev,
654 "request period IRQ failed with %d, IRQ %d\n",
655 ret, rtc->periodic_irq);
656 goto err_unmap;
657 }
658
659 ret = devm_request_irq(&pdev->dev, rtc->carry_irq,
660 sh_rtc_interrupt, 0, "sh-rtc carry", rtc);
661 if (unlikely(ret)) {
662 dev_err(&pdev->dev,
663 "request carry IRQ failed with %d, IRQ %d\n",
664 ret, rtc->carry_irq);
665 goto err_unmap;
666 }
667
668 ret = devm_request_irq(&pdev->dev, rtc->alarm_irq,
669 sh_rtc_alarm, 0, "sh-rtc alarm", rtc);
670 if (unlikely(ret)) {
671 dev_err(&pdev->dev,
672 "request alarm IRQ failed with %d, IRQ %d\n",
673 ret, rtc->alarm_irq);
674 goto err_unmap;
675 }
676 }
677
678 platform_set_drvdata(pdev, rtc);
679
680 /* everything disabled by default */
681 sh_rtc_irq_set_freq(&pdev->dev, 0);
682 sh_rtc_irq_set_state(&pdev->dev, 0);
683 sh_rtc_setaie(&pdev->dev, 0);
684 sh_rtc_setcie(&pdev->dev, 0);
685
686 rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, "sh",
687 &sh_rtc_ops, THIS_MODULE);
688 if (IS_ERR(rtc->rtc_dev)) {
689 ret = PTR_ERR(rtc->rtc_dev);
690 goto err_unmap;
691 }
692
693 rtc->rtc_dev->max_user_freq = 256;
694
695 /* reset rtc to epoch 0 if time is invalid */
696 if (rtc_read_time(rtc->rtc_dev, &r) < 0) {
697 rtc_time_to_tm(0, &r);
698 rtc_set_time(rtc->rtc_dev, &r);
699 }
700
701 device_init_wakeup(&pdev->dev, 1);
702 return 0;
703
704 err_unmap:
705 clk_disable(rtc->clk);
706
707 return ret;
708 }
709
710 static int __exit sh_rtc_remove(struct platform_device *pdev)
711 {
712 struct sh_rtc *rtc = platform_get_drvdata(pdev);
713
714 sh_rtc_irq_set_state(&pdev->dev, 0);
715
716 sh_rtc_setaie(&pdev->dev, 0);
717 sh_rtc_setcie(&pdev->dev, 0);
718
719 clk_disable(rtc->clk);
720
721 return 0;
722 }
723
724 static void sh_rtc_set_irq_wake(struct device *dev, int enabled)
725 {
726 struct platform_device *pdev = to_platform_device(dev);
727 struct sh_rtc *rtc = platform_get_drvdata(pdev);
728
729 irq_set_irq_wake(rtc->periodic_irq, enabled);
730
731 if (rtc->carry_irq > 0) {
732 irq_set_irq_wake(rtc->carry_irq, enabled);
733 irq_set_irq_wake(rtc->alarm_irq, enabled);
734 }
735 }
736
737 static int __maybe_unused sh_rtc_suspend(struct device *dev)
738 {
739 if (device_may_wakeup(dev))
740 sh_rtc_set_irq_wake(dev, 1);
741
742 return 0;
743 }
744
745 static int __maybe_unused sh_rtc_resume(struct device *dev)
746 {
747 if (device_may_wakeup(dev))
748 sh_rtc_set_irq_wake(dev, 0);
749
750 return 0;
751 }
752
753 static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume);
754
755 static const struct of_device_id sh_rtc_of_match[] = {
756 { .compatible = "renesas,sh-rtc", },
757 { /* sentinel */ }
758 };
759 MODULE_DEVICE_TABLE(of, sh_rtc_of_match);
760
761 static struct platform_driver sh_rtc_platform_driver = {
762 .driver = {
763 .name = DRV_NAME,
764 .pm = &sh_rtc_pm_ops,
765 .of_match_table = sh_rtc_of_match,
766 },
767 .remove = __exit_p(sh_rtc_remove),
768 };
769
770 module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe);
771
772 MODULE_DESCRIPTION("SuperH on-chip RTC driver");
773 MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
774 "Jamie Lenehan <lenehan@twibble.org>, "
775 "Angelo Castello <angelo.castello@st.com>");
776 MODULE_LICENSE("GPL");
777 MODULE_ALIAS("platform:" DRV_NAME);
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