drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/mfd/syscon.h>
  13 #include <linux/regmap.h>
  14 #include <drm/drm_of.h>
  15 #include <drm/drmP.h>
  16 #include <drm/drm_crtc_helper.h>
  17 #include <drm/drm_edid.h>
  18 #include <drm/bridge/dw_hdmi.h>
  19
  20 #include "rockchip_drm_drv.h"
  21 #include "rockchip_drm_vop.h"
  22
  23 #define GRF_SOC_CON6                    0x025c
  24 #define HDMI_SEL_VOP_LIT                (1 << 4)
  25
  26 struct rockchip_hdmi {
  27         struct device *dev;
  28         struct regmap *regmap;
  29         struct drm_encoder encoder;
  30 };
  31
  32 #define to_rockchip_hdmi(x)     container_of(x, struct rockchip_hdmi, x)
  33
  34 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
  35         {
  36                 27000000, {
  37                         { 0x00b3, 0x0000},
  38                         { 0x2153, 0x0000},
  39                         { 0x40f3, 0x0000}
  40                 },
  41         }, {
  42                 36000000, {
  43                         { 0x00b3, 0x0000},
  44                         { 0x2153, 0x0000},
  45                         { 0x40f3, 0x0000}
  46                 },
  47         }, {
  48                 40000000, {
  49                         { 0x00b3, 0x0000},
  50                         { 0x2153, 0x0000},
  51                         { 0x40f3, 0x0000}
  52                 },
  53         }, {
  54                 54000000, {
  55                         { 0x0072, 0x0001},
  56                         { 0x2142, 0x0001},
  57                         { 0x40a2, 0x0001},
  58                 },
  59         }, {
  60                 65000000, {
  61                         { 0x0072, 0x0001},
  62                         { 0x2142, 0x0001},
  63                         { 0x40a2, 0x0001},
  64                 },
  65         }, {
  66                 66000000, {
  67                         { 0x013e, 0x0003},
  68                         { 0x217e, 0x0002},
  69                         { 0x4061, 0x0002}
  70                 },
  71         }, {
  72                 74250000, {
  73                         { 0x0072, 0x0001},
  74                         { 0x2145, 0x0002},
  75                         { 0x4061, 0x0002}
  76                 },
  77         }, {
  78                 83500000, {
  79                         { 0x0072, 0x0001},
  80                 },
  81         }, {
  82                 108000000, {
  83                         { 0x0051, 0x0002},
  84                         { 0x2145, 0x0002},
  85                         { 0x4061, 0x0002}
  86                 },
  87         }, {
  88                 106500000, {
  89                         { 0x0051, 0x0002},
  90                         { 0x2145, 0x0002},
  91                         { 0x4061, 0x0002}
  92                 },
  93         }, {
  94                 146250000, {
  95                         { 0x0051, 0x0002},
  96                         { 0x2145, 0x0002},
  97                         { 0x4061, 0x0002}
  98                 },
  99         }, {
 100                 148500000, {
 101                         { 0x0051, 0x0003},
 102                         { 0x214c, 0x0003},
 103                         { 0x4064, 0x0003}
 104                 },
 105         }, {
 106                 ~0UL, {
 107                         { 0x00a0, 0x000a },
 108                         { 0x2001, 0x000f },
 109                         { 0x4002, 0x000f },
 110                 },
 111         }
 112 };
 113
 114 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
 115         /*      pixelclk    bpp8    bpp10   bpp12 */
 116         {
 117                 40000000,  { 0x0018, 0x0018, 0x0018 },
 118         }, {
 119                 65000000,  { 0x0028, 0x0028, 0x0028 },
 120         }, {
 121                 66000000,  { 0x0038, 0x0038, 0x0038 },
 122         }, {
 123                 74250000,  { 0x0028, 0x0038, 0x0038 },
 124         }, {
 125                 83500000,  { 0x0028, 0x0038, 0x0038 },
 126         }, {
 127                 146250000, { 0x0038, 0x0038, 0x0038 },
 128         }, {
 129                 148500000, { 0x0000, 0x0038, 0x0038 },
 130         }, {
 131                 ~0UL,      { 0x0000, 0x0000, 0x0000},
 132         }
 133 };
 134
 135 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
 136         /*pixelclk   symbol   term   vlev*/
 137         { 74250000,  0x8009, 0x0004, 0x0272},
 138         { 148500000, 0x802b, 0x0004, 0x028d},
 139         { 297000000, 0x8039, 0x0005, 0x028d},
 140         { ~0UL,      0x0000, 0x0000, 0x0000}
 141 };
 142
 143 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
 144 {
 145         struct device_node *np = hdmi->dev->of_node;
 146
 147         hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 148         if (IS_ERR(hdmi->regmap)) {
 149                 dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
 150                 return PTR_ERR(hdmi->regmap);
 151         }
 152
 153         return 0;
 154 }
 155
 156 static enum drm_mode_status
 157 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
 158                             const struct drm_display_mode *mode)
 159 {
 160         const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
 161         int pclk = mode->clock * 1000;
 162         bool valid = false;
 163         int i;
 164
 165         for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
 166                 if (pclk == mpll_cfg[i].mpixelclock) {
 167                         valid = true;
 168                         break;
 169                 }
 170         }
 171
 172         return (valid) ? MODE_OK : MODE_BAD;
 173 }
 174
 175 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
 176         .destroy = drm_encoder_cleanup,
 177 };
 178
 179 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
 180 {
 181 }
 182
 183 static bool
 184 dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
 185                                     const struct drm_display_mode *mode,
 186                                     struct drm_display_mode *adj_mode)
 187 {
 188         return true;
 189 }
 190
 191 static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
 192                                               struct drm_display_mode *mode,
 193                                               struct drm_display_mode *adj_mode)
 194 {
 195 }
 196
 197 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
 198 {
 199         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 200         u32 val;
 201         int mux;
 202
 203         mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
 204         if (mux)
 205                 val = HDMI_SEL_VOP_LIT | (HDMI_SEL_VOP_LIT << 16);
 206         else
 207                 val = HDMI_SEL_VOP_LIT << 16;
 208
 209         regmap_write(hdmi->regmap, GRF_SOC_CON6, val);
 210         dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
 211                 (mux) ? "LIT" : "BIG");
 212 }
 213
 214 static int
 215 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
 216                                       struct drm_crtc_state *crtc_state,
 217                                       struct drm_connector_state *conn_state)
 218 {
 219         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 220
 221         s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
 222         s->output_type = DRM_MODE_CONNECTOR_HDMIA;
 223
 224         return 0;
 225 }
 226
 227 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
 228         .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
 229         .mode_set   = dw_hdmi_rockchip_encoder_mode_set,
 230         .enable     = dw_hdmi_rockchip_encoder_enable,
 231         .disable    = dw_hdmi_rockchip_encoder_disable,
 232         .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
 233 };
 234
 235 static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = {
 236         .mode_valid = dw_hdmi_rockchip_mode_valid,
 237         .mpll_cfg   = rockchip_mpll_cfg,
 238         .cur_ctr    = rockchip_cur_ctr,
 239         .phy_config = rockchip_phy_config,
 240 };
 241
 242 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
 243         { .compatible = "rockchip,rk3288-dw-hdmi",
 244           .data = &rockchip_hdmi_drv_data
 245         },
 246         {},
 247 };
 248 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
 249
 250 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 251                                  void *data)
 252 {
 253         struct platform_device *pdev = to_platform_device(dev);
 254         const struct dw_hdmi_plat_data *plat_data;
 255         const struct of_device_id *match;
 256         struct drm_device *drm = data;
 257         struct drm_encoder *encoder;
 258         struct rockchip_hdmi *hdmi;
 259         int ret;
 260
 261         if (!pdev->dev.of_node)
 262                 return -ENODEV;
 263
 264         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
 265         if (!hdmi)
 266                 return -ENOMEM;
 267
 268         match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
 269         plat_data = match->data;
 270         hdmi->dev = &pdev->dev;
 271         encoder = &hdmi->encoder;
 272
 273         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
 274         /*
 275          * If we failed to find the CRTC(s) which this encoder is
 276          * supposed to be connected to, it's because the CRTC has
 277          * not been registered yet.  Defer probing, and hope that
 278          * the required CRTC is added later.
 279          */
 280         if (encoder->possible_crtcs == 0)
 281                 return -EPROBE_DEFER;
 282
 283         ret = rockchip_hdmi_parse_dt(hdmi);
 284         if (ret) {
 285                 dev_err(hdmi->dev, "Unable to parse OF data\n");
 286                 return ret;
 287         }
 288
 289         drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
 290         drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
 291                          DRM_MODE_ENCODER_TMDS, NULL);
 292
 293         ret = dw_hdmi_bind(pdev, encoder, plat_data);
 294
 295         /*
 296          * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
 297          * which would have called the encoder cleanup.  Do it manually.
 298          */
 299         if (ret)
 300                 drm_encoder_cleanup(encoder);
 301
 302         return ret;
 303 }
 304
 305 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
 306                                     void *data)
 307 {
 308         return dw_hdmi_unbind(dev);
 309 }
 310
 311 static const struct component_ops dw_hdmi_rockchip_ops = {
 312         .bind   = dw_hdmi_rockchip_bind,
 313         .unbind = dw_hdmi_rockchip_unbind,
 314 };
 315
 316 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
 317 {
 318         return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
 319 }
 320
 321 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
 322 {
 323         component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
 324
 325         return 0;
 326 }
 327
 328 struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
 329         .probe  = dw_hdmi_rockchip_probe,
 330         .remove = dw_hdmi_rockchip_remove,
 331         .driver = {
 332                 .name = "dwhdmi-rockchip",
 333                 .of_match_table = dw_hdmi_rockchip_dt_ids,
 334         },
 335 };