1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
5 * Copyright (C) 2016 Linaro Ltd
6 * Copyright (C) 2014 Sony Mobile Communications AB
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/firmware.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
18 #include <linux/of_reserved_mem.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/firmware/qcom/qcom_scm.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/remoteproc.h>
25 #include <linux/soc/qcom/mdt_loader.h>
26 #include <linux/soc/qcom/smem.h>
27 #include <linux/soc/qcom/smem_state.h>
29 #include "qcom_common.h"
30 #include "remoteproc_internal.h"
31 #include "qcom_pil_info.h"
32 #include "qcom_wcnss.h"
34 #define WCNSS_CRASH_REASON_SMEM 422
35 #define WCNSS_FIRMWARE_NAME "wcnss.mdt"
36 #define WCNSS_PAS_ID 6
37 #define WCNSS_SSCTL_ID 0x13
39 #define WCNSS_SPARE_NVBIN_DLND BIT(25)
41 #define WCNSS_PMU_IRIS_XO_CFG BIT(3)
42 #define WCNSS_PMU_IRIS_XO_EN BIT(4)
43 #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5)
44 #define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */
46 #define WCNSS_PMU_IRIS_RESET BIT(7)
47 #define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */
48 #define WCNSS_PMU_IRIS_XO_READ BIT(9)
49 #define WCNSS_PMU_IRIS_XO_READ_STS BIT(10)
51 #define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1)
52 #define WCNSS_PMU_XO_MODE_19p2 0
53 #define WCNSS_PMU_XO_MODE_48 3
55 #define WCNSS_MAX_PDS 2
61 const char *pd_names
[WCNSS_MAX_PDS
];
62 const struct wcnss_vreg_info
*vregs
;
63 size_t num_vregs
, num_pd_vregs
;
70 void __iomem
*pmu_cfg
;
71 void __iomem
*spare_out
;
81 struct qcom_smem_state
*state
;
84 struct mutex iris_lock
;
85 struct qcom_iris
*iris
;
87 struct device
*pds
[WCNSS_MAX_PDS
];
89 struct regulator_bulk_data
*vregs
;
92 struct completion start_done
;
93 struct completion stop_done
;
96 phys_addr_t mem_reloc
;
100 struct qcom_rproc_subdev smd_subdev
;
101 struct qcom_sysmon
*sysmon
;
104 static const struct wcnss_data riva_data
= {
106 .spare_offset
= 0xb4,
108 .vregs
= (struct wcnss_vreg_info
[]) {
109 { "vddmx", 1050000, 1150000, 0 },
110 { "vddcx", 1050000, 1150000, 0 },
111 { "vddpx", 1800000, 1800000, 0 },
116 static const struct wcnss_data pronto_v1_data
= {
117 .pmu_offset
= 0x1004,
118 .spare_offset
= 0x1088,
120 .pd_names
= { "mx", "cx" },
121 .vregs
= (struct wcnss_vreg_info
[]) {
122 { "vddmx", 950000, 1150000, 0 },
123 { "vddcx", .super_turbo
= true},
124 { "vddpx", 1800000, 1800000, 0 },
130 static const struct wcnss_data pronto_v2_data
= {
131 .pmu_offset
= 0x1004,
132 .spare_offset
= 0x1088,
134 .pd_names
= { "mx", "cx" },
135 .vregs
= (struct wcnss_vreg_info
[]) {
136 { "vddmx", 1287500, 1287500, 0 },
137 { "vddcx", .super_turbo
= true },
138 { "vddpx", 1800000, 1800000, 0 },
144 static const struct wcnss_data pronto_v3_data
= {
145 .pmu_offset
= 0x1004,
146 .spare_offset
= 0x1088,
148 .pd_names
= { "mx", "cx" },
149 .vregs
= (struct wcnss_vreg_info
[]) {
150 { "vddpx", 1800000, 1800000, 0 },
155 static int wcnss_load(struct rproc
*rproc
, const struct firmware
*fw
)
157 struct qcom_wcnss
*wcnss
= rproc
->priv
;
160 ret
= qcom_mdt_load(wcnss
->dev
, fw
, rproc
->firmware
, WCNSS_PAS_ID
,
161 wcnss
->mem_region
, wcnss
->mem_phys
,
162 wcnss
->mem_size
, &wcnss
->mem_reloc
);
166 qcom_pil_info_store("wcnss", wcnss
->mem_phys
, wcnss
->mem_size
);
171 static void wcnss_indicate_nv_download(struct qcom_wcnss
*wcnss
)
175 /* Indicate NV download capability */
176 val
= readl(wcnss
->spare_out
);
177 val
|= WCNSS_SPARE_NVBIN_DLND
;
178 writel(val
, wcnss
->spare_out
);
181 static void wcnss_configure_iris(struct qcom_wcnss
*wcnss
)
185 /* Clear PMU cfg register */
186 writel(0, wcnss
->pmu_cfg
);
188 val
= WCNSS_PMU_GC_BUS_MUX_SEL_TOP
| WCNSS_PMU_IRIS_XO_EN
;
189 writel(val
, wcnss
->pmu_cfg
);
192 val
&= ~WCNSS_PMU_XO_MODE_MASK
;
193 if (wcnss
->use_48mhz_xo
)
194 val
|= WCNSS_PMU_XO_MODE_48
<< 1;
196 val
|= WCNSS_PMU_XO_MODE_19p2
<< 1;
197 writel(val
, wcnss
->pmu_cfg
);
200 val
|= WCNSS_PMU_IRIS_RESET
;
201 writel(val
, wcnss
->pmu_cfg
);
203 /* Wait for PMU.iris_reg_reset_sts */
204 while (readl(wcnss
->pmu_cfg
) & WCNSS_PMU_IRIS_RESET_STS
)
207 /* Clear IRIS reset */
208 val
&= ~WCNSS_PMU_IRIS_RESET
;
209 writel(val
, wcnss
->pmu_cfg
);
211 /* Start IRIS XO configuration */
212 val
|= WCNSS_PMU_IRIS_XO_CFG
;
213 writel(val
, wcnss
->pmu_cfg
);
215 /* Wait for XO configuration to finish */
216 while (readl(wcnss
->pmu_cfg
) & WCNSS_PMU_IRIS_XO_CFG_STS
)
219 /* Stop IRIS XO configuration */
220 val
&= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP
;
221 val
&= ~WCNSS_PMU_IRIS_XO_CFG
;
222 writel(val
, wcnss
->pmu_cfg
);
224 /* Add some delay for XO to settle */
228 static int wcnss_start(struct rproc
*rproc
)
230 struct qcom_wcnss
*wcnss
= rproc
->priv
;
233 mutex_lock(&wcnss
->iris_lock
);
235 dev_err(wcnss
->dev
, "no iris registered\n");
237 goto release_iris_lock
;
240 for (i
= 0; i
< wcnss
->num_pds
; i
++) {
241 dev_pm_genpd_set_performance_state(wcnss
->pds
[i
], INT_MAX
);
242 ret
= pm_runtime_get_sync(wcnss
->pds
[i
]);
244 pm_runtime_put_noidle(wcnss
->pds
[i
]);
249 ret
= regulator_bulk_enable(wcnss
->num_vregs
, wcnss
->vregs
);
253 ret
= qcom_iris_enable(wcnss
->iris
);
255 goto disable_regulators
;
257 wcnss_indicate_nv_download(wcnss
);
258 wcnss_configure_iris(wcnss
);
260 ret
= qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID
);
263 "failed to authenticate image and release reset\n");
267 ret
= wait_for_completion_timeout(&wcnss
->start_done
,
268 msecs_to_jiffies(5000));
269 if (wcnss
->ready_irq
> 0 && ret
== 0) {
270 /* We have a ready_irq, but it didn't fire in time. */
271 dev_err(wcnss
->dev
, "start timed out\n");
272 qcom_scm_pas_shutdown(WCNSS_PAS_ID
);
280 qcom_iris_disable(wcnss
->iris
);
282 regulator_bulk_disable(wcnss
->num_vregs
, wcnss
->vregs
);
284 for (i
--; i
>= 0; i
--) {
285 pm_runtime_put(wcnss
->pds
[i
]);
286 dev_pm_genpd_set_performance_state(wcnss
->pds
[i
], 0);
289 mutex_unlock(&wcnss
->iris_lock
);
294 static int wcnss_stop(struct rproc
*rproc
)
296 struct qcom_wcnss
*wcnss
= rproc
->priv
;
300 qcom_smem_state_update_bits(wcnss
->state
,
301 BIT(wcnss
->stop_bit
),
302 BIT(wcnss
->stop_bit
));
304 ret
= wait_for_completion_timeout(&wcnss
->stop_done
,
305 msecs_to_jiffies(5000));
307 dev_err(wcnss
->dev
, "timed out on wait\n");
309 qcom_smem_state_update_bits(wcnss
->state
,
310 BIT(wcnss
->stop_bit
),
314 ret
= qcom_scm_pas_shutdown(WCNSS_PAS_ID
);
316 dev_err(wcnss
->dev
, "failed to shutdown: %d\n", ret
);
321 static void *wcnss_da_to_va(struct rproc
*rproc
, u64 da
, size_t len
, bool *is_iomem
)
323 struct qcom_wcnss
*wcnss
= rproc
->priv
;
326 offset
= da
- wcnss
->mem_reloc
;
327 if (offset
< 0 || offset
+ len
> wcnss
->mem_size
)
330 return wcnss
->mem_region
+ offset
;
333 static const struct rproc_ops wcnss_ops
= {
334 .start
= wcnss_start
,
336 .da_to_va
= wcnss_da_to_va
,
337 .parse_fw
= qcom_register_dump_segments
,
341 static irqreturn_t
wcnss_wdog_interrupt(int irq
, void *dev
)
343 struct qcom_wcnss
*wcnss
= dev
;
345 rproc_report_crash(wcnss
->rproc
, RPROC_WATCHDOG
);
350 static irqreturn_t
wcnss_fatal_interrupt(int irq
, void *dev
)
352 struct qcom_wcnss
*wcnss
= dev
;
356 msg
= qcom_smem_get(QCOM_SMEM_HOST_ANY
, WCNSS_CRASH_REASON_SMEM
, &len
);
357 if (!IS_ERR(msg
) && len
> 0 && msg
[0])
358 dev_err(wcnss
->dev
, "fatal error received: %s\n", msg
);
360 rproc_report_crash(wcnss
->rproc
, RPROC_FATAL_ERROR
);
365 static irqreturn_t
wcnss_ready_interrupt(int irq
, void *dev
)
367 struct qcom_wcnss
*wcnss
= dev
;
369 complete(&wcnss
->start_done
);
374 static irqreturn_t
wcnss_handover_interrupt(int irq
, void *dev
)
377 * XXX: At this point we're supposed to release the resources that we
378 * have been holding on behalf of the WCNSS. Unfortunately this
379 * interrupt comes way before the other side seems to be done.
381 * So we're currently relying on the ready interrupt firing later then
382 * this and we just disable the resources at the end of wcnss_start().
388 static irqreturn_t
wcnss_stop_ack_interrupt(int irq
, void *dev
)
390 struct qcom_wcnss
*wcnss
= dev
;
392 complete(&wcnss
->stop_done
);
397 static int wcnss_init_pds(struct qcom_wcnss
*wcnss
,
398 const char * const pd_names
[WCNSS_MAX_PDS
])
402 for (i
= 0; i
< WCNSS_MAX_PDS
; i
++) {
406 wcnss
->pds
[i
] = dev_pm_domain_attach_by_name(wcnss
->dev
, pd_names
[i
]);
407 if (IS_ERR_OR_NULL(wcnss
->pds
[i
])) {
408 ret
= PTR_ERR(wcnss
->pds
[i
]) ? : -ENODATA
;
409 for (i
--; i
>= 0; i
--)
410 dev_pm_domain_detach(wcnss
->pds
[i
], false);
419 static void wcnss_release_pds(struct qcom_wcnss
*wcnss
)
423 for (i
= 0; i
< wcnss
->num_pds
; i
++)
424 dev_pm_domain_detach(wcnss
->pds
[i
], false);
427 static int wcnss_init_regulators(struct qcom_wcnss
*wcnss
,
428 const struct wcnss_vreg_info
*info
,
429 int num_vregs
, int num_pd_vregs
)
431 struct regulator_bulk_data
*bulk
;
436 * If attaching the power domains suceeded we can skip requesting
437 * the regulators for the power domains. For old device trees we need to
438 * reserve extra space to manage them through the regulator interface.
441 info
+= num_pd_vregs
;
443 num_vregs
+= num_pd_vregs
;
445 bulk
= devm_kcalloc(wcnss
->dev
,
446 num_vregs
, sizeof(struct regulator_bulk_data
),
451 for (i
= 0; i
< num_vregs
; i
++)
452 bulk
[i
].supply
= info
[i
].name
;
454 ret
= devm_regulator_bulk_get(wcnss
->dev
, num_vregs
, bulk
);
458 for (i
= 0; i
< num_vregs
; i
++) {
459 if (info
[i
].max_voltage
)
460 regulator_set_voltage(bulk
[i
].consumer
,
462 info
[i
].max_voltage
);
465 regulator_set_load(bulk
[i
].consumer
, info
[i
].load_uA
);
469 wcnss
->num_vregs
= num_vregs
;
474 static int wcnss_request_irq(struct qcom_wcnss
*wcnss
,
475 struct platform_device
*pdev
,
478 irq_handler_t thread_fn
)
483 ret
= platform_get_irq_byname(pdev
, name
);
484 if (ret
< 0 && optional
) {
485 dev_dbg(&pdev
->dev
, "no %s IRQ defined, ignoring\n", name
);
487 } else if (ret
< 0) {
488 dev_err(&pdev
->dev
, "no %s IRQ defined\n", name
);
494 ret
= devm_request_threaded_irq(&pdev
->dev
, ret
,
496 IRQF_TRIGGER_RISING
| IRQF_ONESHOT
,
499 dev_err(&pdev
->dev
, "request %s IRQ failed\n", name
);
503 /* Return the IRQ number if the IRQ was successfully acquired */
507 static int wcnss_alloc_memory_region(struct qcom_wcnss
*wcnss
)
509 struct reserved_mem
*rmem
= NULL
;
510 struct device_node
*node
;
512 node
= of_parse_phandle(wcnss
->dev
->of_node
, "memory-region", 0);
514 rmem
= of_reserved_mem_lookup(node
);
518 dev_err(wcnss
->dev
, "unable to resolve memory-region\n");
522 wcnss
->mem_phys
= wcnss
->mem_reloc
= rmem
->base
;
523 wcnss
->mem_size
= rmem
->size
;
524 wcnss
->mem_region
= devm_ioremap_wc(wcnss
->dev
, wcnss
->mem_phys
, wcnss
->mem_size
);
525 if (!wcnss
->mem_region
) {
526 dev_err(wcnss
->dev
, "unable to map memory region: %pa+%zx\n",
527 &rmem
->base
, wcnss
->mem_size
);
534 static int wcnss_probe(struct platform_device
*pdev
)
536 const char *fw_name
= WCNSS_FIRMWARE_NAME
;
537 const struct wcnss_data
*data
;
538 struct qcom_wcnss
*wcnss
;
543 data
= of_device_get_match_data(&pdev
->dev
);
545 if (!qcom_scm_is_available())
546 return -EPROBE_DEFER
;
548 if (!qcom_scm_pas_supported(WCNSS_PAS_ID
)) {
549 dev_err(&pdev
->dev
, "PAS is not available for WCNSS\n");
553 ret
= of_property_read_string(pdev
->dev
.of_node
, "firmware-name",
555 if (ret
< 0 && ret
!= -EINVAL
)
558 rproc
= devm_rproc_alloc(&pdev
->dev
, pdev
->name
, &wcnss_ops
,
559 fw_name
, sizeof(*wcnss
));
561 dev_err(&pdev
->dev
, "unable to allocate remoteproc\n");
564 rproc_coredump_set_elf_info(rproc
, ELFCLASS32
, EM_NONE
);
567 wcnss
->dev
= &pdev
->dev
;
568 wcnss
->rproc
= rproc
;
569 platform_set_drvdata(pdev
, wcnss
);
571 init_completion(&wcnss
->start_done
);
572 init_completion(&wcnss
->stop_done
);
574 mutex_init(&wcnss
->iris_lock
);
576 mmio
= devm_platform_ioremap_resource_byname(pdev
, "pmu");
578 return PTR_ERR(mmio
);
580 ret
= wcnss_alloc_memory_region(wcnss
);
584 wcnss
->pmu_cfg
= mmio
+ data
->pmu_offset
;
585 wcnss
->spare_out
= mmio
+ data
->spare_offset
;
588 * We might need to fallback to regulators instead of power domains
589 * for old device trees. Don't report an error in that case.
591 ret
= wcnss_init_pds(wcnss
, data
->pd_names
);
592 if (ret
&& (ret
!= -ENODATA
|| !data
->num_pd_vregs
))
595 ret
= wcnss_init_regulators(wcnss
, data
->vregs
, data
->num_vregs
,
600 ret
= wcnss_request_irq(wcnss
, pdev
, "wdog", false, wcnss_wdog_interrupt
);
603 wcnss
->wdog_irq
= ret
;
605 ret
= wcnss_request_irq(wcnss
, pdev
, "fatal", false, wcnss_fatal_interrupt
);
608 wcnss
->fatal_irq
= ret
;
610 ret
= wcnss_request_irq(wcnss
, pdev
, "ready", true, wcnss_ready_interrupt
);
613 wcnss
->ready_irq
= ret
;
615 ret
= wcnss_request_irq(wcnss
, pdev
, "handover", true, wcnss_handover_interrupt
);
618 wcnss
->handover_irq
= ret
;
620 ret
= wcnss_request_irq(wcnss
, pdev
, "stop-ack", true, wcnss_stop_ack_interrupt
);
623 wcnss
->stop_ack_irq
= ret
;
625 if (wcnss
->stop_ack_irq
) {
626 wcnss
->state
= devm_qcom_smem_state_get(&pdev
->dev
, "stop",
628 if (IS_ERR(wcnss
->state
)) {
629 ret
= PTR_ERR(wcnss
->state
);
634 qcom_add_smd_subdev(rproc
, &wcnss
->smd_subdev
);
635 wcnss
->sysmon
= qcom_add_sysmon_subdev(rproc
, "wcnss", WCNSS_SSCTL_ID
);
636 if (IS_ERR(wcnss
->sysmon
)) {
637 ret
= PTR_ERR(wcnss
->sysmon
);
641 wcnss
->iris
= qcom_iris_probe(&pdev
->dev
, &wcnss
->use_48mhz_xo
);
642 if (IS_ERR(wcnss
->iris
)) {
643 ret
= PTR_ERR(wcnss
->iris
);
647 ret
= rproc_add(rproc
);
654 qcom_iris_remove(wcnss
->iris
);
656 wcnss_release_pds(wcnss
);
661 static void wcnss_remove(struct platform_device
*pdev
)
663 struct qcom_wcnss
*wcnss
= platform_get_drvdata(pdev
);
665 qcom_iris_remove(wcnss
->iris
);
667 rproc_del(wcnss
->rproc
);
669 qcom_remove_sysmon_subdev(wcnss
->sysmon
);
670 qcom_remove_smd_subdev(wcnss
->rproc
, &wcnss
->smd_subdev
);
671 wcnss_release_pds(wcnss
);
674 static const struct of_device_id wcnss_of_match
[] = {
675 { .compatible
= "qcom,riva-pil", &riva_data
},
676 { .compatible
= "qcom,pronto-v1-pil", &pronto_v1_data
},
677 { .compatible
= "qcom,pronto-v2-pil", &pronto_v2_data
},
678 { .compatible
= "qcom,pronto-v3-pil", &pronto_v3_data
},
681 MODULE_DEVICE_TABLE(of
, wcnss_of_match
);
683 static struct platform_driver wcnss_driver
= {
684 .probe
= wcnss_probe
,
685 .remove_new
= wcnss_remove
,
687 .name
= "qcom-wcnss-pil",
688 .of_match_table
= wcnss_of_match
,
692 module_platform_driver(wcnss_driver
);
694 MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Wireless Subsystem");
695 MODULE_LICENSE("GPL v2");