1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm ADSP/SLPI Peripheral Image Loader for MSM8974 and MSM8996
5 * Copyright (C) 2016 Linaro Ltd
6 * Copyright (C) 2014 Sony Mobile Communications AB
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/firmware.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_reserved_mem.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/firmware/qcom/qcom_scm.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/remoteproc.h>
25 #include <linux/soc/qcom/mdt_loader.h>
26 #include <linux/soc/qcom/smem.h>
27 #include <linux/soc/qcom/smem_state.h>
29 #include "qcom_common.h"
30 #include "qcom_pil_info.h"
31 #include "qcom_q6v5.h"
32 #include "remoteproc_internal.h"
34 #define ADSP_DECRYPT_SHUTDOWN_DELAY_MS 100
36 #define MAX_ASSIGN_COUNT 3
39 int crash_reason_smem
;
40 const char *firmware_name
;
41 const char *dtb_firmware_name
;
45 unsigned int minidump_id
;
47 bool decrypt_shutdown
;
49 char **proxy_pd_names
;
51 const char *load_state
;
53 const char *sysmon_name
;
55 unsigned int smem_host_id
;
57 int region_assign_idx
;
58 int region_assign_count
;
59 bool region_assign_shared
;
60 int region_assign_vmid
;
67 struct qcom_q6v5 q6v5
;
70 struct clk
*aggre2_clk
;
72 struct regulator
*cx_supply
;
73 struct regulator
*px_supply
;
75 struct device
*proxy_pds
[3];
79 const char *dtb_firmware_name
;
83 unsigned int minidump_id
;
84 int crash_reason_smem
;
85 unsigned int smem_host_id
;
86 bool decrypt_shutdown
;
87 const char *info_name
;
89 const struct firmware
*firmware
;
90 const struct firmware
*dtb_firmware
;
92 struct completion start_done
;
93 struct completion stop_done
;
96 phys_addr_t dtb_mem_phys
;
97 phys_addr_t mem_reloc
;
98 phys_addr_t dtb_mem_reloc
;
99 phys_addr_t region_assign_phys
[MAX_ASSIGN_COUNT
];
101 void *dtb_mem_region
;
104 size_t region_assign_size
[MAX_ASSIGN_COUNT
];
106 int region_assign_idx
;
107 int region_assign_count
;
108 bool region_assign_shared
;
109 int region_assign_vmid
;
110 u64 region_assign_owners
[MAX_ASSIGN_COUNT
];
112 struct qcom_rproc_glink glink_subdev
;
113 struct qcom_rproc_subdev smd_subdev
;
114 struct qcom_rproc_pdm pdm_subdev
;
115 struct qcom_rproc_ssr ssr_subdev
;
116 struct qcom_sysmon
*sysmon
;
118 struct qcom_scm_pas_metadata pas_metadata
;
119 struct qcom_scm_pas_metadata dtb_pas_metadata
;
122 static void adsp_segment_dump(struct rproc
*rproc
, struct rproc_dump_segment
*segment
,
123 void *dest
, size_t offset
, size_t size
)
125 struct qcom_adsp
*adsp
= rproc
->priv
;
128 total_offset
= segment
->da
+ segment
->offset
+ offset
- adsp
->mem_phys
;
129 if (total_offset
< 0 || total_offset
+ size
> adsp
->mem_size
) {
131 "invalid copy request for segment %pad with offset %zu and size %zu)\n",
132 &segment
->da
, offset
, size
);
133 memset(dest
, 0xff, size
);
137 memcpy_fromio(dest
, adsp
->mem_region
+ total_offset
, size
);
140 static void adsp_minidump(struct rproc
*rproc
)
142 struct qcom_adsp
*adsp
= rproc
->priv
;
144 if (rproc
->dump_conf
== RPROC_COREDUMP_DISABLED
)
147 qcom_minidump(rproc
, adsp
->minidump_id
, adsp_segment_dump
);
150 static int adsp_pds_enable(struct qcom_adsp
*adsp
, struct device
**pds
,
156 for (i
= 0; i
< pd_count
; i
++) {
157 dev_pm_genpd_set_performance_state(pds
[i
], INT_MAX
);
158 ret
= pm_runtime_get_sync(pds
[i
]);
160 pm_runtime_put_noidle(pds
[i
]);
161 dev_pm_genpd_set_performance_state(pds
[i
], 0);
162 goto unroll_pd_votes
;
169 for (i
--; i
>= 0; i
--) {
170 dev_pm_genpd_set_performance_state(pds
[i
], 0);
171 pm_runtime_put(pds
[i
]);
177 static void adsp_pds_disable(struct qcom_adsp
*adsp
, struct device
**pds
,
182 for (i
= 0; i
< pd_count
; i
++) {
183 dev_pm_genpd_set_performance_state(pds
[i
], 0);
184 pm_runtime_put(pds
[i
]);
188 static int adsp_shutdown_poll_decrypt(struct qcom_adsp
*adsp
)
190 unsigned int retry_num
= 50;
194 msleep(ADSP_DECRYPT_SHUTDOWN_DELAY_MS
);
195 ret
= qcom_scm_pas_shutdown(adsp
->pas_id
);
196 } while (ret
== -EINVAL
&& --retry_num
);
201 static int adsp_unprepare(struct rproc
*rproc
)
203 struct qcom_adsp
*adsp
= rproc
->priv
;
206 * adsp_load() did pass pas_metadata to the SCM driver for storing
207 * metadata context. It might have been released already if
208 * auth_and_reset() was successful, but in other cases clean it up
211 qcom_scm_pas_metadata_release(&adsp
->pas_metadata
);
212 if (adsp
->dtb_pas_id
)
213 qcom_scm_pas_metadata_release(&adsp
->dtb_pas_metadata
);
218 static int adsp_load(struct rproc
*rproc
, const struct firmware
*fw
)
220 struct qcom_adsp
*adsp
= rproc
->priv
;
223 /* Store firmware handle to be used in adsp_start() */
226 if (adsp
->lite_pas_id
)
227 ret
= qcom_scm_pas_shutdown(adsp
->lite_pas_id
);
229 if (adsp
->dtb_pas_id
) {
230 ret
= request_firmware(&adsp
->dtb_firmware
, adsp
->dtb_firmware_name
, adsp
->dev
);
232 dev_err(adsp
->dev
, "request_firmware failed for %s: %d\n",
233 adsp
->dtb_firmware_name
, ret
);
237 ret
= qcom_mdt_pas_init(adsp
->dev
, adsp
->dtb_firmware
, adsp
->dtb_firmware_name
,
238 adsp
->dtb_pas_id
, adsp
->dtb_mem_phys
,
239 &adsp
->dtb_pas_metadata
);
241 goto release_dtb_firmware
;
243 ret
= qcom_mdt_load_no_init(adsp
->dev
, adsp
->dtb_firmware
, adsp
->dtb_firmware_name
,
244 adsp
->dtb_pas_id
, adsp
->dtb_mem_region
,
245 adsp
->dtb_mem_phys
, adsp
->dtb_mem_size
,
246 &adsp
->dtb_mem_reloc
);
248 goto release_dtb_metadata
;
253 release_dtb_metadata
:
254 qcom_scm_pas_metadata_release(&adsp
->dtb_pas_metadata
);
256 release_dtb_firmware
:
257 release_firmware(adsp
->dtb_firmware
);
262 static int adsp_start(struct rproc
*rproc
)
264 struct qcom_adsp
*adsp
= rproc
->priv
;
267 ret
= qcom_q6v5_prepare(&adsp
->q6v5
);
271 ret
= adsp_pds_enable(adsp
, adsp
->proxy_pds
, adsp
->proxy_pd_count
);
275 ret
= clk_prepare_enable(adsp
->xo
);
277 goto disable_proxy_pds
;
279 ret
= clk_prepare_enable(adsp
->aggre2_clk
);
283 if (adsp
->cx_supply
) {
284 ret
= regulator_enable(adsp
->cx_supply
);
286 goto disable_aggre2_clk
;
289 if (adsp
->px_supply
) {
290 ret
= regulator_enable(adsp
->px_supply
);
292 goto disable_cx_supply
;
295 if (adsp
->dtb_pas_id
) {
296 ret
= qcom_scm_pas_auth_and_reset(adsp
->dtb_pas_id
);
299 "failed to authenticate dtb image and release reset\n");
300 goto disable_px_supply
;
304 ret
= qcom_mdt_pas_init(adsp
->dev
, adsp
->firmware
, rproc
->firmware
, adsp
->pas_id
,
305 adsp
->mem_phys
, &adsp
->pas_metadata
);
307 goto disable_px_supply
;
309 ret
= qcom_mdt_load_no_init(adsp
->dev
, adsp
->firmware
, rproc
->firmware
, adsp
->pas_id
,
310 adsp
->mem_region
, adsp
->mem_phys
, adsp
->mem_size
,
313 goto release_pas_metadata
;
315 qcom_pil_info_store(adsp
->info_name
, adsp
->mem_phys
, adsp
->mem_size
);
317 ret
= qcom_scm_pas_auth_and_reset(adsp
->pas_id
);
320 "failed to authenticate image and release reset\n");
321 goto release_pas_metadata
;
324 ret
= qcom_q6v5_wait_for_start(&adsp
->q6v5
, msecs_to_jiffies(5000));
325 if (ret
== -ETIMEDOUT
) {
326 dev_err(adsp
->dev
, "start timed out\n");
327 qcom_scm_pas_shutdown(adsp
->pas_id
);
328 goto release_pas_metadata
;
331 qcom_scm_pas_metadata_release(&adsp
->pas_metadata
);
332 if (adsp
->dtb_pas_id
)
333 qcom_scm_pas_metadata_release(&adsp
->dtb_pas_metadata
);
335 /* Remove pointer to the loaded firmware, only valid in adsp_load() & adsp_start() */
336 adsp
->firmware
= NULL
;
340 release_pas_metadata
:
341 qcom_scm_pas_metadata_release(&adsp
->pas_metadata
);
342 if (adsp
->dtb_pas_id
)
343 qcom_scm_pas_metadata_release(&adsp
->dtb_pas_metadata
);
346 regulator_disable(adsp
->px_supply
);
349 regulator_disable(adsp
->cx_supply
);
351 clk_disable_unprepare(adsp
->aggre2_clk
);
353 clk_disable_unprepare(adsp
->xo
);
355 adsp_pds_disable(adsp
, adsp
->proxy_pds
, adsp
->proxy_pd_count
);
357 qcom_q6v5_unprepare(&adsp
->q6v5
);
359 /* Remove pointer to the loaded firmware, only valid in adsp_load() & adsp_start() */
360 adsp
->firmware
= NULL
;
365 static void qcom_pas_handover(struct qcom_q6v5
*q6v5
)
367 struct qcom_adsp
*adsp
= container_of(q6v5
, struct qcom_adsp
, q6v5
);
370 regulator_disable(adsp
->px_supply
);
372 regulator_disable(adsp
->cx_supply
);
373 clk_disable_unprepare(adsp
->aggre2_clk
);
374 clk_disable_unprepare(adsp
->xo
);
375 adsp_pds_disable(adsp
, adsp
->proxy_pds
, adsp
->proxy_pd_count
);
378 static int adsp_stop(struct rproc
*rproc
)
380 struct qcom_adsp
*adsp
= rproc
->priv
;
384 ret
= qcom_q6v5_request_stop(&adsp
->q6v5
, adsp
->sysmon
);
385 if (ret
== -ETIMEDOUT
)
386 dev_err(adsp
->dev
, "timed out on wait\n");
388 ret
= qcom_scm_pas_shutdown(adsp
->pas_id
);
389 if (ret
&& adsp
->decrypt_shutdown
)
390 ret
= adsp_shutdown_poll_decrypt(adsp
);
393 dev_err(adsp
->dev
, "failed to shutdown: %d\n", ret
);
395 if (adsp
->dtb_pas_id
) {
396 ret
= qcom_scm_pas_shutdown(adsp
->dtb_pas_id
);
398 dev_err(adsp
->dev
, "failed to shutdown dtb: %d\n", ret
);
401 handover
= qcom_q6v5_unprepare(&adsp
->q6v5
);
403 qcom_pas_handover(&adsp
->q6v5
);
405 if (adsp
->smem_host_id
)
406 ret
= qcom_smem_bust_hwspin_lock_by_host(adsp
->smem_host_id
);
411 static void *adsp_da_to_va(struct rproc
*rproc
, u64 da
, size_t len
, bool *is_iomem
)
413 struct qcom_adsp
*adsp
= rproc
->priv
;
416 offset
= da
- adsp
->mem_reloc
;
417 if (offset
< 0 || offset
+ len
> adsp
->mem_size
)
423 return adsp
->mem_region
+ offset
;
426 static unsigned long adsp_panic(struct rproc
*rproc
)
428 struct qcom_adsp
*adsp
= rproc
->priv
;
430 return qcom_q6v5_panic(&adsp
->q6v5
);
433 static const struct rproc_ops adsp_ops
= {
434 .unprepare
= adsp_unprepare
,
437 .da_to_va
= adsp_da_to_va
,
438 .parse_fw
= qcom_register_dump_segments
,
443 static const struct rproc_ops adsp_minidump_ops
= {
444 .unprepare
= adsp_unprepare
,
447 .da_to_va
= adsp_da_to_va
,
448 .parse_fw
= qcom_register_dump_segments
,
451 .coredump
= adsp_minidump
,
454 static int adsp_init_clock(struct qcom_adsp
*adsp
)
458 adsp
->xo
= devm_clk_get(adsp
->dev
, "xo");
459 if (IS_ERR(adsp
->xo
)) {
460 ret
= PTR_ERR(adsp
->xo
);
461 if (ret
!= -EPROBE_DEFER
)
462 dev_err(adsp
->dev
, "failed to get xo clock");
466 adsp
->aggre2_clk
= devm_clk_get_optional(adsp
->dev
, "aggre2");
467 if (IS_ERR(adsp
->aggre2_clk
)) {
468 ret
= PTR_ERR(adsp
->aggre2_clk
);
469 if (ret
!= -EPROBE_DEFER
)
471 "failed to get aggre2 clock");
478 static int adsp_init_regulator(struct qcom_adsp
*adsp
)
480 adsp
->cx_supply
= devm_regulator_get_optional(adsp
->dev
, "cx");
481 if (IS_ERR(adsp
->cx_supply
)) {
482 if (PTR_ERR(adsp
->cx_supply
) == -ENODEV
)
483 adsp
->cx_supply
= NULL
;
485 return PTR_ERR(adsp
->cx_supply
);
489 regulator_set_load(adsp
->cx_supply
, 100000);
491 adsp
->px_supply
= devm_regulator_get_optional(adsp
->dev
, "px");
492 if (IS_ERR(adsp
->px_supply
)) {
493 if (PTR_ERR(adsp
->px_supply
) == -ENODEV
)
494 adsp
->px_supply
= NULL
;
496 return PTR_ERR(adsp
->px_supply
);
502 static int adsp_pds_attach(struct device
*dev
, struct device
**devs
,
512 /* Handle single power domain */
513 if (dev
->pm_domain
) {
515 pm_runtime_enable(dev
);
519 while (pd_names
[num_pds
])
522 for (i
= 0; i
< num_pds
; i
++) {
523 devs
[i
] = dev_pm_domain_attach_by_name(dev
, pd_names
[i
]);
524 if (IS_ERR_OR_NULL(devs
[i
])) {
525 ret
= PTR_ERR(devs
[i
]) ? : -ENODATA
;
533 for (i
--; i
>= 0; i
--)
534 dev_pm_domain_detach(devs
[i
], false);
539 static void adsp_pds_detach(struct qcom_adsp
*adsp
, struct device
**pds
,
542 struct device
*dev
= adsp
->dev
;
545 /* Handle single power domain */
546 if (dev
->pm_domain
&& pd_count
) {
547 pm_runtime_disable(dev
);
551 for (i
= 0; i
< pd_count
; i
++)
552 dev_pm_domain_detach(pds
[i
], false);
555 static int adsp_alloc_memory_region(struct qcom_adsp
*adsp
)
557 struct reserved_mem
*rmem
;
558 struct device_node
*node
;
560 node
= of_parse_phandle(adsp
->dev
->of_node
, "memory-region", 0);
562 dev_err(adsp
->dev
, "no memory-region specified\n");
566 rmem
= of_reserved_mem_lookup(node
);
569 dev_err(adsp
->dev
, "unable to resolve memory-region\n");
573 adsp
->mem_phys
= adsp
->mem_reloc
= rmem
->base
;
574 adsp
->mem_size
= rmem
->size
;
575 adsp
->mem_region
= devm_ioremap_wc(adsp
->dev
, adsp
->mem_phys
, adsp
->mem_size
);
576 if (!adsp
->mem_region
) {
577 dev_err(adsp
->dev
, "unable to map memory region: %pa+%zx\n",
578 &rmem
->base
, adsp
->mem_size
);
582 if (!adsp
->dtb_pas_id
)
585 node
= of_parse_phandle(adsp
->dev
->of_node
, "memory-region", 1);
587 dev_err(adsp
->dev
, "no dtb memory-region specified\n");
591 rmem
= of_reserved_mem_lookup(node
);
594 dev_err(adsp
->dev
, "unable to resolve dtb memory-region\n");
598 adsp
->dtb_mem_phys
= adsp
->dtb_mem_reloc
= rmem
->base
;
599 adsp
->dtb_mem_size
= rmem
->size
;
600 adsp
->dtb_mem_region
= devm_ioremap_wc(adsp
->dev
, adsp
->dtb_mem_phys
, adsp
->dtb_mem_size
);
601 if (!adsp
->dtb_mem_region
) {
602 dev_err(adsp
->dev
, "unable to map dtb memory region: %pa+%zx\n",
603 &rmem
->base
, adsp
->dtb_mem_size
);
610 static int adsp_assign_memory_region(struct qcom_adsp
*adsp
)
612 struct qcom_scm_vmperm perm
[MAX_ASSIGN_COUNT
];
613 struct device_node
*node
;
614 unsigned int perm_size
;
618 if (!adsp
->region_assign_idx
)
621 for (offset
= 0; offset
< adsp
->region_assign_count
; ++offset
) {
622 struct reserved_mem
*rmem
= NULL
;
624 node
= of_parse_phandle(adsp
->dev
->of_node
, "memory-region",
625 adsp
->region_assign_idx
+ offset
);
627 rmem
= of_reserved_mem_lookup(node
);
630 dev_err(adsp
->dev
, "unable to resolve shareable memory-region index %d\n",
635 if (adsp
->region_assign_shared
) {
636 perm
[0].vmid
= QCOM_SCM_VMID_HLOS
;
637 perm
[0].perm
= QCOM_SCM_PERM_RW
;
638 perm
[1].vmid
= adsp
->region_assign_vmid
;
639 perm
[1].perm
= QCOM_SCM_PERM_RW
;
642 perm
[0].vmid
= adsp
->region_assign_vmid
;
643 perm
[0].perm
= QCOM_SCM_PERM_RW
;
647 adsp
->region_assign_phys
[offset
] = rmem
->base
;
648 adsp
->region_assign_size
[offset
] = rmem
->size
;
649 adsp
->region_assign_owners
[offset
] = BIT(QCOM_SCM_VMID_HLOS
);
651 ret
= qcom_scm_assign_mem(adsp
->region_assign_phys
[offset
],
652 adsp
->region_assign_size
[offset
],
653 &adsp
->region_assign_owners
[offset
],
656 dev_err(adsp
->dev
, "assign memory %d failed\n", offset
);
664 static void adsp_unassign_memory_region(struct qcom_adsp
*adsp
)
666 struct qcom_scm_vmperm perm
;
670 if (!adsp
->region_assign_idx
|| adsp
->region_assign_shared
)
673 for (offset
= 0; offset
< adsp
->region_assign_count
; ++offset
) {
674 perm
.vmid
= QCOM_SCM_VMID_HLOS
;
675 perm
.perm
= QCOM_SCM_PERM_RW
;
677 ret
= qcom_scm_assign_mem(adsp
->region_assign_phys
[offset
],
678 adsp
->region_assign_size
[offset
],
679 &adsp
->region_assign_owners
[offset
],
682 dev_err(adsp
->dev
, "unassign memory %d failed\n", offset
);
686 static int adsp_probe(struct platform_device
*pdev
)
688 const struct adsp_data
*desc
;
689 struct qcom_adsp
*adsp
;
691 const char *fw_name
, *dtb_fw_name
= NULL
;
692 const struct rproc_ops
*ops
= &adsp_ops
;
695 desc
= of_device_get_match_data(&pdev
->dev
);
699 if (!qcom_scm_is_available())
700 return -EPROBE_DEFER
;
702 fw_name
= desc
->firmware_name
;
703 ret
= of_property_read_string(pdev
->dev
.of_node
, "firmware-name",
705 if (ret
< 0 && ret
!= -EINVAL
)
708 if (desc
->dtb_firmware_name
) {
709 dtb_fw_name
= desc
->dtb_firmware_name
;
710 ret
= of_property_read_string_index(pdev
->dev
.of_node
, "firmware-name", 1,
712 if (ret
< 0 && ret
!= -EINVAL
)
716 if (desc
->minidump_id
)
717 ops
= &adsp_minidump_ops
;
719 rproc
= devm_rproc_alloc(&pdev
->dev
, pdev
->name
, ops
, fw_name
, sizeof(*adsp
));
722 dev_err(&pdev
->dev
, "unable to allocate remoteproc\n");
726 rproc
->auto_boot
= desc
->auto_boot
;
727 rproc_coredump_set_elf_info(rproc
, ELFCLASS32
, EM_NONE
);
730 adsp
->dev
= &pdev
->dev
;
732 adsp
->minidump_id
= desc
->minidump_id
;
733 adsp
->pas_id
= desc
->pas_id
;
734 adsp
->lite_pas_id
= desc
->lite_pas_id
;
735 adsp
->info_name
= desc
->sysmon_name
;
736 adsp
->smem_host_id
= desc
->smem_host_id
;
737 adsp
->decrypt_shutdown
= desc
->decrypt_shutdown
;
738 adsp
->region_assign_idx
= desc
->region_assign_idx
;
739 adsp
->region_assign_count
= min_t(int, MAX_ASSIGN_COUNT
, desc
->region_assign_count
);
740 adsp
->region_assign_vmid
= desc
->region_assign_vmid
;
741 adsp
->region_assign_shared
= desc
->region_assign_shared
;
743 adsp
->dtb_firmware_name
= dtb_fw_name
;
744 adsp
->dtb_pas_id
= desc
->dtb_pas_id
;
746 platform_set_drvdata(pdev
, adsp
);
748 ret
= device_init_wakeup(adsp
->dev
, true);
752 ret
= adsp_alloc_memory_region(adsp
);
756 ret
= adsp_assign_memory_region(adsp
);
760 ret
= adsp_init_clock(adsp
);
764 ret
= adsp_init_regulator(adsp
);
768 ret
= adsp_pds_attach(&pdev
->dev
, adsp
->proxy_pds
,
769 desc
->proxy_pd_names
);
772 adsp
->proxy_pd_count
= ret
;
774 ret
= qcom_q6v5_init(&adsp
->q6v5
, pdev
, rproc
, desc
->crash_reason_smem
, desc
->load_state
,
777 goto detach_proxy_pds
;
779 qcom_add_glink_subdev(rproc
, &adsp
->glink_subdev
, desc
->ssr_name
);
780 qcom_add_smd_subdev(rproc
, &adsp
->smd_subdev
);
781 qcom_add_pdm_subdev(rproc
, &adsp
->pdm_subdev
);
782 adsp
->sysmon
= qcom_add_sysmon_subdev(rproc
,
785 if (IS_ERR(adsp
->sysmon
)) {
786 ret
= PTR_ERR(adsp
->sysmon
);
787 goto detach_proxy_pds
;
790 qcom_add_ssr_subdev(rproc
, &adsp
->ssr_subdev
, desc
->ssr_name
);
791 ret
= rproc_add(rproc
);
793 goto detach_proxy_pds
;
798 adsp_pds_detach(adsp
, adsp
->proxy_pds
, adsp
->proxy_pd_count
);
800 device_init_wakeup(adsp
->dev
, false);
805 static void adsp_remove(struct platform_device
*pdev
)
807 struct qcom_adsp
*adsp
= platform_get_drvdata(pdev
);
809 rproc_del(adsp
->rproc
);
811 qcom_q6v5_deinit(&adsp
->q6v5
);
812 adsp_unassign_memory_region(adsp
);
813 qcom_remove_glink_subdev(adsp
->rproc
, &adsp
->glink_subdev
);
814 qcom_remove_sysmon_subdev(adsp
->sysmon
);
815 qcom_remove_smd_subdev(adsp
->rproc
, &adsp
->smd_subdev
);
816 qcom_remove_pdm_subdev(adsp
->rproc
, &adsp
->pdm_subdev
);
817 qcom_remove_ssr_subdev(adsp
->rproc
, &adsp
->ssr_subdev
);
818 adsp_pds_detach(adsp
, adsp
->proxy_pds
, adsp
->proxy_pd_count
);
819 device_init_wakeup(adsp
->dev
, false);
822 static const struct adsp_data adsp_resource_init
= {
823 .crash_reason_smem
= 423,
824 .firmware_name
= "adsp.mdt",
828 .sysmon_name
= "adsp",
832 static const struct adsp_data sdm845_adsp_resource_init
= {
833 .crash_reason_smem
= 423,
834 .firmware_name
= "adsp.mdt",
837 .load_state
= "adsp",
839 .sysmon_name
= "adsp",
843 static const struct adsp_data sm6350_adsp_resource
= {
844 .crash_reason_smem
= 423,
845 .firmware_name
= "adsp.mdt",
848 .proxy_pd_names
= (char*[]){
853 .load_state
= "adsp",
855 .sysmon_name
= "adsp",
859 static const struct adsp_data sm6375_mpss_resource
= {
860 .crash_reason_smem
= 421,
861 .firmware_name
= "modem.mdt",
865 .proxy_pd_names
= (char*[]){
870 .sysmon_name
= "modem",
874 static const struct adsp_data sm8150_adsp_resource
= {
875 .crash_reason_smem
= 423,
876 .firmware_name
= "adsp.mdt",
879 .proxy_pd_names
= (char*[]){
883 .load_state
= "adsp",
885 .sysmon_name
= "adsp",
889 static const struct adsp_data sm8250_adsp_resource
= {
890 .crash_reason_smem
= 423,
891 .firmware_name
= "adsp.mdt",
894 .proxy_pd_names
= (char*[]){
899 .load_state
= "adsp",
901 .sysmon_name
= "adsp",
905 static const struct adsp_data sm8350_adsp_resource
= {
906 .crash_reason_smem
= 423,
907 .firmware_name
= "adsp.mdt",
910 .proxy_pd_names
= (char*[]){
915 .load_state
= "adsp",
917 .sysmon_name
= "adsp",
921 static const struct adsp_data msm8996_adsp_resource
= {
922 .crash_reason_smem
= 423,
923 .firmware_name
= "adsp.mdt",
926 .proxy_pd_names
= (char*[]){
931 .sysmon_name
= "adsp",
935 static const struct adsp_data cdsp_resource_init
= {
936 .crash_reason_smem
= 601,
937 .firmware_name
= "cdsp.mdt",
941 .sysmon_name
= "cdsp",
945 static const struct adsp_data sdm845_cdsp_resource_init
= {
946 .crash_reason_smem
= 601,
947 .firmware_name
= "cdsp.mdt",
950 .load_state
= "cdsp",
952 .sysmon_name
= "cdsp",
956 static const struct adsp_data sm6350_cdsp_resource
= {
957 .crash_reason_smem
= 601,
958 .firmware_name
= "cdsp.mdt",
961 .proxy_pd_names
= (char*[]){
966 .load_state
= "cdsp",
968 .sysmon_name
= "cdsp",
972 static const struct adsp_data sm8150_cdsp_resource
= {
973 .crash_reason_smem
= 601,
974 .firmware_name
= "cdsp.mdt",
977 .proxy_pd_names
= (char*[]){
981 .load_state
= "cdsp",
983 .sysmon_name
= "cdsp",
987 static const struct adsp_data sm8250_cdsp_resource
= {
988 .crash_reason_smem
= 601,
989 .firmware_name
= "cdsp.mdt",
992 .proxy_pd_names
= (char*[]){
996 .load_state
= "cdsp",
998 .sysmon_name
= "cdsp",
1002 static const struct adsp_data sc8280xp_nsp0_resource
= {
1003 .crash_reason_smem
= 601,
1004 .firmware_name
= "cdsp.mdt",
1007 .proxy_pd_names
= (char*[]){
1011 .ssr_name
= "cdsp0",
1012 .sysmon_name
= "cdsp",
1016 static const struct adsp_data sc8280xp_nsp1_resource
= {
1017 .crash_reason_smem
= 633,
1018 .firmware_name
= "cdsp.mdt",
1021 .proxy_pd_names
= (char*[]){
1025 .ssr_name
= "cdsp1",
1026 .sysmon_name
= "cdsp1",
1030 static const struct adsp_data x1e80100_adsp_resource
= {
1031 .crash_reason_smem
= 423,
1032 .firmware_name
= "adsp.mdt",
1033 .dtb_firmware_name
= "adsp_dtb.mdt",
1036 .lite_pas_id
= 0x1f,
1039 .proxy_pd_names
= (char*[]){
1044 .load_state
= "adsp",
1045 .ssr_name
= "lpass",
1046 .sysmon_name
= "adsp",
1050 static const struct adsp_data x1e80100_cdsp_resource
= {
1051 .crash_reason_smem
= 601,
1052 .firmware_name
= "cdsp.mdt",
1053 .dtb_firmware_name
= "cdsp_dtb.mdt",
1058 .proxy_pd_names
= (char*[]){
1064 .load_state
= "cdsp",
1066 .sysmon_name
= "cdsp",
1070 static const struct adsp_data sm8350_cdsp_resource
= {
1071 .crash_reason_smem
= 601,
1072 .firmware_name
= "cdsp.mdt",
1075 .proxy_pd_names
= (char*[]){
1080 .load_state
= "cdsp",
1082 .sysmon_name
= "cdsp",
1086 static const struct adsp_data mpss_resource_init
= {
1087 .crash_reason_smem
= 421,
1088 .firmware_name
= "modem.mdt",
1092 .proxy_pd_names
= (char*[]){
1097 .load_state
= "modem",
1099 .sysmon_name
= "modem",
1103 static const struct adsp_data sc8180x_mpss_resource
= {
1104 .crash_reason_smem
= 421,
1105 .firmware_name
= "modem.mdt",
1108 .proxy_pd_names
= (char*[]){
1112 .load_state
= "modem",
1114 .sysmon_name
= "modem",
1118 static const struct adsp_data msm8996_slpi_resource_init
= {
1119 .crash_reason_smem
= 424,
1120 .firmware_name
= "slpi.mdt",
1123 .proxy_pd_names
= (char*[]){
1128 .sysmon_name
= "slpi",
1132 static const struct adsp_data sdm845_slpi_resource_init
= {
1133 .crash_reason_smem
= 424,
1134 .firmware_name
= "slpi.mdt",
1137 .proxy_pd_names
= (char*[]){
1142 .load_state
= "slpi",
1144 .sysmon_name
= "slpi",
1148 static const struct adsp_data wcss_resource_init
= {
1149 .crash_reason_smem
= 421,
1150 .firmware_name
= "wcnss.mdt",
1154 .sysmon_name
= "wcnss",
1158 static const struct adsp_data sdx55_mpss_resource
= {
1159 .crash_reason_smem
= 421,
1160 .firmware_name
= "modem.mdt",
1163 .proxy_pd_names
= (char*[]){
1169 .sysmon_name
= "modem",
1173 static const struct adsp_data sm8450_mpss_resource
= {
1174 .crash_reason_smem
= 421,
1175 .firmware_name
= "modem.mdt",
1179 .decrypt_shutdown
= true,
1180 .proxy_pd_names
= (char*[]){
1185 .load_state
= "modem",
1187 .sysmon_name
= "modem",
1191 static const struct adsp_data sm8550_adsp_resource
= {
1192 .crash_reason_smem
= 423,
1193 .firmware_name
= "adsp.mdt",
1194 .dtb_firmware_name
= "adsp_dtb.mdt",
1199 .proxy_pd_names
= (char*[]){
1204 .load_state
= "adsp",
1205 .ssr_name
= "lpass",
1206 .sysmon_name
= "adsp",
1211 static const struct adsp_data sm8550_cdsp_resource
= {
1212 .crash_reason_smem
= 601,
1213 .firmware_name
= "cdsp.mdt",
1214 .dtb_firmware_name
= "cdsp_dtb.mdt",
1219 .proxy_pd_names
= (char*[]){
1225 .load_state
= "cdsp",
1227 .sysmon_name
= "cdsp",
1232 static const struct adsp_data sm8550_mpss_resource
= {
1233 .crash_reason_smem
= 421,
1234 .firmware_name
= "modem.mdt",
1235 .dtb_firmware_name
= "modem_dtb.mdt",
1240 .decrypt_shutdown
= true,
1241 .proxy_pd_names
= (char*[]){
1246 .load_state
= "modem",
1248 .sysmon_name
= "modem",
1251 .region_assign_idx
= 2,
1252 .region_assign_count
= 1,
1253 .region_assign_vmid
= QCOM_SCM_VMID_MSS_MSA
,
1256 static const struct adsp_data sc7280_wpss_resource
= {
1257 .crash_reason_smem
= 626,
1258 .firmware_name
= "wpss.mdt",
1261 .proxy_pd_names
= (char*[]){
1266 .load_state
= "wpss",
1268 .sysmon_name
= "wpss",
1272 static const struct adsp_data sm8650_cdsp_resource
= {
1273 .crash_reason_smem
= 601,
1274 .firmware_name
= "cdsp.mdt",
1275 .dtb_firmware_name
= "cdsp_dtb.mdt",
1280 .proxy_pd_names
= (char*[]){
1286 .load_state
= "cdsp",
1288 .sysmon_name
= "cdsp",
1291 .region_assign_idx
= 2,
1292 .region_assign_count
= 1,
1293 .region_assign_shared
= true,
1294 .region_assign_vmid
= QCOM_SCM_VMID_CDSP
,
1297 static const struct adsp_data sm8650_mpss_resource
= {
1298 .crash_reason_smem
= 421,
1299 .firmware_name
= "modem.mdt",
1300 .dtb_firmware_name
= "modem_dtb.mdt",
1305 .decrypt_shutdown
= true,
1306 .proxy_pd_names
= (char*[]){
1311 .load_state
= "modem",
1313 .sysmon_name
= "modem",
1316 .region_assign_idx
= 2,
1317 .region_assign_count
= 3,
1318 .region_assign_vmid
= QCOM_SCM_VMID_MSS_MSA
,
1321 static const struct of_device_id adsp_of_match
[] = {
1322 { .compatible
= "qcom,msm8226-adsp-pil", .data
= &adsp_resource_init
},
1323 { .compatible
= "qcom,msm8953-adsp-pil", .data
= &msm8996_adsp_resource
},
1324 { .compatible
= "qcom,msm8974-adsp-pil", .data
= &adsp_resource_init
},
1325 { .compatible
= "qcom,msm8996-adsp-pil", .data
= &msm8996_adsp_resource
},
1326 { .compatible
= "qcom,msm8996-slpi-pil", .data
= &msm8996_slpi_resource_init
},
1327 { .compatible
= "qcom,msm8998-adsp-pas", .data
= &msm8996_adsp_resource
},
1328 { .compatible
= "qcom,msm8998-slpi-pas", .data
= &msm8996_slpi_resource_init
},
1329 { .compatible
= "qcom,qcs404-adsp-pas", .data
= &adsp_resource_init
},
1330 { .compatible
= "qcom,qcs404-cdsp-pas", .data
= &cdsp_resource_init
},
1331 { .compatible
= "qcom,qcs404-wcss-pas", .data
= &wcss_resource_init
},
1332 { .compatible
= "qcom,sc7180-adsp-pas", .data
= &sm8250_adsp_resource
},
1333 { .compatible
= "qcom,sc7180-mpss-pas", .data
= &mpss_resource_init
},
1334 { .compatible
= "qcom,sc7280-adsp-pas", .data
= &sm8350_adsp_resource
},
1335 { .compatible
= "qcom,sc7280-cdsp-pas", .data
= &sm6350_cdsp_resource
},
1336 { .compatible
= "qcom,sc7280-mpss-pas", .data
= &mpss_resource_init
},
1337 { .compatible
= "qcom,sc7280-wpss-pas", .data
= &sc7280_wpss_resource
},
1338 { .compatible
= "qcom,sc8180x-adsp-pas", .data
= &sm8150_adsp_resource
},
1339 { .compatible
= "qcom,sc8180x-cdsp-pas", .data
= &sm8150_cdsp_resource
},
1340 { .compatible
= "qcom,sc8180x-mpss-pas", .data
= &sc8180x_mpss_resource
},
1341 { .compatible
= "qcom,sc8280xp-adsp-pas", .data
= &sm8250_adsp_resource
},
1342 { .compatible
= "qcom,sc8280xp-nsp0-pas", .data
= &sc8280xp_nsp0_resource
},
1343 { .compatible
= "qcom,sc8280xp-nsp1-pas", .data
= &sc8280xp_nsp1_resource
},
1344 { .compatible
= "qcom,sdm660-adsp-pas", .data
= &adsp_resource_init
},
1345 { .compatible
= "qcom,sdm845-adsp-pas", .data
= &sdm845_adsp_resource_init
},
1346 { .compatible
= "qcom,sdm845-cdsp-pas", .data
= &sdm845_cdsp_resource_init
},
1347 { .compatible
= "qcom,sdm845-slpi-pas", .data
= &sdm845_slpi_resource_init
},
1348 { .compatible
= "qcom,sdx55-mpss-pas", .data
= &sdx55_mpss_resource
},
1349 { .compatible
= "qcom,sm6115-adsp-pas", .data
= &adsp_resource_init
},
1350 { .compatible
= "qcom,sm6115-cdsp-pas", .data
= &cdsp_resource_init
},
1351 { .compatible
= "qcom,sm6115-mpss-pas", .data
= &sc8180x_mpss_resource
},
1352 { .compatible
= "qcom,sm6350-adsp-pas", .data
= &sm6350_adsp_resource
},
1353 { .compatible
= "qcom,sm6350-cdsp-pas", .data
= &sm6350_cdsp_resource
},
1354 { .compatible
= "qcom,sm6350-mpss-pas", .data
= &mpss_resource_init
},
1355 { .compatible
= "qcom,sm6375-adsp-pas", .data
= &sm6350_adsp_resource
},
1356 { .compatible
= "qcom,sm6375-cdsp-pas", .data
= &sm8150_cdsp_resource
},
1357 { .compatible
= "qcom,sm6375-mpss-pas", .data
= &sm6375_mpss_resource
},
1358 { .compatible
= "qcom,sm8150-adsp-pas", .data
= &sm8150_adsp_resource
},
1359 { .compatible
= "qcom,sm8150-cdsp-pas", .data
= &sm8150_cdsp_resource
},
1360 { .compatible
= "qcom,sm8150-mpss-pas", .data
= &mpss_resource_init
},
1361 { .compatible
= "qcom,sm8150-slpi-pas", .data
= &sdm845_slpi_resource_init
},
1362 { .compatible
= "qcom,sm8250-adsp-pas", .data
= &sm8250_adsp_resource
},
1363 { .compatible
= "qcom,sm8250-cdsp-pas", .data
= &sm8250_cdsp_resource
},
1364 { .compatible
= "qcom,sm8250-slpi-pas", .data
= &sdm845_slpi_resource_init
},
1365 { .compatible
= "qcom,sm8350-adsp-pas", .data
= &sm8350_adsp_resource
},
1366 { .compatible
= "qcom,sm8350-cdsp-pas", .data
= &sm8350_cdsp_resource
},
1367 { .compatible
= "qcom,sm8350-slpi-pas", .data
= &sdm845_slpi_resource_init
},
1368 { .compatible
= "qcom,sm8350-mpss-pas", .data
= &mpss_resource_init
},
1369 { .compatible
= "qcom,sm8450-adsp-pas", .data
= &sm8350_adsp_resource
},
1370 { .compatible
= "qcom,sm8450-cdsp-pas", .data
= &sm8350_cdsp_resource
},
1371 { .compatible
= "qcom,sm8450-slpi-pas", .data
= &sdm845_slpi_resource_init
},
1372 { .compatible
= "qcom,sm8450-mpss-pas", .data
= &sm8450_mpss_resource
},
1373 { .compatible
= "qcom,sm8550-adsp-pas", .data
= &sm8550_adsp_resource
},
1374 { .compatible
= "qcom,sm8550-cdsp-pas", .data
= &sm8550_cdsp_resource
},
1375 { .compatible
= "qcom,sm8550-mpss-pas", .data
= &sm8550_mpss_resource
},
1376 { .compatible
= "qcom,sm8650-adsp-pas", .data
= &sm8550_adsp_resource
},
1377 { .compatible
= "qcom,sm8650-cdsp-pas", .data
= &sm8650_cdsp_resource
},
1378 { .compatible
= "qcom,sm8650-mpss-pas", .data
= &sm8650_mpss_resource
},
1379 { .compatible
= "qcom,x1e80100-adsp-pas", .data
= &x1e80100_adsp_resource
},
1380 { .compatible
= "qcom,x1e80100-cdsp-pas", .data
= &x1e80100_cdsp_resource
},
1383 MODULE_DEVICE_TABLE(of
, adsp_of_match
);
1385 static struct platform_driver adsp_driver
= {
1386 .probe
= adsp_probe
,
1387 .remove_new
= adsp_remove
,
1389 .name
= "qcom_q6v5_pas",
1390 .of_match_table
= adsp_of_match
,
1394 module_platform_driver(adsp_driver
);
1395 MODULE_DESCRIPTION("Qualcomm Hexagon v5 Peripheral Authentication Service driver");
1396 MODULE_LICENSE("GPL v2");