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mlxsw: spectrum: Mark split ports as such
[linux-stable.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
blobd768c7b6c6d6688c46077c48e25df45cdf9ad7dc
1 /*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/pci.h>
41 #include <linux/netdevice.h>
42 #include <linux/etherdevice.h>
43 #include <linux/ethtool.h>
44 #include <linux/slab.h>
45 #include <linux/device.h>
46 #include <linux/skbuff.h>
47 #include <linux/if_vlan.h>
48 #include <linux/if_bridge.h>
49 #include <linux/workqueue.h>
50 #include <linux/jiffies.h>
51 #include <linux/bitops.h>
52 #include <linux/list.h>
53 #include <linux/notifier.h>
54 #include <linux/dcbnl.h>
55 #include <linux/inetdevice.h>
56 #include <net/switchdev.h>
57 #include <net/pkt_cls.h>
58 #include <net/tc_act/tc_mirred.h>
59 #include <net/netevent.h>
60
61 #include "spectrum.h"
62 #include "pci.h"
63 #include "core.h"
64 #include "reg.h"
65 #include "port.h"
66 #include "trap.h"
67 #include "txheader.h"
68
69 static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
70 static const char mlxsw_sp_driver_version[] = "1.0";
71
72 /* tx_hdr_version
73 * Tx header version.
74 * Must be set to 1.
75 */
76 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
77
78 /* tx_hdr_ctl
79 * Packet control type.
80 * 0 - Ethernet control (e.g. EMADs, LACP)
81 * 1 - Ethernet data
82 */
83 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
84
85 /* tx_hdr_proto
86 * Packet protocol type. Must be set to 1 (Ethernet).
87 */
88 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
89
90 /* tx_hdr_rx_is_router
91 * Packet is sent from the router. Valid for data packets only.
92 */
93 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
94
95 /* tx_hdr_fid_valid
96 * Indicates if the 'fid' field is valid and should be used for
97 * forwarding lookup. Valid for data packets only.
98 */
99 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
100
101 /* tx_hdr_swid
102 * Switch partition ID. Must be set to 0.
103 */
104 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
105
106 /* tx_hdr_control_tclass
107 * Indicates if the packet should use the control TClass and not one
108 * of the data TClasses.
109 */
110 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
111
112 /* tx_hdr_etclass
113 * Egress TClass to be used on the egress device on the egress port.
114 */
115 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
116
117 /* tx_hdr_port_mid
118 * Destination local port for unicast packets.
119 * Destination multicast ID for multicast packets.
120 *
121 * Control packets are directed to a specific egress port, while data
122 * packets are transmitted through the CPU port (0) into the switch partition,
123 * where forwarding rules are applied.
124 */
125 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
126
127 /* tx_hdr_fid
128 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
129 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
130 * Valid for data packets only.
131 */
132 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
133
134 /* tx_hdr_type
135 * 0 - Data packets
136 * 6 - Control packets
137 */
138 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
139
140 static bool mlxsw_sp_port_dev_check(const struct net_device *dev);
141
142 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
143 const struct mlxsw_tx_info *tx_info)
144 {
145 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
146
147 memset(txhdr, 0, MLXSW_TXHDR_LEN);
148
149 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
150 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
151 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
152 mlxsw_tx_hdr_swid_set(txhdr, 0);
153 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
154 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
155 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
156 }
157
158 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
159 {
160 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
161 int err;
162
163 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
164 if (err)
165 return err;
166 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
167 return 0;
168 }
169
170 static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
171 {
172 int i;
173
174 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
175 return -EIO;
176
177 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
178 MAX_SPAN);
179 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
180 sizeof(struct mlxsw_sp_span_entry),
181 GFP_KERNEL);
182 if (!mlxsw_sp->span.entries)
183 return -ENOMEM;
184
185 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
186 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
187
188 return 0;
189 }
190
191 static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
192 {
193 int i;
194
195 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
196 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
197
198 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
199 }
200 kfree(mlxsw_sp->span.entries);
201 }
202
203 static struct mlxsw_sp_span_entry *
204 mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
205 {
206 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
207 struct mlxsw_sp_span_entry *span_entry;
208 char mpat_pl[MLXSW_REG_MPAT_LEN];
209 u8 local_port = port->local_port;
210 int index;
211 int i;
212 int err;
213
214 /* find a free entry to use */
215 index = -1;
216 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
217 if (!mlxsw_sp->span.entries[i].used) {
218 index = i;
219 span_entry = &mlxsw_sp->span.entries[i];
220 break;
221 }
222 }
223 if (index < 0)
224 return NULL;
225
226 /* create a new port analayzer entry for local_port */
227 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
228 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
229 if (err)
230 return NULL;
231
232 span_entry->used = true;
233 span_entry->id = index;
234 span_entry->ref_count = 1;
235 span_entry->local_port = local_port;
236 return span_entry;
237 }
238
239 static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
240 struct mlxsw_sp_span_entry *span_entry)
241 {
242 u8 local_port = span_entry->local_port;
243 char mpat_pl[MLXSW_REG_MPAT_LEN];
244 int pa_id = span_entry->id;
245
246 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
247 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
248 span_entry->used = false;
249 }
250
251 static struct mlxsw_sp_span_entry *
252 mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
253 {
254 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
255 int i;
256
257 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
258 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
259
260 if (curr->used && curr->local_port == port->local_port)
261 return curr;
262 }
263 return NULL;
264 }
265
266 static struct mlxsw_sp_span_entry
267 *mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
268 {
269 struct mlxsw_sp_span_entry *span_entry;
270
271 span_entry = mlxsw_sp_span_entry_find(port);
272 if (span_entry) {
273 /* Already exists, just take a reference */
274 span_entry->ref_count++;
275 return span_entry;
276 }
277
278 return mlxsw_sp_span_entry_create(port);
279 }
280
281 static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
282 struct mlxsw_sp_span_entry *span_entry)
283 {
284 WARN_ON(!span_entry->ref_count);
285 if (--span_entry->ref_count == 0)
286 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
287 return 0;
288 }
289
290 static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
291 {
292 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
293 struct mlxsw_sp_span_inspected_port *p;
294 int i;
295
296 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
297 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
298
299 list_for_each_entry(p, &curr->bound_ports_list, list)
300 if (p->local_port == port->local_port &&
301 p->type == MLXSW_SP_SPAN_EGRESS)
302 return true;
303 }
304
305 return false;
306 }
307
308 static int mlxsw_sp_span_mtu_to_buffsize(int mtu)
309 {
310 return MLXSW_SP_BYTES_TO_CELLS(mtu * 5 / 2) + 1;
311 }
312
313 static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
314 {
315 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
316 char sbib_pl[MLXSW_REG_SBIB_LEN];
317 int err;
318
319 /* If port is egress mirrored, the shared buffer size should be
320 * updated according to the mtu value
321 */
322 if (mlxsw_sp_span_is_egress_mirror(port)) {
323 mlxsw_reg_sbib_pack(sbib_pl, port->local_port,
324 mlxsw_sp_span_mtu_to_buffsize(mtu));
325 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
326 if (err) {
327 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
328 return err;
329 }
330 }
331
332 return 0;
333 }
334
335 static struct mlxsw_sp_span_inspected_port *
336 mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
337 struct mlxsw_sp_span_entry *span_entry)
338 {
339 struct mlxsw_sp_span_inspected_port *p;
340
341 list_for_each_entry(p, &span_entry->bound_ports_list, list)
342 if (port->local_port == p->local_port)
343 return p;
344 return NULL;
345 }
346
347 static int
348 mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
349 struct mlxsw_sp_span_entry *span_entry,
350 enum mlxsw_sp_span_type type)
351 {
352 struct mlxsw_sp_span_inspected_port *inspected_port;
353 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
354 char mpar_pl[MLXSW_REG_MPAR_LEN];
355 char sbib_pl[MLXSW_REG_SBIB_LEN];
356 int pa_id = span_entry->id;
357 int err;
358
359 /* if it is an egress SPAN, bind a shared buffer to it */
360 if (type == MLXSW_SP_SPAN_EGRESS) {
361 mlxsw_reg_sbib_pack(sbib_pl, port->local_port,
362 mlxsw_sp_span_mtu_to_buffsize(port->dev->mtu));
363 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
364 if (err) {
365 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
366 return err;
367 }
368 }
369
370 /* bind the port to the SPAN entry */
371 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
372 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
373 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
374 if (err)
375 goto err_mpar_reg_write;
376
377 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
378 if (!inspected_port) {
379 err = -ENOMEM;
380 goto err_inspected_port_alloc;
381 }
382 inspected_port->local_port = port->local_port;
383 inspected_port->type = type;
384 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
385
386 return 0;
387
388 err_mpar_reg_write:
389 err_inspected_port_alloc:
390 if (type == MLXSW_SP_SPAN_EGRESS) {
391 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
392 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
393 }
394 return err;
395 }
396
397 static void
398 mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
399 struct mlxsw_sp_span_entry *span_entry,
400 enum mlxsw_sp_span_type type)
401 {
402 struct mlxsw_sp_span_inspected_port *inspected_port;
403 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
404 char mpar_pl[MLXSW_REG_MPAR_LEN];
405 char sbib_pl[MLXSW_REG_SBIB_LEN];
406 int pa_id = span_entry->id;
407
408 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
409 if (!inspected_port)
410 return;
411
412 /* remove the inspected port */
413 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
414 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
415 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
416
417 /* remove the SBIB buffer if it was egress SPAN */
418 if (type == MLXSW_SP_SPAN_EGRESS) {
419 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
420 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
421 }
422
423 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
424
425 list_del(&inspected_port->list);
426 kfree(inspected_port);
427 }
428
429 static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
430 struct mlxsw_sp_port *to,
431 enum mlxsw_sp_span_type type)
432 {
433 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
434 struct mlxsw_sp_span_entry *span_entry;
435 int err;
436
437 span_entry = mlxsw_sp_span_entry_get(to);
438 if (!span_entry)
439 return -ENOENT;
440
441 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
442 span_entry->id);
443
444 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
445 if (err)
446 goto err_port_bind;
447
448 return 0;
449
450 err_port_bind:
451 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
452 return err;
453 }
454
455 static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
456 struct mlxsw_sp_port *to,
457 enum mlxsw_sp_span_type type)
458 {
459 struct mlxsw_sp_span_entry *span_entry;
460
461 span_entry = mlxsw_sp_span_entry_find(to);
462 if (!span_entry) {
463 netdev_err(from->dev, "no span entry found\n");
464 return;
465 }
466
467 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
468 span_entry->id);
469 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
470 }
471
472 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
473 bool is_up)
474 {
475 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
476 char paos_pl[MLXSW_REG_PAOS_LEN];
477
478 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
479 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
480 MLXSW_PORT_ADMIN_STATUS_DOWN);
481 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
482 }
483
484 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
485 unsigned char *addr)
486 {
487 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
488 char ppad_pl[MLXSW_REG_PPAD_LEN];
489
490 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
491 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
492 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
493 }
494
495 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
496 {
497 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
498 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
499
500 ether_addr_copy(addr, mlxsw_sp->base_mac);
501 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
502 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
503 }
504
505 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
506 {
507 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
508 char pmtu_pl[MLXSW_REG_PMTU_LEN];
509 int max_mtu;
510 int err;
511
512 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
513 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
514 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
515 if (err)
516 return err;
517 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
518
519 if (mtu > max_mtu)
520 return -EINVAL;
521
522 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
523 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
524 }
525
526 static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
527 u8 swid)
528 {
529 char pspa_pl[MLXSW_REG_PSPA_LEN];
530
531 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
532 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
533 }
534
535 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
536 {
537 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
538
539 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
540 swid);
541 }
542
543 static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
544 bool enable)
545 {
546 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
547 char svpe_pl[MLXSW_REG_SVPE_LEN];
548
549 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
550 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
551 }
552
553 int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
554 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
555 u16 vid)
556 {
557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
558 char svfa_pl[MLXSW_REG_SVFA_LEN];
559
560 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
561 fid, vid);
562 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
563 }
564
565 int __mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
566 u16 vid_begin, u16 vid_end,
567 bool learn_enable)
568 {
569 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
570 char *spvmlr_pl;
571 int err;
572
573 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
574 if (!spvmlr_pl)
575 return -ENOMEM;
576 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid_begin,
577 vid_end, learn_enable);
578 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
579 kfree(spvmlr_pl);
580 return err;
581 }
582
583 static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
584 u16 vid, bool learn_enable)
585 {
586 return __mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, vid,
587 learn_enable);
588 }
589
590 static int
591 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
592 {
593 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
594 char sspr_pl[MLXSW_REG_SSPR_LEN];
595
596 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
598 }
599
600 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
601 u8 local_port, u8 *p_module,
602 u8 *p_width, u8 *p_lane)
603 {
604 char pmlp_pl[MLXSW_REG_PMLP_LEN];
605 int err;
606
607 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
608 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
609 if (err)
610 return err;
611 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
612 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
613 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
614 return 0;
615 }
616
617 static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
618 u8 module, u8 width, u8 lane)
619 {
620 char pmlp_pl[MLXSW_REG_PMLP_LEN];
621 int i;
622
623 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
624 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
625 for (i = 0; i < width; i++) {
626 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
627 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
628 }
629
630 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
631 }
632
633 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
634 {
635 char pmlp_pl[MLXSW_REG_PMLP_LEN];
636
637 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
638 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
639 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
640 }
641
642 static int mlxsw_sp_port_open(struct net_device *dev)
643 {
644 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
645 int err;
646
647 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
648 if (err)
649 return err;
650 netif_start_queue(dev);
651 return 0;
652 }
653
654 static int mlxsw_sp_port_stop(struct net_device *dev)
655 {
656 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
657
658 netif_stop_queue(dev);
659 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
660 }
661
662 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
663 struct net_device *dev)
664 {
665 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
666 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
667 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
668 const struct mlxsw_tx_info tx_info = {
669 .local_port = mlxsw_sp_port->local_port,
670 .is_emad = false,
671 };
672 u64 len;
673 int err;
674
675 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
676 return NETDEV_TX_BUSY;
677
678 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
679 struct sk_buff *skb_orig = skb;
680
681 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
682 if (!skb) {
683 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
684 dev_kfree_skb_any(skb_orig);
685 return NETDEV_TX_OK;
686 }
687 }
688
689 if (eth_skb_pad(skb)) {
690 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
691 return NETDEV_TX_OK;
692 }
693
694 mlxsw_sp_txhdr_construct(skb, &tx_info);
695 /* TX header is consumed by HW on the way so we shouldn't count its
696 * bytes as being sent.
697 */
698 len = skb->len - MLXSW_TXHDR_LEN;
699
700 /* Due to a race we might fail here because of a full queue. In that
701 * unlikely case we simply drop the packet.
702 */
703 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
704
705 if (!err) {
706 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
707 u64_stats_update_begin(&pcpu_stats->syncp);
708 pcpu_stats->tx_packets++;
709 pcpu_stats->tx_bytes += len;
710 u64_stats_update_end(&pcpu_stats->syncp);
711 } else {
712 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
713 dev_kfree_skb_any(skb);
714 }
715 return NETDEV_TX_OK;
716 }
717
718 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
719 {
720 }
721
722 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
723 {
724 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
725 struct sockaddr *addr = p;
726 int err;
727
728 if (!is_valid_ether_addr(addr->sa_data))
729 return -EADDRNOTAVAIL;
730
731 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
732 if (err)
733 return err;
734 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
735 return 0;
736 }
737
738 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
739 bool pause_en, bool pfc_en, u16 delay)
740 {
741 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
742
743 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
744 MLXSW_SP_PAUSE_DELAY;
745
746 if (pause_en || pfc_en)
747 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
748 pg_size + delay, pg_size);
749 else
750 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
751 }
752
753 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
754 u8 *prio_tc, bool pause_en,
755 struct ieee_pfc *my_pfc)
756 {
757 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
758 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
759 u16 delay = !!my_pfc ? my_pfc->delay : 0;
760 char pbmc_pl[MLXSW_REG_PBMC_LEN];
761 int i, j, err;
762
763 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
764 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
765 if (err)
766 return err;
767
768 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
769 bool configure = false;
770 bool pfc = false;
771
772 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
773 if (prio_tc[j] == i) {
774 pfc = pfc_en & BIT(j);
775 configure = true;
776 break;
777 }
778 }
779
780 if (!configure)
781 continue;
782 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
783 }
784
785 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
786 }
787
788 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
789 int mtu, bool pause_en)
790 {
791 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
792 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
793 struct ieee_pfc *my_pfc;
794 u8 *prio_tc;
795
796 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
797 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
798
799 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
800 pause_en, my_pfc);
801 }
802
803 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
804 {
805 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
806 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
807 int err;
808
809 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
810 if (err)
811 return err;
812 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
813 if (err)
814 goto err_span_port_mtu_update;
815 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
816 if (err)
817 goto err_port_mtu_set;
818 dev->mtu = mtu;
819 return 0;
820
821 err_port_mtu_set:
822 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
823 err_span_port_mtu_update:
824 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
825 return err;
826 }
827
828 static int
829 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
830 struct rtnl_link_stats64 *stats)
831 {
832 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
833 struct mlxsw_sp_port_pcpu_stats *p;
834 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
835 u32 tx_dropped = 0;
836 unsigned int start;
837 int i;
838
839 for_each_possible_cpu(i) {
840 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
841 do {
842 start = u64_stats_fetch_begin_irq(&p->syncp);
843 rx_packets = p->rx_packets;
844 rx_bytes = p->rx_bytes;
845 tx_packets = p->tx_packets;
846 tx_bytes = p->tx_bytes;
847 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
848
849 stats->rx_packets += rx_packets;
850 stats->rx_bytes += rx_bytes;
851 stats->tx_packets += tx_packets;
852 stats->tx_bytes += tx_bytes;
853 /* tx_dropped is u32, updated without syncp protection. */
854 tx_dropped += p->tx_dropped;
855 }
856 stats->tx_dropped = tx_dropped;
857 return 0;
858 }
859
860 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
861 {
862 switch (attr_id) {
863 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
864 return true;
865 }
866
867 return false;
868 }
869
870 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
871 void *sp)
872 {
873 switch (attr_id) {
874 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
875 return mlxsw_sp_port_get_sw_stats64(dev, sp);
876 }
877
878 return -EINVAL;
879 }
880
881 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
882 int prio, char *ppcnt_pl)
883 {
884 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
885 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
886
887 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
888 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
889 }
890
891 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
892 struct rtnl_link_stats64 *stats)
893 {
894 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
895 int err;
896
897 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
898 0, ppcnt_pl);
899 if (err)
900 goto out;
901
902 stats->tx_packets =
903 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
904 stats->rx_packets =
905 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
906 stats->tx_bytes =
907 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
908 stats->rx_bytes =
909 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
910 stats->multicast =
911 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
912
913 stats->rx_crc_errors =
914 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
915 stats->rx_frame_errors =
916 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
917
918 stats->rx_length_errors = (
919 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
920 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
921 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
922
923 stats->rx_errors = (stats->rx_crc_errors +
924 stats->rx_frame_errors + stats->rx_length_errors);
925
926 out:
927 return err;
928 }
929
930 static void update_stats_cache(struct work_struct *work)
931 {
932 struct mlxsw_sp_port *mlxsw_sp_port =
933 container_of(work, struct mlxsw_sp_port,
934 hw_stats.update_dw.work);
935
936 if (!netif_carrier_ok(mlxsw_sp_port->dev))
937 goto out;
938
939 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
940 mlxsw_sp_port->hw_stats.cache);
941
942 out:
943 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
944 MLXSW_HW_STATS_UPDATE_TIME);
945 }
946
947 /* Return the stats from a cache that is updated periodically,
948 * as this function might get called in an atomic context.
949 */
950 static struct rtnl_link_stats64 *
951 mlxsw_sp_port_get_stats64(struct net_device *dev,
952 struct rtnl_link_stats64 *stats)
953 {
954 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
955
956 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
957
958 return stats;
959 }
960
961 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
962 u16 vid_end, bool is_member, bool untagged)
963 {
964 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
965 char *spvm_pl;
966 int err;
967
968 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
969 if (!spvm_pl)
970 return -ENOMEM;
971
972 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
973 vid_end, is_member, untagged);
974 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
975 kfree(spvm_pl);
976 return err;
977 }
978
979 static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
980 {
981 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
982 u16 vid, last_visited_vid;
983 int err;
984
985 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
986 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
987 vid);
988 if (err) {
989 last_visited_vid = vid;
990 goto err_port_vid_to_fid_set;
991 }
992 }
993
994 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
995 if (err) {
996 last_visited_vid = VLAN_N_VID;
997 goto err_port_vid_to_fid_set;
998 }
999
1000 return 0;
1001
1002 err_port_vid_to_fid_set:
1003 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
1004 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
1005 vid);
1006 return err;
1007 }
1008
1009 static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
1010 {
1011 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1012 u16 vid;
1013 int err;
1014
1015 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
1016 if (err)
1017 return err;
1018
1019 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1020 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
1021 vid, vid);
1022 if (err)
1023 return err;
1024 }
1025
1026 return 0;
1027 }
1028
1029 static struct mlxsw_sp_port *
1030 mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1031 {
1032 struct mlxsw_sp_port *mlxsw_sp_vport;
1033
1034 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
1035 if (!mlxsw_sp_vport)
1036 return NULL;
1037
1038 /* dev will be set correctly after the VLAN device is linked
1039 * with the real device. In case of bridge SELF invocation, dev
1040 * will remain as is.
1041 */
1042 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
1043 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1044 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
1045 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
1046 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
1047 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
1048 mlxsw_sp_vport->vport.vid = vid;
1049
1050 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
1051
1052 return mlxsw_sp_vport;
1053 }
1054
1055 static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
1056 {
1057 list_del(&mlxsw_sp_vport->vport.list);
1058 kfree(mlxsw_sp_vport);
1059 }
1060
1061 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1062 __be16 __always_unused proto, u16 vid)
1063 {
1064 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1065 struct mlxsw_sp_port *mlxsw_sp_vport;
1066 bool untagged = vid == 1;
1067 int err;
1068
1069 /* VLAN 0 is added to HW filter when device goes up, but it is
1070 * reserved in our case, so simply return.
1071 */
1072 if (!vid)
1073 return 0;
1074
1075 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid))
1076 return 0;
1077
1078 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
1079 if (!mlxsw_sp_vport)
1080 return -ENOMEM;
1081
1082 /* When adding the first VLAN interface on a bridged port we need to
1083 * transition all the active 802.1Q bridge VLANs to use explicit
1084 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
1085 */
1086 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
1087 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
1088 if (err)
1089 goto err_port_vp_mode_trans;
1090 }
1091
1092 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
1093 if (err)
1094 goto err_port_add_vid;
1095
1096 return 0;
1097
1098 err_port_add_vid:
1099 if (list_is_singular(&mlxsw_sp_port->vports_list))
1100 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
1101 err_port_vp_mode_trans:
1102 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1103 return err;
1104 }
1105
1106 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1107 __be16 __always_unused proto, u16 vid)
1108 {
1109 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1110 struct mlxsw_sp_port *mlxsw_sp_vport;
1111 struct mlxsw_sp_fid *f;
1112
1113 /* VLAN 0 is removed from HW filter when device goes down, but
1114 * it is reserved in our case, so simply return.
1115 */
1116 if (!vid)
1117 return 0;
1118
1119 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
1120 if (WARN_ON(!mlxsw_sp_vport))
1121 return 0;
1122
1123 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
1124
1125 /* Drop FID reference. If this was the last reference the
1126 * resources will be freed.
1127 */
1128 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
1129 if (f && !WARN_ON(!f->leave))
1130 f->leave(mlxsw_sp_vport);
1131
1132 /* When removing the last VLAN interface on a bridged port we need to
1133 * transition all active 802.1Q bridge VLANs to use VID to FID
1134 * mappings and set port's mode to VLAN mode.
1135 */
1136 if (list_is_singular(&mlxsw_sp_port->vports_list))
1137 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
1138
1139 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1140
1141 return 0;
1142 }
1143
1144 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1145 size_t len)
1146 {
1147 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1148 u8 module = mlxsw_sp_port->mapping.module;
1149 u8 width = mlxsw_sp_port->mapping.width;
1150 u8 lane = mlxsw_sp_port->mapping.lane;
1151 int err;
1152
1153 if (!mlxsw_sp_port->split)
1154 err = snprintf(name, len, "p%d", module + 1);
1155 else
1156 err = snprintf(name, len, "p%ds%d", module + 1,
1157 lane / width);
1158
1159 if (err >= len)
1160 return -EINVAL;
1161
1162 return 0;
1163 }
1164
1165 static struct mlxsw_sp_port_mall_tc_entry *
1166 mlxsw_sp_port_mirror_entry_find(struct mlxsw_sp_port *port,
1167 unsigned long cookie) {
1168 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1169
1170 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1171 if (mall_tc_entry->cookie == cookie)
1172 return mall_tc_entry;
1173
1174 return NULL;
1175 }
1176
1177 static int
1178 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1179 struct tc_cls_matchall_offload *cls,
1180 const struct tc_action *a,
1181 bool ingress)
1182 {
1183 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1184 struct net *net = dev_net(mlxsw_sp_port->dev);
1185 enum mlxsw_sp_span_type span_type;
1186 struct mlxsw_sp_port *to_port;
1187 struct net_device *to_dev;
1188 int ifindex;
1189 int err;
1190
1191 ifindex = tcf_mirred_ifindex(a);
1192 to_dev = __dev_get_by_index(net, ifindex);
1193 if (!to_dev) {
1194 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1195 return -EINVAL;
1196 }
1197
1198 if (!mlxsw_sp_port_dev_check(to_dev)) {
1199 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
1200 return -ENOTSUPP;
1201 }
1202 to_port = netdev_priv(to_dev);
1203
1204 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1205 if (!mall_tc_entry)
1206 return -ENOMEM;
1207
1208 mall_tc_entry->cookie = cls->cookie;
1209 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1210 mall_tc_entry->mirror.to_local_port = to_port->local_port;
1211 mall_tc_entry->mirror.ingress = ingress;
1212 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1213
1214 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1215 err = mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1216 if (err)
1217 goto err_mirror_add;
1218 return 0;
1219
1220 err_mirror_add:
1221 list_del(&mall_tc_entry->list);
1222 kfree(mall_tc_entry);
1223 return err;
1224 }
1225
1226 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1227 __be16 protocol,
1228 struct tc_cls_matchall_offload *cls,
1229 bool ingress)
1230 {
1231 const struct tc_action *a;
1232 LIST_HEAD(actions);
1233 int err;
1234
1235 if (!tc_single_action(cls->exts)) {
1236 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1237 return -ENOTSUPP;
1238 }
1239
1240 tcf_exts_to_list(cls->exts, &actions);
1241 list_for_each_entry(a, &actions, list) {
1242 if (!is_tcf_mirred_egress_mirror(a) ||
1243 protocol != htons(ETH_P_ALL)) {
1244 return -ENOTSUPP;
1245 }
1246
1247 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port, cls,
1248 a, ingress);
1249 if (err)
1250 return err;
1251 }
1252
1253 return 0;
1254 }
1255
1256 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1257 struct tc_cls_matchall_offload *cls)
1258 {
1259 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1260 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1261 enum mlxsw_sp_span_type span_type;
1262 struct mlxsw_sp_port *to_port;
1263
1264 mall_tc_entry = mlxsw_sp_port_mirror_entry_find(mlxsw_sp_port,
1265 cls->cookie);
1266 if (!mall_tc_entry) {
1267 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1268 return;
1269 }
1270
1271 switch (mall_tc_entry->type) {
1272 case MLXSW_SP_PORT_MALL_MIRROR:
1273 to_port = mlxsw_sp->ports[mall_tc_entry->mirror.to_local_port];
1274 span_type = mall_tc_entry->mirror.ingress ?
1275 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1276
1277 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
1278 break;
1279 default:
1280 WARN_ON(1);
1281 }
1282
1283 list_del(&mall_tc_entry->list);
1284 kfree(mall_tc_entry);
1285 }
1286
1287 static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
1288 __be16 proto, struct tc_to_netdev *tc)
1289 {
1290 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1291 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1292
1293 if (tc->type == TC_SETUP_MATCHALL) {
1294 switch (tc->cls_mall->command) {
1295 case TC_CLSMATCHALL_REPLACE:
1296 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1297 proto,
1298 tc->cls_mall,
1299 ingress);
1300 case TC_CLSMATCHALL_DESTROY:
1301 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1302 tc->cls_mall);
1303 return 0;
1304 default:
1305 return -EINVAL;
1306 }
1307 }
1308
1309 return -ENOTSUPP;
1310 }
1311
1312 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1313 .ndo_open = mlxsw_sp_port_open,
1314 .ndo_stop = mlxsw_sp_port_stop,
1315 .ndo_start_xmit = mlxsw_sp_port_xmit,
1316 .ndo_setup_tc = mlxsw_sp_setup_tc,
1317 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
1318 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1319 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1320 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
1321 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1322 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
1323 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1324 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1325 .ndo_neigh_construct = mlxsw_sp_router_neigh_construct,
1326 .ndo_neigh_destroy = mlxsw_sp_router_neigh_destroy,
1327 .ndo_fdb_add = switchdev_port_fdb_add,
1328 .ndo_fdb_del = switchdev_port_fdb_del,
1329 .ndo_fdb_dump = switchdev_port_fdb_dump,
1330 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
1331 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
1332 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
1333 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
1334 };
1335
1336 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1337 struct ethtool_drvinfo *drvinfo)
1338 {
1339 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1340 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1341
1342 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1343 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1344 sizeof(drvinfo->version));
1345 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1346 "%d.%d.%d",
1347 mlxsw_sp->bus_info->fw_rev.major,
1348 mlxsw_sp->bus_info->fw_rev.minor,
1349 mlxsw_sp->bus_info->fw_rev.subminor);
1350 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1351 sizeof(drvinfo->bus_info));
1352 }
1353
1354 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1355 struct ethtool_pauseparam *pause)
1356 {
1357 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1358
1359 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1360 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1361 }
1362
1363 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1364 struct ethtool_pauseparam *pause)
1365 {
1366 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1367
1368 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1369 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1370 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1371
1372 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1373 pfcc_pl);
1374 }
1375
1376 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1377 struct ethtool_pauseparam *pause)
1378 {
1379 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1380 bool pause_en = pause->tx_pause || pause->rx_pause;
1381 int err;
1382
1383 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1384 netdev_err(dev, "PFC already enabled on port\n");
1385 return -EINVAL;
1386 }
1387
1388 if (pause->autoneg) {
1389 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1390 return -EINVAL;
1391 }
1392
1393 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1394 if (err) {
1395 netdev_err(dev, "Failed to configure port's headroom\n");
1396 return err;
1397 }
1398
1399 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1400 if (err) {
1401 netdev_err(dev, "Failed to set PAUSE parameters\n");
1402 goto err_port_pause_configure;
1403 }
1404
1405 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1406 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1407
1408 return 0;
1409
1410 err_port_pause_configure:
1411 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1412 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1413 return err;
1414 }
1415
1416 struct mlxsw_sp_port_hw_stats {
1417 char str[ETH_GSTRING_LEN];
1418 u64 (*getter)(const char *payload);
1419 };
1420
1421 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1422 {
1423 .str = "a_frames_transmitted_ok",
1424 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1425 },
1426 {
1427 .str = "a_frames_received_ok",
1428 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1429 },
1430 {
1431 .str = "a_frame_check_sequence_errors",
1432 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1433 },
1434 {
1435 .str = "a_alignment_errors",
1436 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1437 },
1438 {
1439 .str = "a_octets_transmitted_ok",
1440 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1441 },
1442 {
1443 .str = "a_octets_received_ok",
1444 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1445 },
1446 {
1447 .str = "a_multicast_frames_xmitted_ok",
1448 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1449 },
1450 {
1451 .str = "a_broadcast_frames_xmitted_ok",
1452 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1453 },
1454 {
1455 .str = "a_multicast_frames_received_ok",
1456 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1457 },
1458 {
1459 .str = "a_broadcast_frames_received_ok",
1460 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1461 },
1462 {
1463 .str = "a_in_range_length_errors",
1464 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1465 },
1466 {
1467 .str = "a_out_of_range_length_field",
1468 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1469 },
1470 {
1471 .str = "a_frame_too_long_errors",
1472 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1473 },
1474 {
1475 .str = "a_symbol_error_during_carrier",
1476 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1477 },
1478 {
1479 .str = "a_mac_control_frames_transmitted",
1480 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1481 },
1482 {
1483 .str = "a_mac_control_frames_received",
1484 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1485 },
1486 {
1487 .str = "a_unsupported_opcodes_received",
1488 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1489 },
1490 {
1491 .str = "a_pause_mac_ctrl_frames_received",
1492 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1493 },
1494 {
1495 .str = "a_pause_mac_ctrl_frames_xmitted",
1496 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1497 },
1498 };
1499
1500 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1501
1502 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1503 {
1504 .str = "rx_octets_prio",
1505 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1506 },
1507 {
1508 .str = "rx_frames_prio",
1509 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1510 },
1511 {
1512 .str = "tx_octets_prio",
1513 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1514 },
1515 {
1516 .str = "tx_frames_prio",
1517 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1518 },
1519 {
1520 .str = "rx_pause_prio",
1521 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1522 },
1523 {
1524 .str = "rx_pause_duration_prio",
1525 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1526 },
1527 {
1528 .str = "tx_pause_prio",
1529 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1530 },
1531 {
1532 .str = "tx_pause_duration_prio",
1533 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1534 },
1535 };
1536
1537 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1538
1539 static u64 mlxsw_reg_ppcnt_tc_transmit_queue_bytes_get(const char *ppcnt_pl)
1540 {
1541 u64 transmit_queue = mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1542
1543 return MLXSW_SP_CELLS_TO_BYTES(transmit_queue);
1544 }
1545
1546 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1547 {
1548 .str = "tc_transmit_queue_tc",
1549 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_bytes_get,
1550 },
1551 {
1552 .str = "tc_no_buffer_discard_uc_tc",
1553 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1554 },
1555 };
1556
1557 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1558
1559 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
1560 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1561 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
1562 IEEE_8021QAZ_MAX_TCS)
1563
1564 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1565 {
1566 int i;
1567
1568 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1569 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1570 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1571 *p += ETH_GSTRING_LEN;
1572 }
1573 }
1574
1575 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1576 {
1577 int i;
1578
1579 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1580 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1581 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1582 *p += ETH_GSTRING_LEN;
1583 }
1584 }
1585
1586 static void mlxsw_sp_port_get_strings(struct net_device *dev,
1587 u32 stringset, u8 *data)
1588 {
1589 u8 *p = data;
1590 int i;
1591
1592 switch (stringset) {
1593 case ETH_SS_STATS:
1594 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1595 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1596 ETH_GSTRING_LEN);
1597 p += ETH_GSTRING_LEN;
1598 }
1599
1600 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1601 mlxsw_sp_port_get_prio_strings(&p, i);
1602
1603 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1604 mlxsw_sp_port_get_tc_strings(&p, i);
1605
1606 break;
1607 }
1608 }
1609
1610 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1611 enum ethtool_phys_id_state state)
1612 {
1613 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1614 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1615 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1616 bool active;
1617
1618 switch (state) {
1619 case ETHTOOL_ID_ACTIVE:
1620 active = true;
1621 break;
1622 case ETHTOOL_ID_INACTIVE:
1623 active = false;
1624 break;
1625 default:
1626 return -EOPNOTSUPP;
1627 }
1628
1629 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1630 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1631 }
1632
1633 static int
1634 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
1635 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
1636 {
1637 switch (grp) {
1638 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
1639 *p_hw_stats = mlxsw_sp_port_hw_stats;
1640 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
1641 break;
1642 case MLXSW_REG_PPCNT_PRIO_CNT:
1643 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
1644 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1645 break;
1646 case MLXSW_REG_PPCNT_TC_CNT:
1647 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
1648 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
1649 break;
1650 default:
1651 WARN_ON(1);
1652 return -ENOTSUPP;
1653 }
1654 return 0;
1655 }
1656
1657 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
1658 enum mlxsw_reg_ppcnt_grp grp, int prio,
1659 u64 *data, int data_index)
1660 {
1661 struct mlxsw_sp_port_hw_stats *hw_stats;
1662 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1663 int i, len;
1664 int err;
1665
1666 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
1667 if (err)
1668 return;
1669 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
1670 for (i = 0; i < len; i++)
1671 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
1672 }
1673
1674 static void mlxsw_sp_port_get_stats(struct net_device *dev,
1675 struct ethtool_stats *stats, u64 *data)
1676 {
1677 int i, data_index = 0;
1678
1679 /* IEEE 802.3 Counters */
1680 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
1681 data, data_index);
1682 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
1683
1684 /* Per-Priority Counters */
1685 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1686 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
1687 data, data_index);
1688 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1689 }
1690
1691 /* Per-TC Counters */
1692 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1693 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
1694 data, data_index);
1695 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
1696 }
1697 }
1698
1699 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1700 {
1701 switch (sset) {
1702 case ETH_SS_STATS:
1703 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
1704 default:
1705 return -EOPNOTSUPP;
1706 }
1707 }
1708
1709 struct mlxsw_sp_port_link_mode {
1710 enum ethtool_link_mode_bit_indices mask_ethtool;
1711 u32 mask;
1712 u32 speed;
1713 };
1714
1715 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1716 {
1717 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1718 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1719 .speed = SPEED_100,
1720 },
1721 {
1722 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1723 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1724 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1725 .speed = SPEED_1000,
1726 },
1727 {
1728 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1729 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1730 .speed = SPEED_10000,
1731 },
1732 {
1733 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1734 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1735 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
1736 .speed = SPEED_10000,
1737 },
1738 {
1739 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1740 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1741 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1742 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1743 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1744 .speed = SPEED_10000,
1745 },
1746 {
1747 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1748 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
1749 .speed = SPEED_20000,
1750 },
1751 {
1752 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1753 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1754 .speed = SPEED_40000,
1755 },
1756 {
1757 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1758 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1759 .speed = SPEED_40000,
1760 },
1761 {
1762 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1763 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1764 .speed = SPEED_40000,
1765 },
1766 {
1767 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1768 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1769 .speed = SPEED_40000,
1770 },
1771 {
1772 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
1773 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1774 .speed = SPEED_25000,
1775 },
1776 {
1777 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
1778 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1779 .speed = SPEED_25000,
1780 },
1781 {
1782 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1783 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1784 .speed = SPEED_25000,
1785 },
1786 {
1787 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1788 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1789 .speed = SPEED_25000,
1790 },
1791 {
1792 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
1793 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1794 .speed = SPEED_50000,
1795 },
1796 {
1797 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1798 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1799 .speed = SPEED_50000,
1800 },
1801 {
1802 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
1803 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1804 .speed = SPEED_50000,
1805 },
1806 {
1807 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1808 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
1809 .speed = SPEED_56000,
1810 },
1811 {
1812 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1813 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
1814 .speed = SPEED_56000,
1815 },
1816 {
1817 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1818 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
1819 .speed = SPEED_56000,
1820 },
1821 {
1822 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1823 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
1824 .speed = SPEED_56000,
1825 },
1826 {
1827 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
1828 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
1829 .speed = SPEED_100000,
1830 },
1831 {
1832 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
1833 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1834 .speed = SPEED_100000,
1835 },
1836 {
1837 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
1838 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
1839 .speed = SPEED_100000,
1840 },
1841 {
1842 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1843 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
1844 .speed = SPEED_100000,
1845 },
1846 };
1847
1848 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1849
1850 static void
1851 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
1852 struct ethtool_link_ksettings *cmd)
1853 {
1854 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1855 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1856 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1857 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1858 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1859 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1860 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
1861
1862 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1863 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1864 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1865 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1866 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1867 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
1868 }
1869
1870 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
1871 {
1872 int i;
1873
1874 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1875 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1876 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
1877 mode);
1878 }
1879 }
1880
1881 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1882 struct ethtool_link_ksettings *cmd)
1883 {
1884 u32 speed = SPEED_UNKNOWN;
1885 u8 duplex = DUPLEX_UNKNOWN;
1886 int i;
1887
1888 if (!carrier_ok)
1889 goto out;
1890
1891 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1892 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1893 speed = mlxsw_sp_port_link_mode[i].speed;
1894 duplex = DUPLEX_FULL;
1895 break;
1896 }
1897 }
1898 out:
1899 cmd->base.speed = speed;
1900 cmd->base.duplex = duplex;
1901 }
1902
1903 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1904 {
1905 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1906 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1907 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1908 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1909 return PORT_FIBRE;
1910
1911 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1912 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1913 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1914 return PORT_DA;
1915
1916 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1917 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1918 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1919 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1920 return PORT_NONE;
1921
1922 return PORT_OTHER;
1923 }
1924
1925 static u32
1926 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
1927 {
1928 u32 ptys_proto = 0;
1929 int i;
1930
1931 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1932 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
1933 cmd->link_modes.advertising))
1934 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1935 }
1936 return ptys_proto;
1937 }
1938
1939 static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1940 {
1941 u32 ptys_proto = 0;
1942 int i;
1943
1944 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1945 if (speed == mlxsw_sp_port_link_mode[i].speed)
1946 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1947 }
1948 return ptys_proto;
1949 }
1950
1951 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1952 {
1953 u32 ptys_proto = 0;
1954 int i;
1955
1956 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1957 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1958 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1959 }
1960 return ptys_proto;
1961 }
1962
1963 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
1964 struct ethtool_link_ksettings *cmd)
1965 {
1966 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
1967 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
1968 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
1969
1970 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
1971 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
1972 }
1973
1974 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
1975 struct ethtool_link_ksettings *cmd)
1976 {
1977 if (!autoneg)
1978 return;
1979
1980 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
1981 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
1982 }
1983
1984 static void
1985 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
1986 struct ethtool_link_ksettings *cmd)
1987 {
1988 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
1989 return;
1990
1991 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
1992 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
1993 }
1994
1995 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
1996 struct ethtool_link_ksettings *cmd)
1997 {
1998 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
1999 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2000 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2001 char ptys_pl[MLXSW_REG_PTYS_LEN];
2002 u8 autoneg_status;
2003 bool autoneg;
2004 int err;
2005
2006 autoneg = mlxsw_sp_port->link.autoneg;
2007 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
2008 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2009 if (err)
2010 return err;
2011 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2012 &eth_proto_oper);
2013
2014 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2015
2016 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2017
2018 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2019 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2020 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2021
2022 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2023 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2024 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2025 cmd);
2026
2027 return 0;
2028 }
2029
2030 static int
2031 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2032 const struct ethtool_link_ksettings *cmd)
2033 {
2034 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2035 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2036 char ptys_pl[MLXSW_REG_PTYS_LEN];
2037 u32 eth_proto_cap, eth_proto_new;
2038 bool autoneg;
2039 int err;
2040
2041 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
2042 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2043 if (err)
2044 return err;
2045 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
2046
2047 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2048 eth_proto_new = autoneg ?
2049 mlxsw_sp_to_ptys_advert_link(cmd) :
2050 mlxsw_sp_to_ptys_speed(cmd->base.speed);
2051
2052 eth_proto_new = eth_proto_new & eth_proto_cap;
2053 if (!eth_proto_new) {
2054 netdev_err(dev, "No supported speed requested\n");
2055 return -EINVAL;
2056 }
2057
2058 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2059 eth_proto_new);
2060 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2061 if (err)
2062 return err;
2063
2064 if (!netif_running(dev))
2065 return 0;
2066
2067 mlxsw_sp_port->link.autoneg = autoneg;
2068
2069 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2070 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
2071
2072 return 0;
2073 }
2074
2075 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2076 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2077 .get_link = ethtool_op_get_link,
2078 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2079 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
2080 .get_strings = mlxsw_sp_port_get_strings,
2081 .set_phys_id = mlxsw_sp_port_set_phys_id,
2082 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2083 .get_sset_count = mlxsw_sp_port_get_sset_count,
2084 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2085 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
2086 };
2087
2088 static int
2089 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2090 {
2091 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2092 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2093 char ptys_pl[MLXSW_REG_PTYS_LEN];
2094 u32 eth_proto_admin;
2095
2096 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
2097 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2098 eth_proto_admin);
2099 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2100 }
2101
2102 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2103 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2104 bool dwrr, u8 dwrr_weight)
2105 {
2106 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2107 char qeec_pl[MLXSW_REG_QEEC_LEN];
2108
2109 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2110 next_index);
2111 mlxsw_reg_qeec_de_set(qeec_pl, true);
2112 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2113 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2114 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2115 }
2116
2117 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2118 enum mlxsw_reg_qeec_hr hr, u8 index,
2119 u8 next_index, u32 maxrate)
2120 {
2121 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2122 char qeec_pl[MLXSW_REG_QEEC_LEN];
2123
2124 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2125 next_index);
2126 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2127 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2128 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2129 }
2130
2131 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2132 u8 switch_prio, u8 tclass)
2133 {
2134 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2135 char qtct_pl[MLXSW_REG_QTCT_LEN];
2136
2137 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2138 tclass);
2139 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2140 }
2141
2142 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2143 {
2144 int err, i;
2145
2146 /* Setup the elements hierarcy, so that each TC is linked to
2147 * one subgroup, which are all member in the same group.
2148 */
2149 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2150 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2151 0);
2152 if (err)
2153 return err;
2154 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2155 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2156 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2157 0, false, 0);
2158 if (err)
2159 return err;
2160 }
2161 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2162 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2163 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2164 false, 0);
2165 if (err)
2166 return err;
2167 }
2168
2169 /* Make sure the max shaper is disabled in all hierarcies that
2170 * support it.
2171 */
2172 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2173 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2174 MLXSW_REG_QEEC_MAS_DIS);
2175 if (err)
2176 return err;
2177 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2178 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2179 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2180 i, 0,
2181 MLXSW_REG_QEEC_MAS_DIS);
2182 if (err)
2183 return err;
2184 }
2185 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2186 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2187 MLXSW_REG_QEEC_HIERARCY_TC,
2188 i, i,
2189 MLXSW_REG_QEEC_MAS_DIS);
2190 if (err)
2191 return err;
2192 }
2193
2194 /* Map all priorities to traffic class 0. */
2195 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2196 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2197 if (err)
2198 return err;
2199 }
2200
2201 return 0;
2202 }
2203
2204 static int mlxsw_sp_port_pvid_vport_create(struct mlxsw_sp_port *mlxsw_sp_port)
2205 {
2206 mlxsw_sp_port->pvid = 1;
2207
2208 return mlxsw_sp_port_add_vid(mlxsw_sp_port->dev, 0, 1);
2209 }
2210
2211 static int mlxsw_sp_port_pvid_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_port)
2212 {
2213 return mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
2214 }
2215
2216 static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2217 bool split, u8 module, u8 width, u8 lane)
2218 {
2219 struct mlxsw_sp_port *mlxsw_sp_port;
2220 struct net_device *dev;
2221 size_t bytes;
2222 int err;
2223
2224 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2225 if (!dev)
2226 return -ENOMEM;
2227 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
2228 mlxsw_sp_port = netdev_priv(dev);
2229 mlxsw_sp_port->dev = dev;
2230 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2231 mlxsw_sp_port->local_port = local_port;
2232 mlxsw_sp_port->split = split;
2233 mlxsw_sp_port->mapping.module = module;
2234 mlxsw_sp_port->mapping.width = width;
2235 mlxsw_sp_port->mapping.lane = lane;
2236 mlxsw_sp_port->link.autoneg = 1;
2237 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
2238 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
2239 if (!mlxsw_sp_port->active_vlans) {
2240 err = -ENOMEM;
2241 goto err_port_active_vlans_alloc;
2242 }
2243 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
2244 if (!mlxsw_sp_port->untagged_vlans) {
2245 err = -ENOMEM;
2246 goto err_port_untagged_vlans_alloc;
2247 }
2248 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
2249 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
2250
2251 mlxsw_sp_port->pcpu_stats =
2252 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2253 if (!mlxsw_sp_port->pcpu_stats) {
2254 err = -ENOMEM;
2255 goto err_alloc_stats;
2256 }
2257
2258 mlxsw_sp_port->hw_stats.cache =
2259 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2260
2261 if (!mlxsw_sp_port->hw_stats.cache) {
2262 err = -ENOMEM;
2263 goto err_alloc_hw_stats;
2264 }
2265 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2266 &update_stats_cache);
2267
2268 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2269 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2270
2271 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2272 if (err) {
2273 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2274 mlxsw_sp_port->local_port);
2275 goto err_port_swid_set;
2276 }
2277
2278 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2279 if (err) {
2280 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2281 mlxsw_sp_port->local_port);
2282 goto err_dev_addr_init;
2283 }
2284
2285 netif_carrier_off(dev);
2286
2287 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
2288 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2289 dev->hw_features |= NETIF_F_HW_TC;
2290
2291 dev->min_mtu = 0;
2292 dev->max_mtu = ETH_MAX_MTU;
2293
2294 /* Each packet needs to have a Tx header (metadata) on top all other
2295 * headers.
2296 */
2297 dev->needed_headroom = MLXSW_TXHDR_LEN;
2298
2299 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2300 if (err) {
2301 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2302 mlxsw_sp_port->local_port);
2303 goto err_port_system_port_mapping_set;
2304 }
2305
2306 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2307 if (err) {
2308 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2309 mlxsw_sp_port->local_port);
2310 goto err_port_speed_by_width_set;
2311 }
2312
2313 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2314 if (err) {
2315 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2316 mlxsw_sp_port->local_port);
2317 goto err_port_mtu_set;
2318 }
2319
2320 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2321 if (err)
2322 goto err_port_admin_status_set;
2323
2324 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2325 if (err) {
2326 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2327 mlxsw_sp_port->local_port);
2328 goto err_port_buffers_init;
2329 }
2330
2331 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2332 if (err) {
2333 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2334 mlxsw_sp_port->local_port);
2335 goto err_port_ets_init;
2336 }
2337
2338 /* ETS and buffers must be initialized before DCB. */
2339 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2340 if (err) {
2341 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2342 mlxsw_sp_port->local_port);
2343 goto err_port_dcb_init;
2344 }
2345
2346 err = mlxsw_sp_port_pvid_vport_create(mlxsw_sp_port);
2347 if (err) {
2348 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create PVID vPort\n",
2349 mlxsw_sp_port->local_port);
2350 goto err_port_pvid_vport_create;
2351 }
2352
2353 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
2354 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
2355 err = register_netdev(dev);
2356 if (err) {
2357 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2358 mlxsw_sp_port->local_port);
2359 goto err_register_netdev;
2360 }
2361
2362 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2363 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2364 module);
2365 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
2366 return 0;
2367
2368 err_register_netdev:
2369 mlxsw_sp->ports[local_port] = NULL;
2370 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
2371 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2372 err_port_pvid_vport_create:
2373 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
2374 err_port_dcb_init:
2375 err_port_ets_init:
2376 err_port_buffers_init:
2377 err_port_admin_status_set:
2378 err_port_mtu_set:
2379 err_port_speed_by_width_set:
2380 err_port_system_port_mapping_set:
2381 err_dev_addr_init:
2382 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2383 err_port_swid_set:
2384 kfree(mlxsw_sp_port->hw_stats.cache);
2385 err_alloc_hw_stats:
2386 free_percpu(mlxsw_sp_port->pcpu_stats);
2387 err_alloc_stats:
2388 kfree(mlxsw_sp_port->untagged_vlans);
2389 err_port_untagged_vlans_alloc:
2390 kfree(mlxsw_sp_port->active_vlans);
2391 err_port_active_vlans_alloc:
2392 free_netdev(dev);
2393 return err;
2394 }
2395
2396 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2397 bool split, u8 module, u8 width, u8 lane)
2398 {
2399 int err;
2400
2401 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2402 if (err) {
2403 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2404 local_port);
2405 return err;
2406 }
2407 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split,
2408 module, width, lane);
2409 if (err)
2410 goto err_port_create;
2411 return 0;
2412
2413 err_port_create:
2414 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2415 return err;
2416 }
2417
2418 static void __mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2419 {
2420 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2421
2422 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
2423 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
2424 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
2425 mlxsw_sp->ports[local_port] = NULL;
2426 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
2427 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2428 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
2429 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2430 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
2431 free_percpu(mlxsw_sp_port->pcpu_stats);
2432 kfree(mlxsw_sp_port->hw_stats.cache);
2433 kfree(mlxsw_sp_port->untagged_vlans);
2434 kfree(mlxsw_sp_port->active_vlans);
2435 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
2436 free_netdev(mlxsw_sp_port->dev);
2437 }
2438
2439 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2440 {
2441 __mlxsw_sp_port_remove(mlxsw_sp, local_port);
2442 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2443 }
2444
2445 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2446 {
2447 return mlxsw_sp->ports[local_port] != NULL;
2448 }
2449
2450 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2451 {
2452 int i;
2453
2454 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
2455 if (mlxsw_sp_port_created(mlxsw_sp, i))
2456 mlxsw_sp_port_remove(mlxsw_sp, i);
2457 kfree(mlxsw_sp->ports);
2458 }
2459
2460 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2461 {
2462 u8 module, width, lane;
2463 size_t alloc_size;
2464 int i;
2465 int err;
2466
2467 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
2468 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2469 if (!mlxsw_sp->ports)
2470 return -ENOMEM;
2471
2472 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
2473 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
2474 &width, &lane);
2475 if (err)
2476 goto err_port_module_info_get;
2477 if (!width)
2478 continue;
2479 mlxsw_sp->port_to_module[i] = module;
2480 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
2481 module, width, lane);
2482 if (err)
2483 goto err_port_create;
2484 }
2485 return 0;
2486
2487 err_port_create:
2488 err_port_module_info_get:
2489 for (i--; i >= 1; i--)
2490 if (mlxsw_sp_port_created(mlxsw_sp, i))
2491 mlxsw_sp_port_remove(mlxsw_sp, i);
2492 kfree(mlxsw_sp->ports);
2493 return err;
2494 }
2495
2496 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
2497 {
2498 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
2499
2500 return local_port - offset;
2501 }
2502
2503 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
2504 u8 module, unsigned int count)
2505 {
2506 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
2507 int err, i;
2508
2509 for (i = 0; i < count; i++) {
2510 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
2511 width, i * width);
2512 if (err)
2513 goto err_port_module_map;
2514 }
2515
2516 for (i = 0; i < count; i++) {
2517 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
2518 if (err)
2519 goto err_port_swid_set;
2520 }
2521
2522 for (i = 0; i < count; i++) {
2523 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
2524 module, width, i * width);
2525 if (err)
2526 goto err_port_create;
2527 }
2528
2529 return 0;
2530
2531 err_port_create:
2532 for (i--; i >= 0; i--)
2533 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2534 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2535 i = count;
2536 err_port_swid_set:
2537 for (i--; i >= 0; i--)
2538 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
2539 MLXSW_PORT_SWID_DISABLED_PORT);
2540 i = count;
2541 err_port_module_map:
2542 for (i--; i >= 0; i--)
2543 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
2544 return err;
2545 }
2546
2547 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
2548 u8 base_port, unsigned int count)
2549 {
2550 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
2551 int i;
2552
2553 /* Split by four means we need to re-create two ports, otherwise
2554 * only one.
2555 */
2556 count = count / 2;
2557
2558 for (i = 0; i < count; i++) {
2559 local_port = base_port + i * 2;
2560 module = mlxsw_sp->port_to_module[local_port];
2561
2562 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
2563 0);
2564 }
2565
2566 for (i = 0; i < count; i++)
2567 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
2568
2569 for (i = 0; i < count; i++) {
2570 local_port = base_port + i * 2;
2571 module = mlxsw_sp->port_to_module[local_port];
2572
2573 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
2574 width, 0);
2575 }
2576 }
2577
2578 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
2579 unsigned int count)
2580 {
2581 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2582 struct mlxsw_sp_port *mlxsw_sp_port;
2583 u8 module, cur_width, base_port;
2584 int i;
2585 int err;
2586
2587 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2588 if (!mlxsw_sp_port) {
2589 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2590 local_port);
2591 return -EINVAL;
2592 }
2593
2594 module = mlxsw_sp_port->mapping.module;
2595 cur_width = mlxsw_sp_port->mapping.width;
2596
2597 if (count != 2 && count != 4) {
2598 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2599 return -EINVAL;
2600 }
2601
2602 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2603 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2604 return -EINVAL;
2605 }
2606
2607 /* Make sure we have enough slave (even) ports for the split. */
2608 if (count == 2) {
2609 base_port = local_port;
2610 if (mlxsw_sp->ports[base_port + 1]) {
2611 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2612 return -EINVAL;
2613 }
2614 } else {
2615 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2616 if (mlxsw_sp->ports[base_port + 1] ||
2617 mlxsw_sp->ports[base_port + 3]) {
2618 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2619 return -EINVAL;
2620 }
2621 }
2622
2623 for (i = 0; i < count; i++)
2624 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2625 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2626
2627 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2628 if (err) {
2629 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2630 goto err_port_split_create;
2631 }
2632
2633 return 0;
2634
2635 err_port_split_create:
2636 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
2637 return err;
2638 }
2639
2640 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
2641 {
2642 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2643 struct mlxsw_sp_port *mlxsw_sp_port;
2644 u8 cur_width, base_port;
2645 unsigned int count;
2646 int i;
2647
2648 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2649 if (!mlxsw_sp_port) {
2650 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2651 local_port);
2652 return -EINVAL;
2653 }
2654
2655 if (!mlxsw_sp_port->split) {
2656 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2657 return -EINVAL;
2658 }
2659
2660 cur_width = mlxsw_sp_port->mapping.width;
2661 count = cur_width == 1 ? 4 : 2;
2662
2663 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2664
2665 /* Determine which ports to remove. */
2666 if (count == 2 && local_port >= base_port + 2)
2667 base_port = base_port + 2;
2668
2669 for (i = 0; i < count; i++)
2670 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2671 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2672
2673 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
2674
2675 return 0;
2676 }
2677
2678 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2679 char *pude_pl, void *priv)
2680 {
2681 struct mlxsw_sp *mlxsw_sp = priv;
2682 struct mlxsw_sp_port *mlxsw_sp_port;
2683 enum mlxsw_reg_pude_oper_status status;
2684 u8 local_port;
2685
2686 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2687 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2688 if (!mlxsw_sp_port)
2689 return;
2690
2691 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2692 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2693 netdev_info(mlxsw_sp_port->dev, "link up\n");
2694 netif_carrier_on(mlxsw_sp_port->dev);
2695 } else {
2696 netdev_info(mlxsw_sp_port->dev, "link down\n");
2697 netif_carrier_off(mlxsw_sp_port->dev);
2698 }
2699 }
2700
2701 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
2702 u8 local_port, void *priv)
2703 {
2704 struct mlxsw_sp *mlxsw_sp = priv;
2705 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2706 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2707
2708 if (unlikely(!mlxsw_sp_port)) {
2709 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2710 local_port);
2711 return;
2712 }
2713
2714 skb->dev = mlxsw_sp_port->dev;
2715
2716 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2717 u64_stats_update_begin(&pcpu_stats->syncp);
2718 pcpu_stats->rx_packets++;
2719 pcpu_stats->rx_bytes += skb->len;
2720 u64_stats_update_end(&pcpu_stats->syncp);
2721
2722 skb->protocol = eth_type_trans(skb, skb->dev);
2723 netif_receive_skb(skb);
2724 }
2725
2726 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
2727 void *priv)
2728 {
2729 skb->offload_fwd_mark = 1;
2730 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
2731 }
2732
2733 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
2734 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
2735 _is_ctrl, SP_##_trap_group, DISCARD)
2736
2737 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
2738 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
2739 _is_ctrl, SP_##_trap_group, DISCARD)
2740
2741 #define MLXSW_SP_EVENTL(_func, _trap_id) \
2742 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
2743
2744 static const struct mlxsw_listener mlxsw_sp_listener[] = {
2745 /* Events */
2746 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
2747 /* L2 traps */
2748 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
2749 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
2750 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
2751 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
2752 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
2753 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
2754 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
2755 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
2756 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
2757 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
2758 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
2759 /* L3 traps */
2760 MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2761 MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2762 MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2763 MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, OSPF, false),
2764 MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
2765 MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
2766 MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, ARP_MISS, false),
2767 MLXSW_SP_RXL_NO_MARK(BGP_IPV4, TRAP_TO_CPU, BGP_IPV4, false),
2768 };
2769
2770 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
2771 {
2772 char qpcr_pl[MLXSW_REG_QPCR_LEN];
2773 enum mlxsw_reg_qpcr_ir_units ir_units;
2774 int max_cpu_policers;
2775 bool is_bytes;
2776 u8 burst_size;
2777 u32 rate;
2778 int i, err;
2779
2780 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
2781 return -EIO;
2782
2783 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
2784
2785 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
2786 for (i = 0; i < max_cpu_policers; i++) {
2787 is_bytes = false;
2788 switch (i) {
2789 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
2790 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
2791 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
2792 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
2793 rate = 128;
2794 burst_size = 7;
2795 break;
2796 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
2797 rate = 16 * 1024;
2798 burst_size = 10;
2799 break;
2800 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
2801 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
2802 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
2803 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
2804 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2805 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
2806 rate = 1024;
2807 burst_size = 7;
2808 break;
2809 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
2810 is_bytes = true;
2811 rate = 4 * 1024;
2812 burst_size = 4;
2813 break;
2814 default:
2815 continue;
2816 }
2817
2818 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
2819 burst_size);
2820 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
2821 if (err)
2822 return err;
2823 }
2824
2825 return 0;
2826 }
2827
2828 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
2829 {
2830 char htgt_pl[MLXSW_REG_HTGT_LEN];
2831 enum mlxsw_reg_htgt_trap_group i;
2832 int max_cpu_policers;
2833 int max_trap_groups;
2834 u8 priority, tc;
2835 u16 policer_id;
2836 int err;
2837
2838 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
2839 return -EIO;
2840
2841 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
2842 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
2843
2844 for (i = 0; i < max_trap_groups; i++) {
2845 policer_id = i;
2846 switch (i) {
2847 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
2848 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
2849 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
2850 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
2851 priority = 5;
2852 tc = 5;
2853 break;
2854 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
2855 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
2856 priority = 4;
2857 tc = 4;
2858 break;
2859 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
2860 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
2861 priority = 3;
2862 tc = 3;
2863 break;
2864 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
2865 priority = 2;
2866 tc = 2;
2867 break;
2868 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
2869 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2870 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
2871 priority = 1;
2872 tc = 1;
2873 break;
2874 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
2875 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
2876 tc = MLXSW_REG_HTGT_DEFAULT_TC;
2877 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
2878 break;
2879 default:
2880 continue;
2881 }
2882
2883 if (max_cpu_policers <= policer_id &&
2884 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
2885 return -EIO;
2886
2887 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
2888 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
2889 if (err)
2890 return err;
2891 }
2892
2893 return 0;
2894 }
2895
2896 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2897 {
2898 int i;
2899 int err;
2900
2901 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
2902 if (err)
2903 return err;
2904
2905 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
2906 if (err)
2907 return err;
2908
2909 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
2910 err = mlxsw_core_trap_register(mlxsw_sp->core,
2911 &mlxsw_sp_listener[i],
2912 mlxsw_sp);
2913 if (err)
2914 goto err_listener_register;
2915
2916 }
2917 return 0;
2918
2919 err_listener_register:
2920 for (i--; i >= 0; i--) {
2921 mlxsw_core_trap_unregister(mlxsw_sp->core,
2922 &mlxsw_sp_listener[i],
2923 mlxsw_sp);
2924 }
2925 return err;
2926 }
2927
2928 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2929 {
2930 int i;
2931
2932 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
2933 mlxsw_core_trap_unregister(mlxsw_sp->core,
2934 &mlxsw_sp_listener[i],
2935 mlxsw_sp);
2936 }
2937 }
2938
2939 static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2940 enum mlxsw_reg_sfgc_type type,
2941 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2942 {
2943 enum mlxsw_flood_table_type table_type;
2944 enum mlxsw_sp_flood_table flood_table;
2945 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2946
2947 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
2948 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
2949 else
2950 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
2951
2952 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2953 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2954 else
2955 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
2956
2957 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2958 flood_table);
2959 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2960 }
2961
2962 static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2963 {
2964 int type, err;
2965
2966 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2967 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2968 continue;
2969
2970 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2971 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2972 if (err)
2973 return err;
2974
2975 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2976 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2977 if (err)
2978 return err;
2979 }
2980
2981 return 0;
2982 }
2983
2984 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2985 {
2986 char slcr_pl[MLXSW_REG_SLCR_LEN];
2987 int err;
2988
2989 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2990 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2991 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2992 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2993 MLXSW_REG_SLCR_LAG_HASH_SIP |
2994 MLXSW_REG_SLCR_LAG_HASH_DIP |
2995 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2996 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2997 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2998 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2999 if (err)
3000 return err;
3001
3002 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3003 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
3004 return -EIO;
3005
3006 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
3007 sizeof(struct mlxsw_sp_upper),
3008 GFP_KERNEL);
3009 if (!mlxsw_sp->lags)
3010 return -ENOMEM;
3011
3012 return 0;
3013 }
3014
3015 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3016 {
3017 kfree(mlxsw_sp->lags);
3018 }
3019
3020 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3021 {
3022 char htgt_pl[MLXSW_REG_HTGT_LEN];
3023
3024 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3025 MLXSW_REG_HTGT_INVALID_POLICER,
3026 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3027 MLXSW_REG_HTGT_DEFAULT_TC);
3028 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3029 }
3030
3031 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3032 const struct mlxsw_bus_info *mlxsw_bus_info)
3033 {
3034 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3035 int err;
3036
3037 mlxsw_sp->core = mlxsw_core;
3038 mlxsw_sp->bus_info = mlxsw_bus_info;
3039 INIT_LIST_HEAD(&mlxsw_sp->fids);
3040 INIT_LIST_HEAD(&mlxsw_sp->vfids.list);
3041 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
3042
3043 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3044 if (err) {
3045 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3046 return err;
3047 }
3048
3049 err = mlxsw_sp_traps_init(mlxsw_sp);
3050 if (err) {
3051 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3052 return err;
3053 }
3054
3055 err = mlxsw_sp_flood_init(mlxsw_sp);
3056 if (err) {
3057 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
3058 goto err_flood_init;
3059 }
3060
3061 err = mlxsw_sp_buffers_init(mlxsw_sp);
3062 if (err) {
3063 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3064 goto err_buffers_init;
3065 }
3066
3067 err = mlxsw_sp_lag_init(mlxsw_sp);
3068 if (err) {
3069 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3070 goto err_lag_init;
3071 }
3072
3073 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3074 if (err) {
3075 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3076 goto err_switchdev_init;
3077 }
3078
3079 err = mlxsw_sp_router_init(mlxsw_sp);
3080 if (err) {
3081 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3082 goto err_router_init;
3083 }
3084
3085 err = mlxsw_sp_span_init(mlxsw_sp);
3086 if (err) {
3087 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3088 goto err_span_init;
3089 }
3090
3091 err = mlxsw_sp_ports_create(mlxsw_sp);
3092 if (err) {
3093 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3094 goto err_ports_create;
3095 }
3096
3097 return 0;
3098
3099 err_ports_create:
3100 mlxsw_sp_span_fini(mlxsw_sp);
3101 err_span_init:
3102 mlxsw_sp_router_fini(mlxsw_sp);
3103 err_router_init:
3104 mlxsw_sp_switchdev_fini(mlxsw_sp);
3105 err_switchdev_init:
3106 mlxsw_sp_lag_fini(mlxsw_sp);
3107 err_lag_init:
3108 mlxsw_sp_buffers_fini(mlxsw_sp);
3109 err_buffers_init:
3110 err_flood_init:
3111 mlxsw_sp_traps_fini(mlxsw_sp);
3112 return err;
3113 }
3114
3115 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
3116 {
3117 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3118
3119 mlxsw_sp_ports_remove(mlxsw_sp);
3120 mlxsw_sp_span_fini(mlxsw_sp);
3121 mlxsw_sp_router_fini(mlxsw_sp);
3122 mlxsw_sp_switchdev_fini(mlxsw_sp);
3123 mlxsw_sp_lag_fini(mlxsw_sp);
3124 mlxsw_sp_buffers_fini(mlxsw_sp);
3125 mlxsw_sp_traps_fini(mlxsw_sp);
3126 WARN_ON(!list_empty(&mlxsw_sp->vfids.list));
3127 WARN_ON(!list_empty(&mlxsw_sp->fids));
3128 }
3129
3130 static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3131 .used_max_vepa_channels = 1,
3132 .max_vepa_channels = 0,
3133 .used_max_mid = 1,
3134 .max_mid = MLXSW_SP_MID_MAX,
3135 .used_max_pgt = 1,
3136 .max_pgt = 0,
3137 .used_flood_tables = 1,
3138 .used_flood_mode = 1,
3139 .flood_mode = 3,
3140 .max_fid_offset_flood_tables = 2,
3141 .fid_offset_flood_table_size = VLAN_N_VID - 1,
3142 .max_fid_flood_tables = 2,
3143 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
3144 .used_max_ib_mc = 1,
3145 .max_ib_mc = 0,
3146 .used_max_pkey = 1,
3147 .max_pkey = 0,
3148 .used_kvd_split_data = 1,
3149 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3150 .kvd_hash_single_parts = 2,
3151 .kvd_hash_double_parts = 1,
3152 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
3153 .swid_config = {
3154 {
3155 .used_type = 1,
3156 .type = MLXSW_PORT_SWID_TYPE_ETH,
3157 }
3158 },
3159 .resource_query_enable = 1,
3160 };
3161
3162 static struct mlxsw_driver mlxsw_sp_driver = {
3163 .kind = mlxsw_sp_driver_name,
3164 .priv_size = sizeof(struct mlxsw_sp),
3165 .init = mlxsw_sp_init,
3166 .fini = mlxsw_sp_fini,
3167 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
3168 .port_split = mlxsw_sp_port_split,
3169 .port_unsplit = mlxsw_sp_port_unsplit,
3170 .sb_pool_get = mlxsw_sp_sb_pool_get,
3171 .sb_pool_set = mlxsw_sp_sb_pool_set,
3172 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3173 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3174 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3175 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3176 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3177 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3178 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3179 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3180 .txhdr_construct = mlxsw_sp_txhdr_construct,
3181 .txhdr_len = MLXSW_TXHDR_LEN,
3182 .profile = &mlxsw_sp_config_profile,
3183 };
3184
3185 static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
3186 {
3187 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3188 }
3189
3190 static int mlxsw_lower_dev_walk(struct net_device *lower_dev, void *data)
3191 {
3192 struct mlxsw_sp_port **port = data;
3193 int ret = 0;
3194
3195 if (mlxsw_sp_port_dev_check(lower_dev)) {
3196 *port = netdev_priv(lower_dev);
3197 ret = 1;
3198 }
3199
3200 return ret;
3201 }
3202
3203 static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
3204 {
3205 struct mlxsw_sp_port *port;
3206
3207 if (mlxsw_sp_port_dev_check(dev))
3208 return netdev_priv(dev);
3209
3210 port = NULL;
3211 netdev_walk_all_lower_dev(dev, mlxsw_lower_dev_walk, &port);
3212
3213 return port;
3214 }
3215
3216 static struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
3217 {
3218 struct mlxsw_sp_port *mlxsw_sp_port;
3219
3220 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3221 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3222 }
3223
3224 static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3225 {
3226 struct mlxsw_sp_port *port;
3227
3228 if (mlxsw_sp_port_dev_check(dev))
3229 return netdev_priv(dev);
3230
3231 port = NULL;
3232 netdev_walk_all_lower_dev_rcu(dev, mlxsw_lower_dev_walk, &port);
3233
3234 return port;
3235 }
3236
3237 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3238 {
3239 struct mlxsw_sp_port *mlxsw_sp_port;
3240
3241 rcu_read_lock();
3242 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3243 if (mlxsw_sp_port)
3244 dev_hold(mlxsw_sp_port->dev);
3245 rcu_read_unlock();
3246 return mlxsw_sp_port;
3247 }
3248
3249 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3250 {
3251 dev_put(mlxsw_sp_port->dev);
3252 }
3253
3254 static bool mlxsw_sp_rif_should_config(struct mlxsw_sp_rif *r,
3255 unsigned long event)
3256 {
3257 switch (event) {
3258 case NETDEV_UP:
3259 if (!r)
3260 return true;
3261 r->ref_count++;
3262 return false;
3263 case NETDEV_DOWN:
3264 if (r && --r->ref_count == 0)
3265 return true;
3266 /* It is possible we already removed the RIF ourselves
3267 * if it was assigned to a netdev that is now a bridge
3268 * or LAG slave.
3269 */
3270 return false;
3271 }
3272
3273 return false;
3274 }
3275
3276 static int mlxsw_sp_avail_rif_get(struct mlxsw_sp *mlxsw_sp)
3277 {
3278 int i;
3279
3280 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++)
3281 if (!mlxsw_sp->rifs[i])
3282 return i;
3283
3284 return MLXSW_SP_INVALID_RIF;
3285 }
3286
3287 static void mlxsw_sp_vport_rif_sp_attr_get(struct mlxsw_sp_port *mlxsw_sp_vport,
3288 bool *p_lagged, u16 *p_system_port)
3289 {
3290 u8 local_port = mlxsw_sp_vport->local_port;
3291
3292 *p_lagged = mlxsw_sp_vport->lagged;
3293 *p_system_port = *p_lagged ? mlxsw_sp_vport->lag_id : local_port;
3294 }
3295
3296 static int mlxsw_sp_vport_rif_sp_op(struct mlxsw_sp_port *mlxsw_sp_vport,
3297 struct net_device *l3_dev, u16 rif,
3298 bool create)
3299 {
3300 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3301 bool lagged = mlxsw_sp_vport->lagged;
3302 char ritr_pl[MLXSW_REG_RITR_LEN];
3303 u16 system_port;
3304
3305 mlxsw_reg_ritr_pack(ritr_pl, create, MLXSW_REG_RITR_SP_IF, rif,
3306 l3_dev->mtu, l3_dev->dev_addr);
3307
3308 mlxsw_sp_vport_rif_sp_attr_get(mlxsw_sp_vport, &lagged, &system_port);
3309 mlxsw_reg_ritr_sp_if_pack(ritr_pl, lagged, system_port,
3310 mlxsw_sp_vport_vid_get(mlxsw_sp_vport));
3311
3312 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3313 }
3314
3315 static void mlxsw_sp_vport_rif_sp_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
3316
3317 static struct mlxsw_sp_fid *
3318 mlxsw_sp_rfid_alloc(u16 fid, struct net_device *l3_dev)
3319 {
3320 struct mlxsw_sp_fid *f;
3321
3322 f = kzalloc(sizeof(*f), GFP_KERNEL);
3323 if (!f)
3324 return NULL;
3325
3326 f->leave = mlxsw_sp_vport_rif_sp_leave;
3327 f->ref_count = 0;
3328 f->dev = l3_dev;
3329 f->fid = fid;
3330
3331 return f;
3332 }
3333
3334 static struct mlxsw_sp_rif *
3335 mlxsw_sp_rif_alloc(u16 rif, struct net_device *l3_dev, struct mlxsw_sp_fid *f)
3336 {
3337 struct mlxsw_sp_rif *r;
3338
3339 r = kzalloc(sizeof(*r), GFP_KERNEL);
3340 if (!r)
3341 return NULL;
3342
3343 ether_addr_copy(r->addr, l3_dev->dev_addr);
3344 r->mtu = l3_dev->mtu;
3345 r->ref_count = 1;
3346 r->dev = l3_dev;
3347 r->rif = rif;
3348 r->f = f;
3349
3350 return r;
3351 }
3352
3353 static struct mlxsw_sp_rif *
3354 mlxsw_sp_vport_rif_sp_create(struct mlxsw_sp_port *mlxsw_sp_vport,
3355 struct net_device *l3_dev)
3356 {
3357 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3358 struct mlxsw_sp_fid *f;
3359 struct mlxsw_sp_rif *r;
3360 u16 fid, rif;
3361 int err;
3362
3363 rif = mlxsw_sp_avail_rif_get(mlxsw_sp);
3364 if (rif == MLXSW_SP_INVALID_RIF)
3365 return ERR_PTR(-ERANGE);
3366
3367 err = mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, true);
3368 if (err)
3369 return ERR_PTR(err);
3370
3371 fid = mlxsw_sp_rif_sp_to_fid(rif);
3372 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, true);
3373 if (err)
3374 goto err_rif_fdb_op;
3375
3376 f = mlxsw_sp_rfid_alloc(fid, l3_dev);
3377 if (!f) {
3378 err = -ENOMEM;
3379 goto err_rfid_alloc;
3380 }
3381
3382 r = mlxsw_sp_rif_alloc(rif, l3_dev, f);
3383 if (!r) {
3384 err = -ENOMEM;
3385 goto err_rif_alloc;
3386 }
3387
3388 f->r = r;
3389 mlxsw_sp->rifs[rif] = r;
3390
3391 return r;
3392
3393 err_rif_alloc:
3394 kfree(f);
3395 err_rfid_alloc:
3396 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, false);
3397 err_rif_fdb_op:
3398 mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, false);
3399 return ERR_PTR(err);
3400 }
3401
3402 static void mlxsw_sp_vport_rif_sp_destroy(struct mlxsw_sp_port *mlxsw_sp_vport,
3403 struct mlxsw_sp_rif *r)
3404 {
3405 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3406 struct net_device *l3_dev = r->dev;
3407 struct mlxsw_sp_fid *f = r->f;
3408 u16 fid = f->fid;
3409 u16 rif = r->rif;
3410
3411 mlxsw_sp->rifs[rif] = NULL;
3412 f->r = NULL;
3413
3414 kfree(r);
3415
3416 kfree(f);
3417
3418 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, false);
3419
3420 mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, false);
3421 }
3422
3423 static int mlxsw_sp_vport_rif_sp_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3424 struct net_device *l3_dev)
3425 {
3426 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3427 struct mlxsw_sp_rif *r;
3428
3429 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, l3_dev);
3430 if (!r) {
3431 r = mlxsw_sp_vport_rif_sp_create(mlxsw_sp_vport, l3_dev);
3432 if (IS_ERR(r))
3433 return PTR_ERR(r);
3434 }
3435
3436 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, r->f);
3437 r->f->ref_count++;
3438
3439 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", r->f->fid);
3440
3441 return 0;
3442 }
3443
3444 static void mlxsw_sp_vport_rif_sp_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
3445 {
3446 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3447
3448 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
3449
3450 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
3451 if (--f->ref_count == 0)
3452 mlxsw_sp_vport_rif_sp_destroy(mlxsw_sp_vport, f->r);
3453 }
3454
3455 static int mlxsw_sp_inetaddr_vport_event(struct net_device *l3_dev,
3456 struct net_device *port_dev,
3457 unsigned long event, u16 vid)
3458 {
3459 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(port_dev);
3460 struct mlxsw_sp_port *mlxsw_sp_vport;
3461
3462 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3463 if (WARN_ON(!mlxsw_sp_vport))
3464 return -EINVAL;
3465
3466 switch (event) {
3467 case NETDEV_UP:
3468 return mlxsw_sp_vport_rif_sp_join(mlxsw_sp_vport, l3_dev);
3469 case NETDEV_DOWN:
3470 mlxsw_sp_vport_rif_sp_leave(mlxsw_sp_vport);
3471 break;
3472 }
3473
3474 return 0;
3475 }
3476
3477 static int mlxsw_sp_inetaddr_port_event(struct net_device *port_dev,
3478 unsigned long event)
3479 {
3480 if (netif_is_bridge_port(port_dev) || netif_is_lag_port(port_dev))
3481 return 0;
3482
3483 return mlxsw_sp_inetaddr_vport_event(port_dev, port_dev, event, 1);
3484 }
3485
3486 static int __mlxsw_sp_inetaddr_lag_event(struct net_device *l3_dev,
3487 struct net_device *lag_dev,
3488 unsigned long event, u16 vid)
3489 {
3490 struct net_device *port_dev;
3491 struct list_head *iter;
3492 int err;
3493
3494 netdev_for_each_lower_dev(lag_dev, port_dev, iter) {
3495 if (mlxsw_sp_port_dev_check(port_dev)) {
3496 err = mlxsw_sp_inetaddr_vport_event(l3_dev, port_dev,
3497 event, vid);
3498 if (err)
3499 return err;
3500 }
3501 }
3502
3503 return 0;
3504 }
3505
3506 static int mlxsw_sp_inetaddr_lag_event(struct net_device *lag_dev,
3507 unsigned long event)
3508 {
3509 if (netif_is_bridge_port(lag_dev))
3510 return 0;
3511
3512 return __mlxsw_sp_inetaddr_lag_event(lag_dev, lag_dev, event, 1);
3513 }
3514
3515 static struct mlxsw_sp_fid *mlxsw_sp_bridge_fid_get(struct mlxsw_sp *mlxsw_sp,
3516 struct net_device *l3_dev)
3517 {
3518 u16 fid;
3519
3520 if (is_vlan_dev(l3_dev))
3521 fid = vlan_dev_vlan_id(l3_dev);
3522 else if (mlxsw_sp->master_bridge.dev == l3_dev)
3523 fid = 1;
3524 else
3525 return mlxsw_sp_vfid_find(mlxsw_sp, l3_dev);
3526
3527 return mlxsw_sp_fid_find(mlxsw_sp, fid);
3528 }
3529
3530 static enum mlxsw_flood_table_type mlxsw_sp_flood_table_type_get(u16 fid)
3531 {
3532 return mlxsw_sp_fid_is_vfid(fid) ? MLXSW_REG_SFGC_TABLE_TYPE_FID :
3533 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
3534 }
3535
3536 static u16 mlxsw_sp_flood_table_index_get(u16 fid)
3537 {
3538 return mlxsw_sp_fid_is_vfid(fid) ? mlxsw_sp_fid_to_vfid(fid) : fid;
3539 }
3540
3541 static int mlxsw_sp_router_port_flood_set(struct mlxsw_sp *mlxsw_sp, u16 fid,
3542 bool set)
3543 {
3544 enum mlxsw_flood_table_type table_type;
3545 char *sftr_pl;
3546 u16 index;
3547 int err;
3548
3549 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
3550 if (!sftr_pl)
3551 return -ENOMEM;
3552
3553 table_type = mlxsw_sp_flood_table_type_get(fid);
3554 index = mlxsw_sp_flood_table_index_get(fid);
3555 mlxsw_reg_sftr_pack(sftr_pl, MLXSW_SP_FLOOD_TABLE_BM, index, table_type,
3556 1, MLXSW_PORT_ROUTER_PORT, set);
3557 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sftr), sftr_pl);
3558
3559 kfree(sftr_pl);
3560 return err;
3561 }
3562
3563 static enum mlxsw_reg_ritr_if_type mlxsw_sp_rif_type_get(u16 fid)
3564 {
3565 if (mlxsw_sp_fid_is_vfid(fid))
3566 return MLXSW_REG_RITR_FID_IF;
3567 else
3568 return MLXSW_REG_RITR_VLAN_IF;
3569 }
3570
3571 static int mlxsw_sp_rif_bridge_op(struct mlxsw_sp *mlxsw_sp,
3572 struct net_device *l3_dev,
3573 u16 fid, u16 rif,
3574 bool create)
3575 {
3576 enum mlxsw_reg_ritr_if_type rif_type;
3577 char ritr_pl[MLXSW_REG_RITR_LEN];
3578
3579 rif_type = mlxsw_sp_rif_type_get(fid);
3580 mlxsw_reg_ritr_pack(ritr_pl, create, rif_type, rif, l3_dev->mtu,
3581 l3_dev->dev_addr);
3582 mlxsw_reg_ritr_fid_set(ritr_pl, rif_type, fid);
3583
3584 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3585 }
3586
3587 static int mlxsw_sp_rif_bridge_create(struct mlxsw_sp *mlxsw_sp,
3588 struct net_device *l3_dev,
3589 struct mlxsw_sp_fid *f)
3590 {
3591 struct mlxsw_sp_rif *r;
3592 u16 rif;
3593 int err;
3594
3595 rif = mlxsw_sp_avail_rif_get(mlxsw_sp);
3596 if (rif == MLXSW_SP_INVALID_RIF)
3597 return -ERANGE;
3598
3599 err = mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, true);
3600 if (err)
3601 return err;
3602
3603 err = mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, true);
3604 if (err)
3605 goto err_rif_bridge_op;
3606
3607 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, true);
3608 if (err)
3609 goto err_rif_fdb_op;
3610
3611 r = mlxsw_sp_rif_alloc(rif, l3_dev, f);
3612 if (!r) {
3613 err = -ENOMEM;
3614 goto err_rif_alloc;
3615 }
3616
3617 f->r = r;
3618 mlxsw_sp->rifs[rif] = r;
3619
3620 netdev_dbg(l3_dev, "RIF=%d created\n", rif);
3621
3622 return 0;
3623
3624 err_rif_alloc:
3625 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, false);
3626 err_rif_fdb_op:
3627 mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, false);
3628 err_rif_bridge_op:
3629 mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, false);
3630 return err;
3631 }
3632
3633 void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp *mlxsw_sp,
3634 struct mlxsw_sp_rif *r)
3635 {
3636 struct net_device *l3_dev = r->dev;
3637 struct mlxsw_sp_fid *f = r->f;
3638 u16 rif = r->rif;
3639
3640 mlxsw_sp->rifs[rif] = NULL;
3641 f->r = NULL;
3642
3643 kfree(r);
3644
3645 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, false);
3646
3647 mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, false);
3648
3649 mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, false);
3650
3651 netdev_dbg(l3_dev, "RIF=%d destroyed\n", rif);
3652 }
3653
3654 static int mlxsw_sp_inetaddr_bridge_event(struct net_device *l3_dev,
3655 struct net_device *br_dev,
3656 unsigned long event)
3657 {
3658 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(l3_dev);
3659 struct mlxsw_sp_fid *f;
3660
3661 /* FID can either be an actual FID if the L3 device is the
3662 * VLAN-aware bridge or a VLAN device on top. Otherwise, the
3663 * L3 device is a VLAN-unaware bridge and we get a vFID.
3664 */
3665 f = mlxsw_sp_bridge_fid_get(mlxsw_sp, l3_dev);
3666 if (WARN_ON(!f))
3667 return -EINVAL;
3668
3669 switch (event) {
3670 case NETDEV_UP:
3671 return mlxsw_sp_rif_bridge_create(mlxsw_sp, l3_dev, f);
3672 case NETDEV_DOWN:
3673 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
3674 break;
3675 }
3676
3677 return 0;
3678 }
3679
3680 static int mlxsw_sp_inetaddr_vlan_event(struct net_device *vlan_dev,
3681 unsigned long event)
3682 {
3683 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3684 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
3685 u16 vid = vlan_dev_vlan_id(vlan_dev);
3686
3687 if (mlxsw_sp_port_dev_check(real_dev))
3688 return mlxsw_sp_inetaddr_vport_event(vlan_dev, real_dev, event,
3689 vid);
3690 else if (netif_is_lag_master(real_dev))
3691 return __mlxsw_sp_inetaddr_lag_event(vlan_dev, real_dev, event,
3692 vid);
3693 else if (netif_is_bridge_master(real_dev) &&
3694 mlxsw_sp->master_bridge.dev == real_dev)
3695 return mlxsw_sp_inetaddr_bridge_event(vlan_dev, real_dev,
3696 event);
3697
3698 return 0;
3699 }
3700
3701 static int mlxsw_sp_inetaddr_event(struct notifier_block *unused,
3702 unsigned long event, void *ptr)
3703 {
3704 struct in_ifaddr *ifa = (struct in_ifaddr *) ptr;
3705 struct net_device *dev = ifa->ifa_dev->dev;
3706 struct mlxsw_sp *mlxsw_sp;
3707 struct mlxsw_sp_rif *r;
3708 int err = 0;
3709
3710 mlxsw_sp = mlxsw_sp_lower_get(dev);
3711 if (!mlxsw_sp)
3712 goto out;
3713
3714 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, dev);
3715 if (!mlxsw_sp_rif_should_config(r, event))
3716 goto out;
3717
3718 if (mlxsw_sp_port_dev_check(dev))
3719 err = mlxsw_sp_inetaddr_port_event(dev, event);
3720 else if (netif_is_lag_master(dev))
3721 err = mlxsw_sp_inetaddr_lag_event(dev, event);
3722 else if (netif_is_bridge_master(dev))
3723 err = mlxsw_sp_inetaddr_bridge_event(dev, dev, event);
3724 else if (is_vlan_dev(dev))
3725 err = mlxsw_sp_inetaddr_vlan_event(dev, event);
3726
3727 out:
3728 return notifier_from_errno(err);
3729 }
3730
3731 static int mlxsw_sp_rif_edit(struct mlxsw_sp *mlxsw_sp, u16 rif,
3732 const char *mac, int mtu)
3733 {
3734 char ritr_pl[MLXSW_REG_RITR_LEN];
3735 int err;
3736
3737 mlxsw_reg_ritr_rif_pack(ritr_pl, rif);
3738 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3739 if (err)
3740 return err;
3741
3742 mlxsw_reg_ritr_mtu_set(ritr_pl, mtu);
3743 mlxsw_reg_ritr_if_mac_memcpy_to(ritr_pl, mac);
3744 mlxsw_reg_ritr_op_set(ritr_pl, MLXSW_REG_RITR_RIF_CREATE);
3745 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3746 }
3747
3748 static int mlxsw_sp_netdevice_router_port_event(struct net_device *dev)
3749 {
3750 struct mlxsw_sp *mlxsw_sp;
3751 struct mlxsw_sp_rif *r;
3752 int err;
3753
3754 mlxsw_sp = mlxsw_sp_lower_get(dev);
3755 if (!mlxsw_sp)
3756 return 0;
3757
3758 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, dev);
3759 if (!r)
3760 return 0;
3761
3762 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, false);
3763 if (err)
3764 return err;
3765
3766 err = mlxsw_sp_rif_edit(mlxsw_sp, r->rif, dev->dev_addr, dev->mtu);
3767 if (err)
3768 goto err_rif_edit;
3769
3770 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, dev->dev_addr, r->f->fid, true);
3771 if (err)
3772 goto err_rif_fdb_op;
3773
3774 ether_addr_copy(r->addr, dev->dev_addr);
3775 r->mtu = dev->mtu;
3776
3777 netdev_dbg(dev, "Updated RIF=%d\n", r->rif);
3778
3779 return 0;
3780
3781 err_rif_fdb_op:
3782 mlxsw_sp_rif_edit(mlxsw_sp, r->rif, r->addr, r->mtu);
3783 err_rif_edit:
3784 mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, true);
3785 return err;
3786 }
3787
3788 static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
3789 u16 fid)
3790 {
3791 if (mlxsw_sp_fid_is_vfid(fid))
3792 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
3793 else
3794 return test_bit(fid, lag_port->active_vlans);
3795 }
3796
3797 static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
3798 u16 fid)
3799 {
3800 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3801 u8 local_port = mlxsw_sp_port->local_port;
3802 u16 lag_id = mlxsw_sp_port->lag_id;
3803 u64 max_lag_members;
3804 int i, count = 0;
3805
3806 if (!mlxsw_sp_port->lagged)
3807 return true;
3808
3809 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3810 MAX_LAG_MEMBERS);
3811 for (i = 0; i < max_lag_members; i++) {
3812 struct mlxsw_sp_port *lag_port;
3813
3814 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
3815 if (!lag_port || lag_port->local_port == local_port)
3816 continue;
3817 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
3818 count++;
3819 }
3820
3821 return !count;
3822 }
3823
3824 static int
3825 mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3826 u16 fid)
3827 {
3828 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3829 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3830
3831 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
3832 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3833 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
3834 mlxsw_sp_port->local_port);
3835
3836 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
3837 mlxsw_sp_port->local_port, fid);
3838
3839 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3840 }
3841
3842 static int
3843 mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3844 u16 fid)
3845 {
3846 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3847 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3848
3849 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
3850 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3851 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
3852
3853 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
3854 mlxsw_sp_port->lag_id, fid);
3855
3856 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3857 }
3858
3859 int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
3860 {
3861 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
3862 return 0;
3863
3864 if (mlxsw_sp_port->lagged)
3865 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
3866 fid);
3867 else
3868 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
3869 }
3870
3871 static void mlxsw_sp_master_bridge_gone_sync(struct mlxsw_sp *mlxsw_sp)
3872 {
3873 struct mlxsw_sp_fid *f, *tmp;
3874
3875 list_for_each_entry_safe(f, tmp, &mlxsw_sp->fids, list)
3876 if (--f->ref_count == 0)
3877 mlxsw_sp_fid_destroy(mlxsw_sp, f);
3878 else
3879 WARN_ON_ONCE(1);
3880 }
3881
3882 static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
3883 struct net_device *br_dev)
3884 {
3885 return !mlxsw_sp->master_bridge.dev ||
3886 mlxsw_sp->master_bridge.dev == br_dev;
3887 }
3888
3889 static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
3890 struct net_device *br_dev)
3891 {
3892 mlxsw_sp->master_bridge.dev = br_dev;
3893 mlxsw_sp->master_bridge.ref_count++;
3894 }
3895
3896 static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
3897 {
3898 if (--mlxsw_sp->master_bridge.ref_count == 0) {
3899 mlxsw_sp->master_bridge.dev = NULL;
3900 /* It's possible upper VLAN devices are still holding
3901 * references to underlying FIDs. Drop the reference
3902 * and release the resources if it was the last one.
3903 * If it wasn't, then something bad happened.
3904 */
3905 mlxsw_sp_master_bridge_gone_sync(mlxsw_sp);
3906 }
3907 }
3908
3909 static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
3910 struct net_device *br_dev)
3911 {
3912 struct net_device *dev = mlxsw_sp_port->dev;
3913 int err;
3914
3915 /* When port is not bridged untagged packets are tagged with
3916 * PVID=VID=1, thereby creating an implicit VLAN interface in
3917 * the device. Remove it and let bridge code take care of its
3918 * own VLANs.
3919 */
3920 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
3921 if (err)
3922 return err;
3923
3924 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
3925
3926 mlxsw_sp_port->learning = 1;
3927 mlxsw_sp_port->learning_sync = 1;
3928 mlxsw_sp_port->uc_flood = 1;
3929 mlxsw_sp_port->bridged = 1;
3930
3931 return 0;
3932 }
3933
3934 static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
3935 {
3936 struct net_device *dev = mlxsw_sp_port->dev;
3937
3938 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
3939
3940 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
3941
3942 mlxsw_sp_port->learning = 0;
3943 mlxsw_sp_port->learning_sync = 0;
3944 mlxsw_sp_port->uc_flood = 0;
3945 mlxsw_sp_port->bridged = 0;
3946
3947 /* Add implicit VLAN interface in the device, so that untagged
3948 * packets will be classified to the default vFID.
3949 */
3950 mlxsw_sp_port_add_vid(dev, 0, 1);
3951 }
3952
3953 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3954 {
3955 char sldr_pl[MLXSW_REG_SLDR_LEN];
3956
3957 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3958 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3959 }
3960
3961 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3962 {
3963 char sldr_pl[MLXSW_REG_SLDR_LEN];
3964
3965 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3966 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3967 }
3968
3969 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3970 u16 lag_id, u8 port_index)
3971 {
3972 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3973 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3974
3975 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3976 lag_id, port_index);
3977 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3978 }
3979
3980 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3981 u16 lag_id)
3982 {
3983 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3984 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3985
3986 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3987 lag_id);
3988 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3989 }
3990
3991 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3992 u16 lag_id)
3993 {
3994 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3995 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3996
3997 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3998 lag_id);
3999 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4000 }
4001
4002 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4003 u16 lag_id)
4004 {
4005 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4006 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4007
4008 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4009 lag_id);
4010 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4011 }
4012
4013 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4014 struct net_device *lag_dev,
4015 u16 *p_lag_id)
4016 {
4017 struct mlxsw_sp_upper *lag;
4018 int free_lag_id = -1;
4019 u64 max_lag;
4020 int i;
4021
4022 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4023 for (i = 0; i < max_lag; i++) {
4024 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4025 if (lag->ref_count) {
4026 if (lag->dev == lag_dev) {
4027 *p_lag_id = i;
4028 return 0;
4029 }
4030 } else if (free_lag_id < 0) {
4031 free_lag_id = i;
4032 }
4033 }
4034 if (free_lag_id < 0)
4035 return -EBUSY;
4036 *p_lag_id = free_lag_id;
4037 return 0;
4038 }
4039
4040 static bool
4041 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4042 struct net_device *lag_dev,
4043 struct netdev_lag_upper_info *lag_upper_info)
4044 {
4045 u16 lag_id;
4046
4047 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
4048 return false;
4049 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
4050 return false;
4051 return true;
4052 }
4053
4054 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4055 u16 lag_id, u8 *p_port_index)
4056 {
4057 u64 max_lag_members;
4058 int i;
4059
4060 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4061 MAX_LAG_MEMBERS);
4062 for (i = 0; i < max_lag_members; i++) {
4063 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4064 *p_port_index = i;
4065 return 0;
4066 }
4067 }
4068 return -EBUSY;
4069 }
4070
4071 static void
4072 mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4073 u16 lag_id)
4074 {
4075 struct mlxsw_sp_port *mlxsw_sp_vport;
4076 struct mlxsw_sp_fid *f;
4077
4078 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4079 if (WARN_ON(!mlxsw_sp_vport))
4080 return;
4081
4082 /* If vPort is assigned a RIF, then leave it since it's no
4083 * longer valid.
4084 */
4085 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4086 if (f)
4087 f->leave(mlxsw_sp_vport);
4088
4089 mlxsw_sp_vport->lag_id = lag_id;
4090 mlxsw_sp_vport->lagged = 1;
4091 }
4092
4093 static void
4094 mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4095 {
4096 struct mlxsw_sp_port *mlxsw_sp_vport;
4097 struct mlxsw_sp_fid *f;
4098
4099 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4100 if (WARN_ON(!mlxsw_sp_vport))
4101 return;
4102
4103 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4104 if (f)
4105 f->leave(mlxsw_sp_vport);
4106
4107 mlxsw_sp_vport->lagged = 0;
4108 }
4109
4110 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4111 struct net_device *lag_dev)
4112 {
4113 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4114 struct mlxsw_sp_upper *lag;
4115 u16 lag_id;
4116 u8 port_index;
4117 int err;
4118
4119 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4120 if (err)
4121 return err;
4122 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4123 if (!lag->ref_count) {
4124 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4125 if (err)
4126 return err;
4127 lag->dev = lag_dev;
4128 }
4129
4130 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4131 if (err)
4132 return err;
4133 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4134 if (err)
4135 goto err_col_port_add;
4136 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4137 if (err)
4138 goto err_col_port_enable;
4139
4140 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4141 mlxsw_sp_port->local_port);
4142 mlxsw_sp_port->lag_id = lag_id;
4143 mlxsw_sp_port->lagged = 1;
4144 lag->ref_count++;
4145
4146 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_id);
4147
4148 return 0;
4149
4150 err_col_port_enable:
4151 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4152 err_col_port_add:
4153 if (!lag->ref_count)
4154 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4155 return err;
4156 }
4157
4158 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4159 struct net_device *lag_dev)
4160 {
4161 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4162 u16 lag_id = mlxsw_sp_port->lag_id;
4163 struct mlxsw_sp_upper *lag;
4164
4165 if (!mlxsw_sp_port->lagged)
4166 return;
4167 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4168 WARN_ON(lag->ref_count == 0);
4169
4170 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4171 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4172
4173 if (mlxsw_sp_port->bridged) {
4174 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
4175 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
4176 }
4177
4178 if (lag->ref_count == 1)
4179 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4180
4181 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4182 mlxsw_sp_port->local_port);
4183 mlxsw_sp_port->lagged = 0;
4184 lag->ref_count--;
4185
4186 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
4187 }
4188
4189 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4190 u16 lag_id)
4191 {
4192 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4193 char sldr_pl[MLXSW_REG_SLDR_LEN];
4194
4195 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4196 mlxsw_sp_port->local_port);
4197 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4198 }
4199
4200 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4201 u16 lag_id)
4202 {
4203 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4204 char sldr_pl[MLXSW_REG_SLDR_LEN];
4205
4206 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4207 mlxsw_sp_port->local_port);
4208 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4209 }
4210
4211 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4212 bool lag_tx_enabled)
4213 {
4214 if (lag_tx_enabled)
4215 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4216 mlxsw_sp_port->lag_id);
4217 else
4218 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4219 mlxsw_sp_port->lag_id);
4220 }
4221
4222 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4223 struct netdev_lag_lower_state_info *info)
4224 {
4225 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4226 }
4227
4228 static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
4229 struct net_device *vlan_dev)
4230 {
4231 struct mlxsw_sp_port *mlxsw_sp_vport;
4232 u16 vid = vlan_dev_vlan_id(vlan_dev);
4233
4234 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
4235 if (WARN_ON(!mlxsw_sp_vport))
4236 return -EINVAL;
4237
4238 mlxsw_sp_vport->dev = vlan_dev;
4239
4240 return 0;
4241 }
4242
4243 static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
4244 struct net_device *vlan_dev)
4245 {
4246 struct mlxsw_sp_port *mlxsw_sp_vport;
4247 u16 vid = vlan_dev_vlan_id(vlan_dev);
4248
4249 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
4250 if (WARN_ON(!mlxsw_sp_vport))
4251 return;
4252
4253 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
4254 }
4255
4256 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
4257 unsigned long event, void *ptr)
4258 {
4259 struct netdev_notifier_changeupper_info *info;
4260 struct mlxsw_sp_port *mlxsw_sp_port;
4261 struct net_device *upper_dev;
4262 struct mlxsw_sp *mlxsw_sp;
4263 int err = 0;
4264
4265 mlxsw_sp_port = netdev_priv(dev);
4266 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4267 info = ptr;
4268
4269 switch (event) {
4270 case NETDEV_PRECHANGEUPPER:
4271 upper_dev = info->upper_dev;
4272 if (!is_vlan_dev(upper_dev) &&
4273 !netif_is_lag_master(upper_dev) &&
4274 !netif_is_bridge_master(upper_dev))
4275 return -EINVAL;
4276 if (!info->linking)
4277 break;
4278 /* HW limitation forbids to put ports to multiple bridges. */
4279 if (netif_is_bridge_master(upper_dev) &&
4280 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
4281 return -EINVAL;
4282 if (netif_is_lag_master(upper_dev) &&
4283 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4284 info->upper_info))
4285 return -EINVAL;
4286 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4287 return -EINVAL;
4288 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4289 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4290 return -EINVAL;
4291 break;
4292 case NETDEV_CHANGEUPPER:
4293 upper_dev = info->upper_dev;
4294 if (is_vlan_dev(upper_dev)) {
4295 if (info->linking)
4296 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
4297 upper_dev);
4298 else
4299 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
4300 upper_dev);
4301 } else if (netif_is_bridge_master(upper_dev)) {
4302 if (info->linking)
4303 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4304 upper_dev);
4305 else
4306 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
4307 } else if (netif_is_lag_master(upper_dev)) {
4308 if (info->linking)
4309 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4310 upper_dev);
4311 else
4312 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4313 upper_dev);
4314 } else {
4315 err = -EINVAL;
4316 WARN_ON(1);
4317 }
4318 break;
4319 }
4320
4321 return err;
4322 }
4323
4324 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4325 unsigned long event, void *ptr)
4326 {
4327 struct netdev_notifier_changelowerstate_info *info;
4328 struct mlxsw_sp_port *mlxsw_sp_port;
4329 int err;
4330
4331 mlxsw_sp_port = netdev_priv(dev);
4332 info = ptr;
4333
4334 switch (event) {
4335 case NETDEV_CHANGELOWERSTATE:
4336 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4337 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4338 info->lower_state_info);
4339 if (err)
4340 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4341 }
4342 break;
4343 }
4344
4345 return 0;
4346 }
4347
4348 static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
4349 unsigned long event, void *ptr)
4350 {
4351 switch (event) {
4352 case NETDEV_PRECHANGEUPPER:
4353 case NETDEV_CHANGEUPPER:
4354 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
4355 case NETDEV_CHANGELOWERSTATE:
4356 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
4357 }
4358
4359 return 0;
4360 }
4361
4362 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4363 unsigned long event, void *ptr)
4364 {
4365 struct net_device *dev;
4366 struct list_head *iter;
4367 int ret;
4368
4369 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4370 if (mlxsw_sp_port_dev_check(dev)) {
4371 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4372 if (ret)
4373 return ret;
4374 }
4375 }
4376
4377 return 0;
4378 }
4379
4380 static int mlxsw_sp_master_bridge_vlan_link(struct mlxsw_sp *mlxsw_sp,
4381 struct net_device *vlan_dev)
4382 {
4383 u16 fid = vlan_dev_vlan_id(vlan_dev);
4384 struct mlxsw_sp_fid *f;
4385
4386 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4387 if (!f) {
4388 f = mlxsw_sp_fid_create(mlxsw_sp, fid);
4389 if (IS_ERR(f))
4390 return PTR_ERR(f);
4391 }
4392
4393 f->ref_count++;
4394
4395 return 0;
4396 }
4397
4398 static void mlxsw_sp_master_bridge_vlan_unlink(struct mlxsw_sp *mlxsw_sp,
4399 struct net_device *vlan_dev)
4400 {
4401 u16 fid = vlan_dev_vlan_id(vlan_dev);
4402 struct mlxsw_sp_fid *f;
4403
4404 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4405 if (f && f->r)
4406 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
4407 if (f && --f->ref_count == 0)
4408 mlxsw_sp_fid_destroy(mlxsw_sp, f);
4409 }
4410
4411 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4412 unsigned long event, void *ptr)
4413 {
4414 struct netdev_notifier_changeupper_info *info;
4415 struct net_device *upper_dev;
4416 struct mlxsw_sp *mlxsw_sp;
4417 int err;
4418
4419 mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4420 if (!mlxsw_sp)
4421 return 0;
4422 if (br_dev != mlxsw_sp->master_bridge.dev)
4423 return 0;
4424
4425 info = ptr;
4426
4427 switch (event) {
4428 case NETDEV_CHANGEUPPER:
4429 upper_dev = info->upper_dev;
4430 if (!is_vlan_dev(upper_dev))
4431 break;
4432 if (info->linking) {
4433 err = mlxsw_sp_master_bridge_vlan_link(mlxsw_sp,
4434 upper_dev);
4435 if (err)
4436 return err;
4437 } else {
4438 mlxsw_sp_master_bridge_vlan_unlink(mlxsw_sp, upper_dev);
4439 }
4440 break;
4441 }
4442
4443 return 0;
4444 }
4445
4446 static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
4447 {
4448 return find_first_zero_bit(mlxsw_sp->vfids.mapped,
4449 MLXSW_SP_VFID_MAX);
4450 }
4451
4452 static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
4453 {
4454 char sfmr_pl[MLXSW_REG_SFMR_LEN];
4455
4456 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
4457 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
4458 }
4459
4460 static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
4461
4462 static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
4463 struct net_device *br_dev)
4464 {
4465 struct device *dev = mlxsw_sp->bus_info->dev;
4466 struct mlxsw_sp_fid *f;
4467 u16 vfid, fid;
4468 int err;
4469
4470 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
4471 if (vfid == MLXSW_SP_VFID_MAX) {
4472 dev_err(dev, "No available vFIDs\n");
4473 return ERR_PTR(-ERANGE);
4474 }
4475
4476 fid = mlxsw_sp_vfid_to_fid(vfid);
4477 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
4478 if (err) {
4479 dev_err(dev, "Failed to create FID=%d\n", fid);
4480 return ERR_PTR(err);
4481 }
4482
4483 f = kzalloc(sizeof(*f), GFP_KERNEL);
4484 if (!f)
4485 goto err_allocate_vfid;
4486
4487 f->leave = mlxsw_sp_vport_vfid_leave;
4488 f->fid = fid;
4489 f->dev = br_dev;
4490
4491 list_add(&f->list, &mlxsw_sp->vfids.list);
4492 set_bit(vfid, mlxsw_sp->vfids.mapped);
4493
4494 return f;
4495
4496 err_allocate_vfid:
4497 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
4498 return ERR_PTR(-ENOMEM);
4499 }
4500
4501 static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
4502 struct mlxsw_sp_fid *f)
4503 {
4504 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
4505 u16 fid = f->fid;
4506
4507 clear_bit(vfid, mlxsw_sp->vfids.mapped);
4508 list_del(&f->list);
4509
4510 if (f->r)
4511 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
4512
4513 kfree(f);
4514
4515 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
4516 }
4517
4518 static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
4519 bool valid)
4520 {
4521 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
4522 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4523
4524 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
4525 vid);
4526 }
4527
4528 static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4529 struct net_device *br_dev)
4530 {
4531 struct mlxsw_sp_fid *f;
4532 int err;
4533
4534 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
4535 if (!f) {
4536 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
4537 if (IS_ERR(f))
4538 return PTR_ERR(f);
4539 }
4540
4541 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
4542 if (err)
4543 goto err_vport_flood_set;
4544
4545 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
4546 if (err)
4547 goto err_vport_fid_map;
4548
4549 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
4550 f->ref_count++;
4551
4552 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
4553
4554 return 0;
4555
4556 err_vport_fid_map:
4557 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4558 err_vport_flood_set:
4559 if (!f->ref_count)
4560 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
4561 return err;
4562 }
4563
4564 static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
4565 {
4566 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4567
4568 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
4569
4570 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
4571
4572 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4573
4574 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
4575
4576 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
4577 if (--f->ref_count == 0)
4578 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
4579 }
4580
4581 static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4582 struct net_device *br_dev)
4583 {
4584 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4585 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4586 struct net_device *dev = mlxsw_sp_vport->dev;
4587 int err;
4588
4589 if (f && !WARN_ON(!f->leave))
4590 f->leave(mlxsw_sp_vport);
4591
4592 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport, br_dev);
4593 if (err) {
4594 netdev_err(dev, "Failed to join vFID\n");
4595 return err;
4596 }
4597
4598 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
4599 if (err) {
4600 netdev_err(dev, "Failed to enable learning\n");
4601 goto err_port_vid_learning_set;
4602 }
4603
4604 mlxsw_sp_vport->learning = 1;
4605 mlxsw_sp_vport->learning_sync = 1;
4606 mlxsw_sp_vport->uc_flood = 1;
4607 mlxsw_sp_vport->bridged = 1;
4608
4609 return 0;
4610
4611 err_port_vid_learning_set:
4612 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
4613 return err;
4614 }
4615
4616 static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
4617 {
4618 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4619
4620 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
4621
4622 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
4623
4624 mlxsw_sp_vport->learning = 0;
4625 mlxsw_sp_vport->learning_sync = 0;
4626 mlxsw_sp_vport->uc_flood = 0;
4627 mlxsw_sp_vport->bridged = 0;
4628 }
4629
4630 static bool
4631 mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
4632 const struct net_device *br_dev)
4633 {
4634 struct mlxsw_sp_port *mlxsw_sp_vport;
4635
4636 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
4637 vport.list) {
4638 struct net_device *dev = mlxsw_sp_vport_dev_get(mlxsw_sp_vport);
4639
4640 if (dev && dev == br_dev)
4641 return false;
4642 }
4643
4644 return true;
4645 }
4646
4647 static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
4648 unsigned long event, void *ptr,
4649 u16 vid)
4650 {
4651 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4652 struct netdev_notifier_changeupper_info *info = ptr;
4653 struct mlxsw_sp_port *mlxsw_sp_vport;
4654 struct net_device *upper_dev;
4655 int err = 0;
4656
4657 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
4658
4659 switch (event) {
4660 case NETDEV_PRECHANGEUPPER:
4661 upper_dev = info->upper_dev;
4662 if (!netif_is_bridge_master(upper_dev))
4663 return -EINVAL;
4664 if (!info->linking)
4665 break;
4666 /* We can't have multiple VLAN interfaces configured on
4667 * the same port and being members in the same bridge.
4668 */
4669 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
4670 upper_dev))
4671 return -EINVAL;
4672 break;
4673 case NETDEV_CHANGEUPPER:
4674 upper_dev = info->upper_dev;
4675 if (info->linking) {
4676 if (WARN_ON(!mlxsw_sp_vport))
4677 return -EINVAL;
4678 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
4679 upper_dev);
4680 } else {
4681 if (!mlxsw_sp_vport)
4682 return 0;
4683 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
4684 }
4685 }
4686
4687 return err;
4688 }
4689
4690 static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
4691 unsigned long event, void *ptr,
4692 u16 vid)
4693 {
4694 struct net_device *dev;
4695 struct list_head *iter;
4696 int ret;
4697
4698 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4699 if (mlxsw_sp_port_dev_check(dev)) {
4700 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
4701 vid);
4702 if (ret)
4703 return ret;
4704 }
4705 }
4706
4707 return 0;
4708 }
4709
4710 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4711 unsigned long event, void *ptr)
4712 {
4713 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4714 u16 vid = vlan_dev_vlan_id(vlan_dev);
4715
4716 if (mlxsw_sp_port_dev_check(real_dev))
4717 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
4718 vid);
4719 else if (netif_is_lag_master(real_dev))
4720 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
4721 vid);
4722
4723 return 0;
4724 }
4725
4726 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4727 unsigned long event, void *ptr)
4728 {
4729 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4730 int err = 0;
4731
4732 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4733 err = mlxsw_sp_netdevice_router_port_event(dev);
4734 else if (mlxsw_sp_port_dev_check(dev))
4735 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4736 else if (netif_is_lag_master(dev))
4737 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4738 else if (netif_is_bridge_master(dev))
4739 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
4740 else if (is_vlan_dev(dev))
4741 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
4742
4743 return notifier_from_errno(err);
4744 }
4745
4746 static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4747 .notifier_call = mlxsw_sp_netdevice_event,
4748 };
4749
4750 static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4751 .notifier_call = mlxsw_sp_inetaddr_event,
4752 .priority = 10, /* Must be called before FIB notifier block */
4753 };
4754
4755 static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4756 .notifier_call = mlxsw_sp_router_netevent_event,
4757 };
4758
4759 static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4760 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4761 {0, },
4762 };
4763
4764 static struct pci_driver mlxsw_sp_pci_driver = {
4765 .name = mlxsw_sp_driver_name,
4766 .id_table = mlxsw_sp_pci_id_table,
4767 };
4768
4769 static int __init mlxsw_sp_module_init(void)
4770 {
4771 int err;
4772
4773 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4774 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4775 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4776
4777 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4778 if (err)
4779 goto err_core_driver_register;
4780
4781 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4782 if (err)
4783 goto err_pci_driver_register;
4784
4785 return 0;
4786
4787 err_pci_driver_register:
4788 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
4789 err_core_driver_register:
4790 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4791 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4792 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4793 return err;
4794 }
4795
4796 static void __exit mlxsw_sp_module_exit(void)
4797 {
4798 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
4799 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
4800 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4801 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4802 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4803 }
4804
4805 module_init(mlxsw_sp_module_init);
4806 module_exit(mlxsw_sp_module_exit);
4807
4808 MODULE_LICENSE("Dual BSD/GPL");
4809 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4810 MODULE_DESCRIPTION("Mellanox Spectrum driver");
4811 MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
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