2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/scatterlist.h>
27 #include <linux/of_dma.h>
28 #include <linux/err.h>
29 #include <linux/pm_runtime.h>
31 #include "dmaengine.h"
32 #define PL330_MAX_CHAN 8
33 #define PL330_MAX_IRQS 32
34 #define PL330_MAX_PERI 32
35 #define PL330_MAX_BURST 16
37 #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
39 enum pl330_cachectrl
{
40 CCTRL0
, /* Noncacheable and nonbufferable */
41 CCTRL1
, /* Bufferable only */
42 CCTRL2
, /* Cacheable, but do not allocate */
43 CCTRL3
, /* Cacheable and bufferable, but do not allocate */
44 INVALID1
, /* AWCACHE = 0x1000 */
46 CCTRL6
, /* Cacheable write-through, allocate on writes only */
47 CCTRL7
, /* Cacheable write-back, allocate on writes only */
58 /* Register and Bit field Definitions */
60 #define DS_ST_STOP 0x0
61 #define DS_ST_EXEC 0x1
62 #define DS_ST_CMISS 0x2
63 #define DS_ST_UPDTPC 0x3
65 #define DS_ST_ATBRR 0x5
66 #define DS_ST_QBUSY 0x6
68 #define DS_ST_KILL 0x8
69 #define DS_ST_CMPLT 0x9
70 #define DS_ST_FLTCMP 0xe
71 #define DS_ST_FAULT 0xf
76 #define INTSTATUS 0x28
83 #define FTC(n) (_FTC + (n)*0x4)
86 #define CS(n) (_CS + (n)*0x8)
87 #define CS_CNS (1 << 21)
90 #define CPC(n) (_CPC + (n)*0x8)
93 #define SA(n) (_SA + (n)*0x20)
96 #define DA(n) (_DA + (n)*0x20)
99 #define CC(n) (_CC + (n)*0x20)
101 #define CC_SRCINC (1 << 0)
102 #define CC_DSTINC (1 << 14)
103 #define CC_SRCPRI (1 << 8)
104 #define CC_DSTPRI (1 << 22)
105 #define CC_SRCNS (1 << 9)
106 #define CC_DSTNS (1 << 23)
107 #define CC_SRCIA (1 << 10)
108 #define CC_DSTIA (1 << 24)
109 #define CC_SRCBRSTLEN_SHFT 4
110 #define CC_DSTBRSTLEN_SHFT 18
111 #define CC_SRCBRSTSIZE_SHFT 1
112 #define CC_DSTBRSTSIZE_SHFT 15
113 #define CC_SRCCCTRL_SHFT 11
114 #define CC_SRCCCTRL_MASK 0x7
115 #define CC_DSTCCTRL_SHFT 25
116 #define CC_DRCCCTRL_MASK 0x7
117 #define CC_SWAP_SHFT 28
120 #define LC0(n) (_LC0 + (n)*0x20)
123 #define LC1(n) (_LC1 + (n)*0x20)
125 #define DBGSTATUS 0xd00
126 #define DBG_BUSY (1 << 0)
129 #define DBGINST0 0xd08
130 #define DBGINST1 0xd0c
139 #define PERIPH_ID 0xfe0
140 #define PERIPH_REV_SHIFT 20
141 #define PERIPH_REV_MASK 0xf
142 #define PERIPH_REV_R0P0 0
143 #define PERIPH_REV_R1P0 1
144 #define PERIPH_REV_R1P1 2
146 #define CR0_PERIPH_REQ_SET (1 << 0)
147 #define CR0_BOOT_EN_SET (1 << 1)
148 #define CR0_BOOT_MAN_NS (1 << 2)
149 #define CR0_NUM_CHANS_SHIFT 4
150 #define CR0_NUM_CHANS_MASK 0x7
151 #define CR0_NUM_PERIPH_SHIFT 12
152 #define CR0_NUM_PERIPH_MASK 0x1f
153 #define CR0_NUM_EVENTS_SHIFT 17
154 #define CR0_NUM_EVENTS_MASK 0x1f
156 #define CR1_ICACHE_LEN_SHIFT 0
157 #define CR1_ICACHE_LEN_MASK 0x7
158 #define CR1_NUM_ICACHELINES_SHIFT 4
159 #define CR1_NUM_ICACHELINES_MASK 0xf
161 #define CRD_DATA_WIDTH_SHIFT 0
162 #define CRD_DATA_WIDTH_MASK 0x7
163 #define CRD_WR_CAP_SHIFT 4
164 #define CRD_WR_CAP_MASK 0x7
165 #define CRD_WR_Q_DEP_SHIFT 8
166 #define CRD_WR_Q_DEP_MASK 0xf
167 #define CRD_RD_CAP_SHIFT 12
168 #define CRD_RD_CAP_MASK 0x7
169 #define CRD_RD_Q_DEP_SHIFT 16
170 #define CRD_RD_Q_DEP_MASK 0xf
171 #define CRD_DATA_BUFF_SHIFT 20
172 #define CRD_DATA_BUFF_MASK 0x3ff
175 #define DESIGNER 0x41
177 #define INTEG_CFG 0x0
178 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
180 #define PL330_STATE_STOPPED (1 << 0)
181 #define PL330_STATE_EXECUTING (1 << 1)
182 #define PL330_STATE_WFE (1 << 2)
183 #define PL330_STATE_FAULTING (1 << 3)
184 #define PL330_STATE_COMPLETING (1 << 4)
185 #define PL330_STATE_WFP (1 << 5)
186 #define PL330_STATE_KILLING (1 << 6)
187 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
188 #define PL330_STATE_CACHEMISS (1 << 8)
189 #define PL330_STATE_UPDTPC (1 << 9)
190 #define PL330_STATE_ATBARRIER (1 << 10)
191 #define PL330_STATE_QUEUEBUSY (1 << 11)
192 #define PL330_STATE_INVALID (1 << 15)
194 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
195 | PL330_STATE_WFE | PL330_STATE_FAULTING)
197 #define CMD_DMAADDH 0x54
198 #define CMD_DMAEND 0x00
199 #define CMD_DMAFLUSHP 0x35
200 #define CMD_DMAGO 0xa0
201 #define CMD_DMALD 0x04
202 #define CMD_DMALDP 0x25
203 #define CMD_DMALP 0x20
204 #define CMD_DMALPEND 0x28
205 #define CMD_DMAKILL 0x01
206 #define CMD_DMAMOV 0xbc
207 #define CMD_DMANOP 0x18
208 #define CMD_DMARMB 0x12
209 #define CMD_DMASEV 0x34
210 #define CMD_DMAST 0x08
211 #define CMD_DMASTP 0x29
212 #define CMD_DMASTZ 0x0c
213 #define CMD_DMAWFE 0x36
214 #define CMD_DMAWFP 0x30
215 #define CMD_DMAWMB 0x13
219 #define SZ_DMAFLUSHP 2
223 #define SZ_DMALPEND 2
237 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
238 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
240 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
241 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
244 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
245 * at 1byte/burst for P<->M and M<->M respectively.
246 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
247 * should be enough for P<->M and M<->M respectively.
249 #define MCODE_BUFF_PER_REQ 256
251 /* Use this _only_ to wait on transient states */
252 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
254 #ifdef PL330_DEBUG_MCGEN
255 static unsigned cmd_line
;
256 #define PL330_DBGCMD_DUMP(off, x...) do { \
257 printk("%x:", cmd_line); \
261 #define PL330_DBGMC_START(addr) (cmd_line = addr)
263 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264 #define PL330_DBGMC_START(addr) do {} while (0)
267 /* The number of default descriptors */
269 #define NR_DEFAULT_DESC 16
271 /* Delay for runtime PM autosuspend, ms */
272 #define PL330_AUTOSUSPEND_DELAY 20
274 /* Populated by the PL330 core driver for DMA API driver's info */
275 struct pl330_config
{
277 #define DMAC_MODE_NS (1 << 0)
279 unsigned int data_bus_width
:10; /* In number of bits */
280 unsigned int data_buf_dep
:11;
281 unsigned int num_chan
:4;
282 unsigned int num_peri
:6;
284 unsigned int num_events
:6;
289 * Request Configuration.
290 * The PL330 core does not modify this and uses the last
291 * working configuration if the request doesn't provide any.
293 * The Client may want to provide this info only for the
294 * first request and a request with new settings.
296 struct pl330_reqcfg
{
297 /* Address Incrementing */
302 * For now, the SRC & DST protection levels
303 * and burst size/length are assumed same.
309 unsigned brst_size
:3; /* in power of 2 */
311 enum pl330_cachectrl dcctl
;
312 enum pl330_cachectrl scctl
;
313 enum pl330_byteswap swap
;
314 struct pl330_config
*pcfg
;
318 * One cycle of DMAC operation.
319 * There may be more than one xfer in a request.
328 /* The xfer callbacks are made with one of these arguments. */
330 /* The all xfers in the request were success. */
332 /* If req aborted due to global error. */
334 /* If req failed due to problem with Channel. */
355 struct dma_pl330_desc
;
360 struct dma_pl330_desc
*desc
;
363 /* ToBeDone for tasklet */
371 struct pl330_thread
{
374 /* If the channel is not yet acquired by any client */
377 struct pl330_dmac
*dmac
;
378 /* Only two at a time */
379 struct _pl330_req req
[2];
380 /* Index of the last enqueued request */
382 /* Index of the last submitted request or -1 if the DMA is stopped */
386 enum pl330_dmac_state
{
393 /* In the DMAC pool */
396 * Allocated to some channel during prep_xxx
397 * Also may be sitting on the work_list.
401 * Sitting on the work_list and already submitted
402 * to the PL330 core. Not more than two descriptors
403 * of a channel can be BUSY at any time.
407 * Sitting on the channel work_list but xfer done
413 struct dma_pl330_chan
{
414 /* Schedule desc completion */
415 struct tasklet_struct task
;
417 /* DMA-Engine Channel */
418 struct dma_chan chan
;
420 /* List of submitted descriptors */
421 struct list_head submitted_list
;
422 /* List of issued descriptors */
423 struct list_head work_list
;
424 /* List of completed descriptors */
425 struct list_head completed_list
;
427 /* Pointer to the DMAC that manages this channel,
428 * NULL if the channel is available to be acquired.
429 * As the parent, this DMAC also provides descriptors
432 struct pl330_dmac
*dmac
;
434 /* To protect channel manipulation */
438 * Hardware channel thread of PL330 DMAC. NULL if the channel is
441 struct pl330_thread
*thread
;
443 /* For D-to-M and M-to-D channels */
444 int burst_sz
; /* the peripheral fifo width */
445 int burst_len
; /* the number of burst */
446 phys_addr_t fifo_addr
;
447 /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
449 enum dma_data_direction dir
;
451 /* for cyclic capability */
454 /* for runtime pm tracking */
459 /* DMA-Engine Device */
460 struct dma_device ddma
;
462 /* Holds info about sg limitations */
463 struct device_dma_parameters dma_parms
;
465 /* Pool of descriptors available for the DMAC's channels */
466 struct list_head desc_pool
;
467 /* To protect desc_pool manipulation */
468 spinlock_t pool_lock
;
470 /* Size of MicroCode buffers for each channel. */
472 /* ioremap'ed address of PL330 registers. */
474 /* Populated by the PL330 core driver during pl330_add */
475 struct pl330_config pcfg
;
478 /* Maximum possible events/irqs */
480 /* BUS address of MicroCode buffer */
481 dma_addr_t mcode_bus
;
482 /* CPU address of MicroCode buffer */
484 /* List of all Channel threads */
485 struct pl330_thread
*channels
;
486 /* Pointer to the MANAGER thread */
487 struct pl330_thread
*manager
;
488 /* To handle bad news in interrupt */
489 struct tasklet_struct tasks
;
490 struct _pl330_tbd dmac_tbd
;
491 /* State of DMAC operation */
492 enum pl330_dmac_state state
;
493 /* Holds list of reqs with due callbacks */
494 struct list_head req_done
;
496 /* Peripheral channels connected to this DMAC */
497 unsigned int num_peripherals
;
498 struct dma_pl330_chan
*peripherals
; /* keep at end */
502 static struct pl330_of_quirks
{
507 .quirk
= "arm,pl330-broken-no-flushp",
508 .id
= PL330_QUIRK_BROKEN_NO_FLUSHP
,
512 struct dma_pl330_desc
{
513 /* To attach to a queue as child */
514 struct list_head node
;
516 /* Descriptor for the DMA Engine API */
517 struct dma_async_tx_descriptor txd
;
519 /* Xfer for PL330 core */
520 struct pl330_xfer px
;
522 struct pl330_reqcfg rqcfg
;
524 enum desc_status status
;
529 /* The channel which currently holds this desc */
530 struct dma_pl330_chan
*pchan
;
532 enum dma_transfer_direction rqtype
;
533 /* Index of peripheral for the xfer. */
535 /* Hook to attach to DMAC's list of reqs with due callback */
536 struct list_head rqd
;
541 struct dma_pl330_desc
*desc
;
544 static inline bool _queue_full(struct pl330_thread
*thrd
)
546 return thrd
->req
[0].desc
!= NULL
&& thrd
->req
[1].desc
!= NULL
;
549 static inline bool is_manager(struct pl330_thread
*thrd
)
551 return thrd
->dmac
->manager
== thrd
;
554 /* If manager of the thread is in Non-Secure mode */
555 static inline bool _manager_ns(struct pl330_thread
*thrd
)
557 return (thrd
->dmac
->pcfg
.mode
& DMAC_MODE_NS
) ? true : false;
560 static inline u32
get_revision(u32 periph_id
)
562 return (periph_id
>> PERIPH_REV_SHIFT
) & PERIPH_REV_MASK
;
565 static inline u32
_emit_END(unsigned dry_run
, u8 buf
[])
572 PL330_DBGCMD_DUMP(SZ_DMAEND
, "\tDMAEND\n");
577 static inline u32
_emit_FLUSHP(unsigned dry_run
, u8 buf
[], u8 peri
)
582 buf
[0] = CMD_DMAFLUSHP
;
588 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP
, "\tDMAFLUSHP %u\n", peri
>> 3);
593 static inline u32
_emit_LD(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
601 buf
[0] |= (0 << 1) | (1 << 0);
602 else if (cond
== BURST
)
603 buf
[0] |= (1 << 1) | (1 << 0);
605 PL330_DBGCMD_DUMP(SZ_DMALD
, "\tDMALD%c\n",
606 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
611 static inline u32
_emit_LDP(unsigned dry_run
, u8 buf
[],
612 enum pl330_cond cond
, u8 peri
)
626 PL330_DBGCMD_DUMP(SZ_DMALDP
, "\tDMALDP%c %u\n",
627 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
632 static inline u32
_emit_LP(unsigned dry_run
, u8 buf
[],
633 unsigned loop
, u8 cnt
)
643 cnt
--; /* DMAC increments by 1 internally */
646 PL330_DBGCMD_DUMP(SZ_DMALP
, "\tDMALP_%c %u\n", loop
? '1' : '0', cnt
);
652 enum pl330_cond cond
;
658 static inline u32
_emit_LPEND(unsigned dry_run
, u8 buf
[],
659 const struct _arg_LPEND
*arg
)
661 enum pl330_cond cond
= arg
->cond
;
662 bool forever
= arg
->forever
;
663 unsigned loop
= arg
->loop
;
664 u8 bjump
= arg
->bjump
;
669 buf
[0] = CMD_DMALPEND
;
678 buf
[0] |= (0 << 1) | (1 << 0);
679 else if (cond
== BURST
)
680 buf
[0] |= (1 << 1) | (1 << 0);
684 PL330_DBGCMD_DUMP(SZ_DMALPEND
, "\tDMALP%s%c_%c bjmpto_%x\n",
685 forever
? "FE" : "END",
686 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'),
693 static inline u32
_emit_KILL(unsigned dry_run
, u8 buf
[])
698 buf
[0] = CMD_DMAKILL
;
703 static inline u32
_emit_MOV(unsigned dry_run
, u8 buf
[],
704 enum dmamov_dst dst
, u32 val
)
716 PL330_DBGCMD_DUMP(SZ_DMAMOV
, "\tDMAMOV %s 0x%x\n",
717 dst
== SAR
? "SAR" : (dst
== DAR
? "DAR" : "CCR"), val
);
722 static inline u32
_emit_RMB(unsigned dry_run
, u8 buf
[])
729 PL330_DBGCMD_DUMP(SZ_DMARMB
, "\tDMARMB\n");
734 static inline u32
_emit_SEV(unsigned dry_run
, u8 buf
[], u8 ev
)
745 PL330_DBGCMD_DUMP(SZ_DMASEV
, "\tDMASEV %u\n", ev
>> 3);
750 static inline u32
_emit_ST(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
758 buf
[0] |= (0 << 1) | (1 << 0);
759 else if (cond
== BURST
)
760 buf
[0] |= (1 << 1) | (1 << 0);
762 PL330_DBGCMD_DUMP(SZ_DMAST
, "\tDMAST%c\n",
763 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
768 static inline u32
_emit_STP(unsigned dry_run
, u8 buf
[],
769 enum pl330_cond cond
, u8 peri
)
783 PL330_DBGCMD_DUMP(SZ_DMASTP
, "\tDMASTP%c %u\n",
784 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
789 static inline u32
_emit_WFP(unsigned dry_run
, u8 buf
[],
790 enum pl330_cond cond
, u8 peri
)
798 buf
[0] |= (0 << 1) | (0 << 0);
799 else if (cond
== BURST
)
800 buf
[0] |= (1 << 1) | (0 << 0);
802 buf
[0] |= (0 << 1) | (1 << 0);
808 PL330_DBGCMD_DUMP(SZ_DMAWFP
, "\tDMAWFP%c %u\n",
809 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'P'), peri
>> 3);
814 static inline u32
_emit_WMB(unsigned dry_run
, u8 buf
[])
821 PL330_DBGCMD_DUMP(SZ_DMAWMB
, "\tDMAWMB\n");
832 static inline u32
_emit_GO(unsigned dry_run
, u8 buf
[],
833 const struct _arg_GO
*arg
)
836 u32 addr
= arg
->addr
;
837 unsigned ns
= arg
->ns
;
853 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
855 /* Returns Time-Out */
856 static bool _until_dmac_idle(struct pl330_thread
*thrd
)
858 void __iomem
*regs
= thrd
->dmac
->base
;
859 unsigned long loops
= msecs_to_loops(5);
862 /* Until Manager is Idle */
863 if (!(readl(regs
+ DBGSTATUS
) & DBG_BUSY
))
875 static inline void _execute_DBGINSN(struct pl330_thread
*thrd
,
876 u8 insn
[], bool as_manager
)
878 void __iomem
*regs
= thrd
->dmac
->base
;
881 val
= (insn
[0] << 16) | (insn
[1] << 24);
884 val
|= (thrd
->id
<< 8); /* Channel Number */
886 writel(val
, regs
+ DBGINST0
);
888 val
= le32_to_cpu(*((__le32
*)&insn
[2]));
889 writel(val
, regs
+ DBGINST1
);
891 /* If timed out due to halted state-machine */
892 if (_until_dmac_idle(thrd
)) {
893 dev_err(thrd
->dmac
->ddma
.dev
, "DMAC halted!\n");
898 writel(0, regs
+ DBGCMD
);
901 static inline u32
_state(struct pl330_thread
*thrd
)
903 void __iomem
*regs
= thrd
->dmac
->base
;
906 if (is_manager(thrd
))
907 val
= readl(regs
+ DS
) & 0xf;
909 val
= readl(regs
+ CS(thrd
->id
)) & 0xf;
913 return PL330_STATE_STOPPED
;
915 return PL330_STATE_EXECUTING
;
917 return PL330_STATE_CACHEMISS
;
919 return PL330_STATE_UPDTPC
;
921 return PL330_STATE_WFE
;
923 return PL330_STATE_FAULTING
;
925 if (is_manager(thrd
))
926 return PL330_STATE_INVALID
;
928 return PL330_STATE_ATBARRIER
;
930 if (is_manager(thrd
))
931 return PL330_STATE_INVALID
;
933 return PL330_STATE_QUEUEBUSY
;
935 if (is_manager(thrd
))
936 return PL330_STATE_INVALID
;
938 return PL330_STATE_WFP
;
940 if (is_manager(thrd
))
941 return PL330_STATE_INVALID
;
943 return PL330_STATE_KILLING
;
945 if (is_manager(thrd
))
946 return PL330_STATE_INVALID
;
948 return PL330_STATE_COMPLETING
;
950 if (is_manager(thrd
))
951 return PL330_STATE_INVALID
;
953 return PL330_STATE_FAULT_COMPLETING
;
955 return PL330_STATE_INVALID
;
959 static void _stop(struct pl330_thread
*thrd
)
961 void __iomem
*regs
= thrd
->dmac
->base
;
962 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
964 if (_state(thrd
) == PL330_STATE_FAULT_COMPLETING
)
965 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
967 /* Return if nothing needs to be done */
968 if (_state(thrd
) == PL330_STATE_COMPLETING
969 || _state(thrd
) == PL330_STATE_KILLING
970 || _state(thrd
) == PL330_STATE_STOPPED
)
975 /* Stop generating interrupts for SEV */
976 writel(readl(regs
+ INTEN
) & ~(1 << thrd
->ev
), regs
+ INTEN
);
978 _execute_DBGINSN(thrd
, insn
, is_manager(thrd
));
981 /* Start doing req 'idx' of thread 'thrd' */
982 static bool _trigger(struct pl330_thread
*thrd
)
984 void __iomem
*regs
= thrd
->dmac
->base
;
985 struct _pl330_req
*req
;
986 struct dma_pl330_desc
*desc
;
989 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
992 /* Return if already ACTIVE */
993 if (_state(thrd
) != PL330_STATE_STOPPED
)
996 idx
= 1 - thrd
->lstenq
;
997 if (thrd
->req
[idx
].desc
!= NULL
) {
998 req
= &thrd
->req
[idx
];
1001 if (thrd
->req
[idx
].desc
!= NULL
)
1002 req
= &thrd
->req
[idx
];
1007 /* Return if no request */
1011 /* Return if req is running */
1012 if (idx
== thrd
->req_running
)
1017 ns
= desc
->rqcfg
.nonsecure
? 1 : 0;
1019 /* See 'Abort Sources' point-4 at Page 2-25 */
1020 if (_manager_ns(thrd
) && !ns
)
1021 dev_info(thrd
->dmac
->ddma
.dev
, "%s:%d Recipe for ABORT!\n",
1022 __func__
, __LINE__
);
1025 go
.addr
= req
->mc_bus
;
1027 _emit_GO(0, insn
, &go
);
1029 /* Set to generate interrupts for SEV */
1030 writel(readl(regs
+ INTEN
) | (1 << thrd
->ev
), regs
+ INTEN
);
1032 /* Only manager can execute GO */
1033 _execute_DBGINSN(thrd
, insn
, true);
1035 thrd
->req_running
= idx
;
1040 static bool _start(struct pl330_thread
*thrd
)
1042 switch (_state(thrd
)) {
1043 case PL330_STATE_FAULT_COMPLETING
:
1044 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1046 if (_state(thrd
) == PL330_STATE_KILLING
)
1047 UNTIL(thrd
, PL330_STATE_STOPPED
)
1049 case PL330_STATE_FAULTING
:
1052 case PL330_STATE_KILLING
:
1053 case PL330_STATE_COMPLETING
:
1054 UNTIL(thrd
, PL330_STATE_STOPPED
)
1056 case PL330_STATE_STOPPED
:
1057 return _trigger(thrd
);
1059 case PL330_STATE_WFP
:
1060 case PL330_STATE_QUEUEBUSY
:
1061 case PL330_STATE_ATBARRIER
:
1062 case PL330_STATE_UPDTPC
:
1063 case PL330_STATE_CACHEMISS
:
1064 case PL330_STATE_EXECUTING
:
1067 case PL330_STATE_WFE
: /* For RESUME, nothing yet */
1073 static inline int _ldst_memtomem(unsigned dry_run
, u8 buf
[],
1074 const struct _xfer_spec
*pxs
, int cyc
)
1077 struct pl330_config
*pcfg
= pxs
->desc
->rqcfg
.pcfg
;
1079 /* check lock-up free version */
1080 if (get_revision(pcfg
->periph_id
) >= PERIPH_REV_R1P0
) {
1082 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1083 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1087 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1088 off
+= _emit_RMB(dry_run
, &buf
[off
]);
1089 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1090 off
+= _emit_WMB(dry_run
, &buf
[off
]);
1097 static inline int _ldst_devtomem(struct pl330_dmac
*pl330
, unsigned dry_run
,
1098 u8 buf
[], const struct _xfer_spec
*pxs
,
1102 enum pl330_cond cond
;
1104 if (pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
)
1110 off
+= _emit_WFP(dry_run
, &buf
[off
], cond
, pxs
->desc
->peri
);
1111 off
+= _emit_LDP(dry_run
, &buf
[off
], cond
, pxs
->desc
->peri
);
1112 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1114 if (!(pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
))
1115 off
+= _emit_FLUSHP(dry_run
, &buf
[off
],
1122 static inline int _ldst_memtodev(struct pl330_dmac
*pl330
,
1123 unsigned dry_run
, u8 buf
[],
1124 const struct _xfer_spec
*pxs
, int cyc
)
1127 enum pl330_cond cond
;
1129 if (pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
)
1135 off
+= _emit_WFP(dry_run
, &buf
[off
], cond
, pxs
->desc
->peri
);
1136 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1137 off
+= _emit_STP(dry_run
, &buf
[off
], cond
, pxs
->desc
->peri
);
1139 if (!(pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
))
1140 off
+= _emit_FLUSHP(dry_run
, &buf
[off
],
1147 static int _bursts(struct pl330_dmac
*pl330
, unsigned dry_run
, u8 buf
[],
1148 const struct _xfer_spec
*pxs
, int cyc
)
1152 switch (pxs
->desc
->rqtype
) {
1153 case DMA_MEM_TO_DEV
:
1154 off
+= _ldst_memtodev(pl330
, dry_run
, &buf
[off
], pxs
, cyc
);
1156 case DMA_DEV_TO_MEM
:
1157 off
+= _ldst_devtomem(pl330
, dry_run
, &buf
[off
], pxs
, cyc
);
1159 case DMA_MEM_TO_MEM
:
1160 off
+= _ldst_memtomem(dry_run
, &buf
[off
], pxs
, cyc
);
1163 off
+= 0x40000000; /* Scare off the Client */
1170 /* Returns bytes consumed and updates bursts */
1171 static inline int _loop(struct pl330_dmac
*pl330
, unsigned dry_run
, u8 buf
[],
1172 unsigned long *bursts
, const struct _xfer_spec
*pxs
)
1174 int cyc
, cycmax
, szlp
, szlpend
, szbrst
, off
;
1175 unsigned lcnt0
, lcnt1
, ljmp0
, ljmp1
;
1176 struct _arg_LPEND lpend
;
1179 return _bursts(pl330
, dry_run
, buf
, pxs
, 1);
1181 /* Max iterations possible in DMALP is 256 */
1182 if (*bursts
>= 256*256) {
1185 cyc
= *bursts
/ lcnt1
/ lcnt0
;
1186 } else if (*bursts
> 256) {
1188 lcnt0
= *bursts
/ lcnt1
;
1196 szlp
= _emit_LP(1, buf
, 0, 0);
1197 szbrst
= _bursts(pl330
, 1, buf
, pxs
, 1);
1199 lpend
.cond
= ALWAYS
;
1200 lpend
.forever
= false;
1203 szlpend
= _emit_LPEND(1, buf
, &lpend
);
1211 * Max bursts that we can unroll due to limit on the
1212 * size of backward jump that can be encoded in DMALPEND
1213 * which is 8-bits and hence 255
1215 cycmax
= (255 - (szlp
+ szlpend
)) / szbrst
;
1217 cyc
= (cycmax
< cyc
) ? cycmax
: cyc
;
1222 off
+= _emit_LP(dry_run
, &buf
[off
], 0, lcnt0
);
1226 off
+= _emit_LP(dry_run
, &buf
[off
], 1, lcnt1
);
1229 off
+= _bursts(pl330
, dry_run
, &buf
[off
], pxs
, cyc
);
1231 lpend
.cond
= ALWAYS
;
1232 lpend
.forever
= false;
1234 lpend
.bjump
= off
- ljmp1
;
1235 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1238 lpend
.cond
= ALWAYS
;
1239 lpend
.forever
= false;
1241 lpend
.bjump
= off
- ljmp0
;
1242 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1245 *bursts
= lcnt1
* cyc
;
1252 static inline int _setup_loops(struct pl330_dmac
*pl330
,
1253 unsigned dry_run
, u8 buf
[],
1254 const struct _xfer_spec
*pxs
)
1256 struct pl330_xfer
*x
= &pxs
->desc
->px
;
1258 unsigned long c
, bursts
= BYTE_TO_BURST(x
->bytes
, ccr
);
1263 off
+= _loop(pl330
, dry_run
, &buf
[off
], &c
, pxs
);
1270 static inline int _setup_xfer(struct pl330_dmac
*pl330
,
1271 unsigned dry_run
, u8 buf
[],
1272 const struct _xfer_spec
*pxs
)
1274 struct pl330_xfer
*x
= &pxs
->desc
->px
;
1277 /* DMAMOV SAR, x->src_addr */
1278 off
+= _emit_MOV(dry_run
, &buf
[off
], SAR
, x
->src_addr
);
1279 /* DMAMOV DAR, x->dst_addr */
1280 off
+= _emit_MOV(dry_run
, &buf
[off
], DAR
, x
->dst_addr
);
1283 off
+= _setup_loops(pl330
, dry_run
, &buf
[off
], pxs
);
1289 * A req is a sequence of one or more xfer units.
1290 * Returns the number of bytes taken to setup the MC for the req.
1292 static int _setup_req(struct pl330_dmac
*pl330
, unsigned dry_run
,
1293 struct pl330_thread
*thrd
, unsigned index
,
1294 struct _xfer_spec
*pxs
)
1296 struct _pl330_req
*req
= &thrd
->req
[index
];
1297 struct pl330_xfer
*x
;
1298 u8
*buf
= req
->mc_cpu
;
1301 PL330_DBGMC_START(req
->mc_bus
);
1303 /* DMAMOV CCR, ccr */
1304 off
+= _emit_MOV(dry_run
, &buf
[off
], CCR
, pxs
->ccr
);
1307 /* Error if xfer length is not aligned at burst size */
1308 if (x
->bytes
% (BRST_SIZE(pxs
->ccr
) * BRST_LEN(pxs
->ccr
)))
1311 off
+= _setup_xfer(pl330
, dry_run
, &buf
[off
], pxs
);
1313 /* DMASEV peripheral/event */
1314 off
+= _emit_SEV(dry_run
, &buf
[off
], thrd
->ev
);
1316 off
+= _emit_END(dry_run
, &buf
[off
]);
1321 static inline u32
_prepare_ccr(const struct pl330_reqcfg
*rqc
)
1331 /* We set same protection levels for Src and DST for now */
1332 if (rqc
->privileged
)
1333 ccr
|= CC_SRCPRI
| CC_DSTPRI
;
1335 ccr
|= CC_SRCNS
| CC_DSTNS
;
1336 if (rqc
->insnaccess
)
1337 ccr
|= CC_SRCIA
| CC_DSTIA
;
1339 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_SRCBRSTLEN_SHFT
);
1340 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_DSTBRSTLEN_SHFT
);
1342 ccr
|= (rqc
->brst_size
<< CC_SRCBRSTSIZE_SHFT
);
1343 ccr
|= (rqc
->brst_size
<< CC_DSTBRSTSIZE_SHFT
);
1345 ccr
|= (rqc
->scctl
<< CC_SRCCCTRL_SHFT
);
1346 ccr
|= (rqc
->dcctl
<< CC_DSTCCTRL_SHFT
);
1348 ccr
|= (rqc
->swap
<< CC_SWAP_SHFT
);
1354 * Submit a list of xfers after which the client wants notification.
1355 * Client is not notified after each xfer unit, just once after all
1356 * xfer units are done or some error occurs.
1358 static int pl330_submit_req(struct pl330_thread
*thrd
,
1359 struct dma_pl330_desc
*desc
)
1361 struct pl330_dmac
*pl330
= thrd
->dmac
;
1362 struct _xfer_spec xs
;
1363 unsigned long flags
;
1368 if (pl330
->state
== DYING
1369 || pl330
->dmac_tbd
.reset_chan
& (1 << thrd
->id
)) {
1370 dev_info(thrd
->dmac
->ddma
.dev
, "%s:%d\n",
1371 __func__
, __LINE__
);
1375 /* If request for non-existing peripheral */
1376 if (desc
->rqtype
!= DMA_MEM_TO_MEM
&&
1377 desc
->peri
>= pl330
->pcfg
.num_peri
) {
1378 dev_info(thrd
->dmac
->ddma
.dev
,
1379 "%s:%d Invalid peripheral(%u)!\n",
1380 __func__
, __LINE__
, desc
->peri
);
1384 spin_lock_irqsave(&pl330
->lock
, flags
);
1386 if (_queue_full(thrd
)) {
1391 /* Prefer Secure Channel */
1392 if (!_manager_ns(thrd
))
1393 desc
->rqcfg
.nonsecure
= 0;
1395 desc
->rqcfg
.nonsecure
= 1;
1397 ccr
= _prepare_ccr(&desc
->rqcfg
);
1399 idx
= thrd
->req
[0].desc
== NULL
? 0 : 1;
1404 /* First dry run to check if req is acceptable */
1405 ret
= _setup_req(pl330
, 1, thrd
, idx
, &xs
);
1409 if (ret
> pl330
->mcbufsz
/ 2) {
1410 dev_info(pl330
->ddma
.dev
, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1411 __func__
, __LINE__
, ret
, pl330
->mcbufsz
/ 2);
1416 /* Hook the request */
1418 thrd
->req
[idx
].desc
= desc
;
1419 _setup_req(pl330
, 0, thrd
, idx
, &xs
);
1424 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1429 static void dma_pl330_rqcb(struct dma_pl330_desc
*desc
, enum pl330_op_err err
)
1431 struct dma_pl330_chan
*pch
;
1432 unsigned long flags
;
1439 /* If desc aborted */
1443 spin_lock_irqsave(&pch
->lock
, flags
);
1445 desc
->status
= DONE
;
1447 spin_unlock_irqrestore(&pch
->lock
, flags
);
1449 tasklet_schedule(&pch
->task
);
1452 static void pl330_dotask(unsigned long data
)
1454 struct pl330_dmac
*pl330
= (struct pl330_dmac
*) data
;
1455 unsigned long flags
;
1458 spin_lock_irqsave(&pl330
->lock
, flags
);
1460 /* The DMAC itself gone nuts */
1461 if (pl330
->dmac_tbd
.reset_dmac
) {
1462 pl330
->state
= DYING
;
1463 /* Reset the manager too */
1464 pl330
->dmac_tbd
.reset_mngr
= true;
1465 /* Clear the reset flag */
1466 pl330
->dmac_tbd
.reset_dmac
= false;
1469 if (pl330
->dmac_tbd
.reset_mngr
) {
1470 _stop(pl330
->manager
);
1471 /* Reset all channels */
1472 pl330
->dmac_tbd
.reset_chan
= (1 << pl330
->pcfg
.num_chan
) - 1;
1473 /* Clear the reset flag */
1474 pl330
->dmac_tbd
.reset_mngr
= false;
1477 for (i
= 0; i
< pl330
->pcfg
.num_chan
; i
++) {
1479 if (pl330
->dmac_tbd
.reset_chan
& (1 << i
)) {
1480 struct pl330_thread
*thrd
= &pl330
->channels
[i
];
1481 void __iomem
*regs
= pl330
->base
;
1482 enum pl330_op_err err
;
1486 if (readl(regs
+ FSC
) & (1 << thrd
->id
))
1487 err
= PL330_ERR_FAIL
;
1489 err
= PL330_ERR_ABORT
;
1491 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1492 dma_pl330_rqcb(thrd
->req
[1 - thrd
->lstenq
].desc
, err
);
1493 dma_pl330_rqcb(thrd
->req
[thrd
->lstenq
].desc
, err
);
1494 spin_lock_irqsave(&pl330
->lock
, flags
);
1496 thrd
->req
[0].desc
= NULL
;
1497 thrd
->req
[1].desc
= NULL
;
1498 thrd
->req_running
= -1;
1500 /* Clear the reset flag */
1501 pl330
->dmac_tbd
.reset_chan
&= ~(1 << i
);
1505 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1510 /* Returns 1 if state was updated, 0 otherwise */
1511 static int pl330_update(struct pl330_dmac
*pl330
)
1513 struct dma_pl330_desc
*descdone
;
1514 unsigned long flags
;
1517 int id
, ev
, ret
= 0;
1521 spin_lock_irqsave(&pl330
->lock
, flags
);
1523 val
= readl(regs
+ FSM
) & 0x1;
1525 pl330
->dmac_tbd
.reset_mngr
= true;
1527 pl330
->dmac_tbd
.reset_mngr
= false;
1529 val
= readl(regs
+ FSC
) & ((1 << pl330
->pcfg
.num_chan
) - 1);
1530 pl330
->dmac_tbd
.reset_chan
|= val
;
1533 while (i
< pl330
->pcfg
.num_chan
) {
1534 if (val
& (1 << i
)) {
1535 dev_info(pl330
->ddma
.dev
,
1536 "Reset Channel-%d\t CS-%x FTC-%x\n",
1537 i
, readl(regs
+ CS(i
)),
1538 readl(regs
+ FTC(i
)));
1539 _stop(&pl330
->channels
[i
]);
1545 /* Check which event happened i.e, thread notified */
1546 val
= readl(regs
+ ES
);
1547 if (pl330
->pcfg
.num_events
< 32
1548 && val
& ~((1 << pl330
->pcfg
.num_events
) - 1)) {
1549 pl330
->dmac_tbd
.reset_dmac
= true;
1550 dev_err(pl330
->ddma
.dev
, "%s:%d Unexpected!\n", __func__
,
1556 for (ev
= 0; ev
< pl330
->pcfg
.num_events
; ev
++) {
1557 if (val
& (1 << ev
)) { /* Event occurred */
1558 struct pl330_thread
*thrd
;
1559 u32 inten
= readl(regs
+ INTEN
);
1562 /* Clear the event */
1563 if (inten
& (1 << ev
))
1564 writel(1 << ev
, regs
+ INTCLR
);
1568 id
= pl330
->events
[ev
];
1570 thrd
= &pl330
->channels
[id
];
1572 active
= thrd
->req_running
;
1573 if (active
== -1) /* Aborted */
1576 /* Detach the req */
1577 descdone
= thrd
->req
[active
].desc
;
1578 thrd
->req
[active
].desc
= NULL
;
1580 thrd
->req_running
= -1;
1582 /* Get going again ASAP */
1585 /* For now, just make a list of callbacks to be done */
1586 list_add_tail(&descdone
->rqd
, &pl330
->req_done
);
1590 /* Now that we are in no hurry, do the callbacks */
1591 while (!list_empty(&pl330
->req_done
)) {
1592 descdone
= list_first_entry(&pl330
->req_done
,
1593 struct dma_pl330_desc
, rqd
);
1594 list_del(&descdone
->rqd
);
1595 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1596 dma_pl330_rqcb(descdone
, PL330_ERR_NONE
);
1597 spin_lock_irqsave(&pl330
->lock
, flags
);
1601 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1603 if (pl330
->dmac_tbd
.reset_dmac
1604 || pl330
->dmac_tbd
.reset_mngr
1605 || pl330
->dmac_tbd
.reset_chan
) {
1607 tasklet_schedule(&pl330
->tasks
);
1613 /* Reserve an event */
1614 static inline int _alloc_event(struct pl330_thread
*thrd
)
1616 struct pl330_dmac
*pl330
= thrd
->dmac
;
1619 for (ev
= 0; ev
< pl330
->pcfg
.num_events
; ev
++)
1620 if (pl330
->events
[ev
] == -1) {
1621 pl330
->events
[ev
] = thrd
->id
;
1628 static bool _chan_ns(const struct pl330_dmac
*pl330
, int i
)
1630 return pl330
->pcfg
.irq_ns
& (1 << i
);
1633 /* Upon success, returns IdentityToken for the
1634 * allocated channel, NULL otherwise.
1636 static struct pl330_thread
*pl330_request_channel(struct pl330_dmac
*pl330
)
1638 struct pl330_thread
*thrd
= NULL
;
1641 if (pl330
->state
== DYING
)
1644 chans
= pl330
->pcfg
.num_chan
;
1646 for (i
= 0; i
< chans
; i
++) {
1647 thrd
= &pl330
->channels
[i
];
1648 if ((thrd
->free
) && (!_manager_ns(thrd
) ||
1649 _chan_ns(pl330
, i
))) {
1650 thrd
->ev
= _alloc_event(thrd
);
1651 if (thrd
->ev
>= 0) {
1654 thrd
->req
[0].desc
= NULL
;
1655 thrd
->req
[1].desc
= NULL
;
1656 thrd
->req_running
= -1;
1666 /* Release an event */
1667 static inline void _free_event(struct pl330_thread
*thrd
, int ev
)
1669 struct pl330_dmac
*pl330
= thrd
->dmac
;
1671 /* If the event is valid and was held by the thread */
1672 if (ev
>= 0 && ev
< pl330
->pcfg
.num_events
1673 && pl330
->events
[ev
] == thrd
->id
)
1674 pl330
->events
[ev
] = -1;
1677 static void pl330_release_channel(struct pl330_thread
*thrd
)
1679 struct pl330_dmac
*pl330
;
1681 if (!thrd
|| thrd
->free
)
1686 dma_pl330_rqcb(thrd
->req
[1 - thrd
->lstenq
].desc
, PL330_ERR_ABORT
);
1687 dma_pl330_rqcb(thrd
->req
[thrd
->lstenq
].desc
, PL330_ERR_ABORT
);
1691 _free_event(thrd
, thrd
->ev
);
1695 /* Initialize the structure for PL330 configuration, that can be used
1696 * by the client driver the make best use of the DMAC
1698 static void read_dmac_config(struct pl330_dmac
*pl330
)
1700 void __iomem
*regs
= pl330
->base
;
1703 val
= readl(regs
+ CRD
) >> CRD_DATA_WIDTH_SHIFT
;
1704 val
&= CRD_DATA_WIDTH_MASK
;
1705 pl330
->pcfg
.data_bus_width
= 8 * (1 << val
);
1707 val
= readl(regs
+ CRD
) >> CRD_DATA_BUFF_SHIFT
;
1708 val
&= CRD_DATA_BUFF_MASK
;
1709 pl330
->pcfg
.data_buf_dep
= val
+ 1;
1711 val
= readl(regs
+ CR0
) >> CR0_NUM_CHANS_SHIFT
;
1712 val
&= CR0_NUM_CHANS_MASK
;
1714 pl330
->pcfg
.num_chan
= val
;
1716 val
= readl(regs
+ CR0
);
1717 if (val
& CR0_PERIPH_REQ_SET
) {
1718 val
= (val
>> CR0_NUM_PERIPH_SHIFT
) & CR0_NUM_PERIPH_MASK
;
1720 pl330
->pcfg
.num_peri
= val
;
1721 pl330
->pcfg
.peri_ns
= readl(regs
+ CR4
);
1723 pl330
->pcfg
.num_peri
= 0;
1726 val
= readl(regs
+ CR0
);
1727 if (val
& CR0_BOOT_MAN_NS
)
1728 pl330
->pcfg
.mode
|= DMAC_MODE_NS
;
1730 pl330
->pcfg
.mode
&= ~DMAC_MODE_NS
;
1732 val
= readl(regs
+ CR0
) >> CR0_NUM_EVENTS_SHIFT
;
1733 val
&= CR0_NUM_EVENTS_MASK
;
1735 pl330
->pcfg
.num_events
= val
;
1737 pl330
->pcfg
.irq_ns
= readl(regs
+ CR3
);
1740 static inline void _reset_thread(struct pl330_thread
*thrd
)
1742 struct pl330_dmac
*pl330
= thrd
->dmac
;
1744 thrd
->req
[0].mc_cpu
= pl330
->mcode_cpu
1745 + (thrd
->id
* pl330
->mcbufsz
);
1746 thrd
->req
[0].mc_bus
= pl330
->mcode_bus
1747 + (thrd
->id
* pl330
->mcbufsz
);
1748 thrd
->req
[0].desc
= NULL
;
1750 thrd
->req
[1].mc_cpu
= thrd
->req
[0].mc_cpu
1751 + pl330
->mcbufsz
/ 2;
1752 thrd
->req
[1].mc_bus
= thrd
->req
[0].mc_bus
1753 + pl330
->mcbufsz
/ 2;
1754 thrd
->req
[1].desc
= NULL
;
1756 thrd
->req_running
= -1;
1759 static int dmac_alloc_threads(struct pl330_dmac
*pl330
)
1761 int chans
= pl330
->pcfg
.num_chan
;
1762 struct pl330_thread
*thrd
;
1765 /* Allocate 1 Manager and 'chans' Channel threads */
1766 pl330
->channels
= kzalloc((1 + chans
) * sizeof(*thrd
),
1768 if (!pl330
->channels
)
1771 /* Init Channel threads */
1772 for (i
= 0; i
< chans
; i
++) {
1773 thrd
= &pl330
->channels
[i
];
1776 _reset_thread(thrd
);
1780 /* MANAGER is indexed at the end */
1781 thrd
= &pl330
->channels
[chans
];
1785 pl330
->manager
= thrd
;
1790 static int dmac_alloc_resources(struct pl330_dmac
*pl330
)
1792 int chans
= pl330
->pcfg
.num_chan
;
1796 * Alloc MicroCode buffer for 'chans' Channel threads.
1797 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1799 pl330
->mcode_cpu
= dma_alloc_attrs(pl330
->ddma
.dev
,
1800 chans
* pl330
->mcbufsz
,
1801 &pl330
->mcode_bus
, GFP_KERNEL
,
1802 DMA_ATTR_PRIVILEGED
);
1803 if (!pl330
->mcode_cpu
) {
1804 dev_err(pl330
->ddma
.dev
, "%s:%d Can't allocate memory!\n",
1805 __func__
, __LINE__
);
1809 ret
= dmac_alloc_threads(pl330
);
1811 dev_err(pl330
->ddma
.dev
, "%s:%d Can't to create channels for DMAC!\n",
1812 __func__
, __LINE__
);
1813 dma_free_coherent(pl330
->ddma
.dev
,
1814 chans
* pl330
->mcbufsz
,
1815 pl330
->mcode_cpu
, pl330
->mcode_bus
);
1822 static int pl330_add(struct pl330_dmac
*pl330
)
1826 /* Check if we can handle this DMAC */
1827 if ((pl330
->pcfg
.periph_id
& 0xfffff) != PERIPH_ID_VAL
) {
1828 dev_err(pl330
->ddma
.dev
, "PERIPH_ID 0x%x !\n",
1829 pl330
->pcfg
.periph_id
);
1833 /* Read the configuration of the DMAC */
1834 read_dmac_config(pl330
);
1836 if (pl330
->pcfg
.num_events
== 0) {
1837 dev_err(pl330
->ddma
.dev
, "%s:%d Can't work without events!\n",
1838 __func__
, __LINE__
);
1842 spin_lock_init(&pl330
->lock
);
1844 INIT_LIST_HEAD(&pl330
->req_done
);
1846 /* Use default MC buffer size if not provided */
1847 if (!pl330
->mcbufsz
)
1848 pl330
->mcbufsz
= MCODE_BUFF_PER_REQ
* 2;
1850 /* Mark all events as free */
1851 for (i
= 0; i
< pl330
->pcfg
.num_events
; i
++)
1852 pl330
->events
[i
] = -1;
1854 /* Allocate resources needed by the DMAC */
1855 ret
= dmac_alloc_resources(pl330
);
1857 dev_err(pl330
->ddma
.dev
, "Unable to create channels for DMAC\n");
1861 tasklet_init(&pl330
->tasks
, pl330_dotask
, (unsigned long) pl330
);
1863 pl330
->state
= INIT
;
1868 static int dmac_free_threads(struct pl330_dmac
*pl330
)
1870 struct pl330_thread
*thrd
;
1873 /* Release Channel threads */
1874 for (i
= 0; i
< pl330
->pcfg
.num_chan
; i
++) {
1875 thrd
= &pl330
->channels
[i
];
1876 pl330_release_channel(thrd
);
1880 kfree(pl330
->channels
);
1885 static void pl330_del(struct pl330_dmac
*pl330
)
1887 pl330
->state
= UNINIT
;
1889 tasklet_kill(&pl330
->tasks
);
1891 /* Free DMAC resources */
1892 dmac_free_threads(pl330
);
1894 dma_free_coherent(pl330
->ddma
.dev
,
1895 pl330
->pcfg
.num_chan
* pl330
->mcbufsz
, pl330
->mcode_cpu
,
1899 /* forward declaration */
1900 static struct amba_driver pl330_driver
;
1902 static inline struct dma_pl330_chan
*
1903 to_pchan(struct dma_chan
*ch
)
1908 return container_of(ch
, struct dma_pl330_chan
, chan
);
1911 static inline struct dma_pl330_desc
*
1912 to_desc(struct dma_async_tx_descriptor
*tx
)
1914 return container_of(tx
, struct dma_pl330_desc
, txd
);
1917 static inline void fill_queue(struct dma_pl330_chan
*pch
)
1919 struct dma_pl330_desc
*desc
;
1922 list_for_each_entry(desc
, &pch
->work_list
, node
) {
1924 /* If already submitted */
1925 if (desc
->status
== BUSY
)
1928 ret
= pl330_submit_req(pch
->thread
, desc
);
1930 desc
->status
= BUSY
;
1931 } else if (ret
== -EAGAIN
) {
1932 /* QFull or DMAC Dying */
1935 /* Unacceptable request */
1936 desc
->status
= DONE
;
1937 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Bad Desc(%d)\n",
1938 __func__
, __LINE__
, desc
->txd
.cookie
);
1939 tasklet_schedule(&pch
->task
);
1944 static void pl330_tasklet(unsigned long data
)
1946 struct dma_pl330_chan
*pch
= (struct dma_pl330_chan
*)data
;
1947 struct dma_pl330_desc
*desc
, *_dt
;
1948 unsigned long flags
;
1949 bool power_down
= false;
1951 spin_lock_irqsave(&pch
->lock
, flags
);
1953 /* Pick up ripe tomatoes */
1954 list_for_each_entry_safe(desc
, _dt
, &pch
->work_list
, node
)
1955 if (desc
->status
== DONE
) {
1957 dma_cookie_complete(&desc
->txd
);
1958 list_move_tail(&desc
->node
, &pch
->completed_list
);
1961 /* Try to submit a req imm. next to the last completed cookie */
1964 if (list_empty(&pch
->work_list
)) {
1965 spin_lock(&pch
->thread
->dmac
->lock
);
1967 spin_unlock(&pch
->thread
->dmac
->lock
);
1969 pch
->active
= false;
1971 /* Make sure the PL330 Channel thread is active */
1972 spin_lock(&pch
->thread
->dmac
->lock
);
1973 _start(pch
->thread
);
1974 spin_unlock(&pch
->thread
->dmac
->lock
);
1977 while (!list_empty(&pch
->completed_list
)) {
1978 struct dmaengine_desc_callback cb
;
1980 desc
= list_first_entry(&pch
->completed_list
,
1981 struct dma_pl330_desc
, node
);
1983 dmaengine_desc_get_callback(&desc
->txd
, &cb
);
1986 desc
->status
= PREP
;
1987 list_move_tail(&desc
->node
, &pch
->work_list
);
1990 spin_lock(&pch
->thread
->dmac
->lock
);
1991 _start(pch
->thread
);
1992 spin_unlock(&pch
->thread
->dmac
->lock
);
1996 desc
->status
= FREE
;
1997 list_move_tail(&desc
->node
, &pch
->dmac
->desc_pool
);
2000 dma_descriptor_unmap(&desc
->txd
);
2002 if (dmaengine_desc_callback_valid(&cb
)) {
2003 spin_unlock_irqrestore(&pch
->lock
, flags
);
2004 dmaengine_desc_callback_invoke(&cb
, NULL
);
2005 spin_lock_irqsave(&pch
->lock
, flags
);
2008 spin_unlock_irqrestore(&pch
->lock
, flags
);
2010 /* If work list empty, power down */
2012 pm_runtime_mark_last_busy(pch
->dmac
->ddma
.dev
);
2013 pm_runtime_put_autosuspend(pch
->dmac
->ddma
.dev
);
2017 static struct dma_chan
*of_dma_pl330_xlate(struct of_phandle_args
*dma_spec
,
2018 struct of_dma
*ofdma
)
2020 int count
= dma_spec
->args_count
;
2021 struct pl330_dmac
*pl330
= ofdma
->of_dma_data
;
2022 unsigned int chan_id
;
2030 chan_id
= dma_spec
->args
[0];
2031 if (chan_id
>= pl330
->num_peripherals
)
2034 return dma_get_slave_channel(&pl330
->peripherals
[chan_id
].chan
);
2037 static int pl330_alloc_chan_resources(struct dma_chan
*chan
)
2039 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2040 struct pl330_dmac
*pl330
= pch
->dmac
;
2041 unsigned long flags
;
2043 spin_lock_irqsave(&pl330
->lock
, flags
);
2045 dma_cookie_init(chan
);
2046 pch
->cyclic
= false;
2048 pch
->thread
= pl330_request_channel(pl330
);
2050 spin_unlock_irqrestore(&pl330
->lock
, flags
);
2054 tasklet_init(&pch
->task
, pl330_tasklet
, (unsigned long) pch
);
2056 spin_unlock_irqrestore(&pl330
->lock
, flags
);
2062 * We need the data direction between the DMAC (the dma-mapping "device") and
2063 * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing!
2065 static enum dma_data_direction
2066 pl330_dma_slave_map_dir(enum dma_transfer_direction dir
)
2069 case DMA_MEM_TO_DEV
:
2070 return DMA_FROM_DEVICE
;
2071 case DMA_DEV_TO_MEM
:
2072 return DMA_TO_DEVICE
;
2073 case DMA_DEV_TO_DEV
:
2074 return DMA_BIDIRECTIONAL
;
2080 static void pl330_unprep_slave_fifo(struct dma_pl330_chan
*pch
)
2082 if (pch
->dir
!= DMA_NONE
)
2083 dma_unmap_resource(pch
->chan
.device
->dev
, pch
->fifo_dma
,
2084 1 << pch
->burst_sz
, pch
->dir
, 0);
2085 pch
->dir
= DMA_NONE
;
2089 static bool pl330_prep_slave_fifo(struct dma_pl330_chan
*pch
,
2090 enum dma_transfer_direction dir
)
2092 struct device
*dev
= pch
->chan
.device
->dev
;
2093 enum dma_data_direction dma_dir
= pl330_dma_slave_map_dir(dir
);
2095 /* Already mapped for this config? */
2096 if (pch
->dir
== dma_dir
)
2099 pl330_unprep_slave_fifo(pch
);
2100 pch
->fifo_dma
= dma_map_resource(dev
, pch
->fifo_addr
,
2101 1 << pch
->burst_sz
, dma_dir
, 0);
2102 if (dma_mapping_error(dev
, pch
->fifo_dma
))
2109 static int pl330_config(struct dma_chan
*chan
,
2110 struct dma_slave_config
*slave_config
)
2112 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2114 pl330_unprep_slave_fifo(pch
);
2115 if (slave_config
->direction
== DMA_MEM_TO_DEV
) {
2116 if (slave_config
->dst_addr
)
2117 pch
->fifo_addr
= slave_config
->dst_addr
;
2118 if (slave_config
->dst_addr_width
)
2119 pch
->burst_sz
= __ffs(slave_config
->dst_addr_width
);
2120 if (slave_config
->dst_maxburst
)
2121 pch
->burst_len
= slave_config
->dst_maxburst
;
2122 } else if (slave_config
->direction
== DMA_DEV_TO_MEM
) {
2123 if (slave_config
->src_addr
)
2124 pch
->fifo_addr
= slave_config
->src_addr
;
2125 if (slave_config
->src_addr_width
)
2126 pch
->burst_sz
= __ffs(slave_config
->src_addr_width
);
2127 if (slave_config
->src_maxburst
)
2128 pch
->burst_len
= slave_config
->src_maxburst
;
2134 static int pl330_terminate_all(struct dma_chan
*chan
)
2136 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2137 struct dma_pl330_desc
*desc
;
2138 unsigned long flags
;
2139 struct pl330_dmac
*pl330
= pch
->dmac
;
2141 bool power_down
= false;
2143 pm_runtime_get_sync(pl330
->ddma
.dev
);
2144 spin_lock_irqsave(&pch
->lock
, flags
);
2146 spin_lock(&pl330
->lock
);
2148 pch
->thread
->req
[0].desc
= NULL
;
2149 pch
->thread
->req
[1].desc
= NULL
;
2150 pch
->thread
->req_running
= -1;
2151 spin_unlock(&pl330
->lock
);
2153 power_down
= pch
->active
;
2154 pch
->active
= false;
2156 /* Mark all desc done */
2157 list_for_each_entry(desc
, &pch
->submitted_list
, node
) {
2158 desc
->status
= FREE
;
2159 dma_cookie_complete(&desc
->txd
);
2162 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2163 desc
->status
= FREE
;
2164 dma_cookie_complete(&desc
->txd
);
2167 list_splice_tail_init(&pch
->submitted_list
, &pl330
->desc_pool
);
2168 list_splice_tail_init(&pch
->work_list
, &pl330
->desc_pool
);
2169 list_splice_tail_init(&pch
->completed_list
, &pl330
->desc_pool
);
2170 spin_unlock_irqrestore(&pch
->lock
, flags
);
2171 pm_runtime_mark_last_busy(pl330
->ddma
.dev
);
2173 pm_runtime_put_autosuspend(pl330
->ddma
.dev
);
2174 pm_runtime_put_autosuspend(pl330
->ddma
.dev
);
2180 * We don't support DMA_RESUME command because of hardware
2181 * limitations, so after pausing the channel we cannot restore
2182 * it to active state. We have to terminate channel and setup
2183 * DMA transfer again. This pause feature was implemented to
2184 * allow safely read residue before channel termination.
2186 static int pl330_pause(struct dma_chan
*chan
)
2188 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2189 struct pl330_dmac
*pl330
= pch
->dmac
;
2190 unsigned long flags
;
2192 pm_runtime_get_sync(pl330
->ddma
.dev
);
2193 spin_lock_irqsave(&pch
->lock
, flags
);
2195 spin_lock(&pl330
->lock
);
2197 spin_unlock(&pl330
->lock
);
2199 spin_unlock_irqrestore(&pch
->lock
, flags
);
2200 pm_runtime_mark_last_busy(pl330
->ddma
.dev
);
2201 pm_runtime_put_autosuspend(pl330
->ddma
.dev
);
2206 static void pl330_free_chan_resources(struct dma_chan
*chan
)
2208 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2209 struct pl330_dmac
*pl330
= pch
->dmac
;
2210 unsigned long flags
;
2212 tasklet_kill(&pch
->task
);
2214 pm_runtime_get_sync(pch
->dmac
->ddma
.dev
);
2215 spin_lock_irqsave(&pl330
->lock
, flags
);
2217 pl330_release_channel(pch
->thread
);
2221 list_splice_tail_init(&pch
->work_list
, &pch
->dmac
->desc_pool
);
2223 spin_unlock_irqrestore(&pl330
->lock
, flags
);
2224 pm_runtime_mark_last_busy(pch
->dmac
->ddma
.dev
);
2225 pm_runtime_put_autosuspend(pch
->dmac
->ddma
.dev
);
2226 pl330_unprep_slave_fifo(pch
);
2229 static int pl330_get_current_xferred_count(struct dma_pl330_chan
*pch
,
2230 struct dma_pl330_desc
*desc
)
2232 struct pl330_thread
*thrd
= pch
->thread
;
2233 struct pl330_dmac
*pl330
= pch
->dmac
;
2234 void __iomem
*regs
= thrd
->dmac
->base
;
2237 pm_runtime_get_sync(pl330
->ddma
.dev
);
2239 if (desc
->rqcfg
.src_inc
) {
2240 val
= readl(regs
+ SA(thrd
->id
));
2241 addr
= desc
->px
.src_addr
;
2243 val
= readl(regs
+ DA(thrd
->id
));
2244 addr
= desc
->px
.dst_addr
;
2246 pm_runtime_mark_last_busy(pch
->dmac
->ddma
.dev
);
2247 pm_runtime_put_autosuspend(pl330
->ddma
.dev
);
2249 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
2256 static enum dma_status
2257 pl330_tx_status(struct dma_chan
*chan
, dma_cookie_t cookie
,
2258 struct dma_tx_state
*txstate
)
2260 enum dma_status ret
;
2261 unsigned long flags
;
2262 struct dma_pl330_desc
*desc
, *running
= NULL
, *last_enq
= NULL
;
2263 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2264 unsigned int transferred
, residual
= 0;
2266 ret
= dma_cookie_status(chan
, cookie
, txstate
);
2271 if (ret
== DMA_COMPLETE
)
2274 spin_lock_irqsave(&pch
->lock
, flags
);
2275 spin_lock(&pch
->thread
->dmac
->lock
);
2277 if (pch
->thread
->req_running
!= -1)
2278 running
= pch
->thread
->req
[pch
->thread
->req_running
].desc
;
2280 last_enq
= pch
->thread
->req
[pch
->thread
->lstenq
].desc
;
2282 /* Check in pending list */
2283 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2284 if (desc
->status
== DONE
)
2285 transferred
= desc
->bytes_requested
;
2286 else if (running
&& desc
== running
)
2288 pl330_get_current_xferred_count(pch
, desc
);
2289 else if (desc
->status
== BUSY
)
2291 * Busy but not running means either just enqueued,
2292 * or finished and not yet marked done
2294 if (desc
== last_enq
)
2297 transferred
= desc
->bytes_requested
;
2300 residual
+= desc
->bytes_requested
- transferred
;
2301 if (desc
->txd
.cookie
== cookie
) {
2302 switch (desc
->status
) {
2308 ret
= DMA_IN_PROGRESS
;
2318 spin_unlock(&pch
->thread
->dmac
->lock
);
2319 spin_unlock_irqrestore(&pch
->lock
, flags
);
2322 dma_set_residue(txstate
, residual
);
2327 static void pl330_issue_pending(struct dma_chan
*chan
)
2329 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2330 unsigned long flags
;
2332 spin_lock_irqsave(&pch
->lock
, flags
);
2333 if (list_empty(&pch
->work_list
)) {
2335 * Warn on nothing pending. Empty submitted_list may
2336 * break our pm_runtime usage counter as it is
2337 * updated on work_list emptiness status.
2339 WARN_ON(list_empty(&pch
->submitted_list
));
2341 pm_runtime_get_sync(pch
->dmac
->ddma
.dev
);
2343 list_splice_tail_init(&pch
->submitted_list
, &pch
->work_list
);
2344 spin_unlock_irqrestore(&pch
->lock
, flags
);
2346 pl330_tasklet((unsigned long)pch
);
2350 * We returned the last one of the circular list of descriptor(s)
2351 * from prep_xxx, so the argument to submit corresponds to the last
2352 * descriptor of the list.
2354 static dma_cookie_t
pl330_tx_submit(struct dma_async_tx_descriptor
*tx
)
2356 struct dma_pl330_desc
*desc
, *last
= to_desc(tx
);
2357 struct dma_pl330_chan
*pch
= to_pchan(tx
->chan
);
2358 dma_cookie_t cookie
;
2359 unsigned long flags
;
2361 spin_lock_irqsave(&pch
->lock
, flags
);
2363 /* Assign cookies to all nodes */
2364 while (!list_empty(&last
->node
)) {
2365 desc
= list_entry(last
->node
.next
, struct dma_pl330_desc
, node
);
2367 desc
->txd
.callback
= last
->txd
.callback
;
2368 desc
->txd
.callback_param
= last
->txd
.callback_param
;
2372 dma_cookie_assign(&desc
->txd
);
2374 list_move_tail(&desc
->node
, &pch
->submitted_list
);
2378 cookie
= dma_cookie_assign(&last
->txd
);
2379 list_add_tail(&last
->node
, &pch
->submitted_list
);
2380 spin_unlock_irqrestore(&pch
->lock
, flags
);
2385 static inline void _init_desc(struct dma_pl330_desc
*desc
)
2387 desc
->rqcfg
.swap
= SWAP_NO
;
2388 desc
->rqcfg
.scctl
= CCTRL0
;
2389 desc
->rqcfg
.dcctl
= CCTRL0
;
2390 desc
->txd
.tx_submit
= pl330_tx_submit
;
2392 INIT_LIST_HEAD(&desc
->node
);
2395 /* Returns the number of descriptors added to the DMAC pool */
2396 static int add_desc(struct pl330_dmac
*pl330
, gfp_t flg
, int count
)
2398 struct dma_pl330_desc
*desc
;
2399 unsigned long flags
;
2402 desc
= kcalloc(count
, sizeof(*desc
), flg
);
2406 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2408 for (i
= 0; i
< count
; i
++) {
2409 _init_desc(&desc
[i
]);
2410 list_add_tail(&desc
[i
].node
, &pl330
->desc_pool
);
2413 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2418 static struct dma_pl330_desc
*pluck_desc(struct pl330_dmac
*pl330
)
2420 struct dma_pl330_desc
*desc
= NULL
;
2421 unsigned long flags
;
2423 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2425 if (!list_empty(&pl330
->desc_pool
)) {
2426 desc
= list_entry(pl330
->desc_pool
.next
,
2427 struct dma_pl330_desc
, node
);
2429 list_del_init(&desc
->node
);
2431 desc
->status
= PREP
;
2432 desc
->txd
.callback
= NULL
;
2435 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2440 static struct dma_pl330_desc
*pl330_get_desc(struct dma_pl330_chan
*pch
)
2442 struct pl330_dmac
*pl330
= pch
->dmac
;
2443 u8
*peri_id
= pch
->chan
.private;
2444 struct dma_pl330_desc
*desc
;
2446 /* Pluck one desc from the pool of DMAC */
2447 desc
= pluck_desc(pl330
);
2449 /* If the DMAC pool is empty, alloc new */
2451 if (!add_desc(pl330
, GFP_ATOMIC
, 1))
2455 desc
= pluck_desc(pl330
);
2457 dev_err(pch
->dmac
->ddma
.dev
,
2458 "%s:%d ALERT!\n", __func__
, __LINE__
);
2463 /* Initialize the descriptor */
2465 desc
->txd
.cookie
= 0;
2466 async_tx_ack(&desc
->txd
);
2468 desc
->peri
= peri_id
? pch
->chan
.chan_id
: 0;
2469 desc
->rqcfg
.pcfg
= &pch
->dmac
->pcfg
;
2471 dma_async_tx_descriptor_init(&desc
->txd
, &pch
->chan
);
2476 static inline void fill_px(struct pl330_xfer
*px
,
2477 dma_addr_t dst
, dma_addr_t src
, size_t len
)
2484 static struct dma_pl330_desc
*
2485 __pl330_prep_dma_memcpy(struct dma_pl330_chan
*pch
, dma_addr_t dst
,
2486 dma_addr_t src
, size_t len
)
2488 struct dma_pl330_desc
*desc
= pl330_get_desc(pch
);
2491 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Unable to fetch desc\n",
2492 __func__
, __LINE__
);
2497 * Ideally we should lookout for reqs bigger than
2498 * those that can be programmed with 256 bytes of
2499 * MC buffer, but considering a req size is seldom
2500 * going to be word-unaligned and more than 200MB,
2502 * Also, should the limit is reached we'd rather
2503 * have the platform increase MC buffer size than
2504 * complicating this API driver.
2506 fill_px(&desc
->px
, dst
, src
, len
);
2511 /* Call after fixing burst size */
2512 static inline int get_burst_len(struct dma_pl330_desc
*desc
, size_t len
)
2514 struct dma_pl330_chan
*pch
= desc
->pchan
;
2515 struct pl330_dmac
*pl330
= pch
->dmac
;
2518 burst_len
= pl330
->pcfg
.data_bus_width
/ 8;
2519 burst_len
*= pl330
->pcfg
.data_buf_dep
/ pl330
->pcfg
.num_chan
;
2520 burst_len
>>= desc
->rqcfg
.brst_size
;
2522 /* src/dst_burst_len can't be more than 16 */
2526 while (burst_len
> 1) {
2527 if (!(len
% (burst_len
<< desc
->rqcfg
.brst_size
)))
2535 static struct dma_async_tx_descriptor
*pl330_prep_dma_cyclic(
2536 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t len
,
2537 size_t period_len
, enum dma_transfer_direction direction
,
2538 unsigned long flags
)
2540 struct dma_pl330_desc
*desc
= NULL
, *first
= NULL
;
2541 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2542 struct pl330_dmac
*pl330
= pch
->dmac
;
2547 if (len
% period_len
!= 0)
2550 if (!is_slave_direction(direction
)) {
2551 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Invalid dma direction\n",
2552 __func__
, __LINE__
);
2556 if (!pl330_prep_slave_fifo(pch
, direction
))
2559 for (i
= 0; i
< len
/ period_len
; i
++) {
2560 desc
= pl330_get_desc(pch
);
2562 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Unable to fetch desc\n",
2563 __func__
, __LINE__
);
2568 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2570 while (!list_empty(&first
->node
)) {
2571 desc
= list_entry(first
->node
.next
,
2572 struct dma_pl330_desc
, node
);
2573 list_move_tail(&desc
->node
, &pl330
->desc_pool
);
2576 list_move_tail(&first
->node
, &pl330
->desc_pool
);
2578 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2583 switch (direction
) {
2584 case DMA_MEM_TO_DEV
:
2585 desc
->rqcfg
.src_inc
= 1;
2586 desc
->rqcfg
.dst_inc
= 0;
2588 dst
= pch
->fifo_dma
;
2590 case DMA_DEV_TO_MEM
:
2591 desc
->rqcfg
.src_inc
= 0;
2592 desc
->rqcfg
.dst_inc
= 1;
2593 src
= pch
->fifo_dma
;
2600 desc
->rqtype
= direction
;
2601 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2602 desc
->rqcfg
.brst_len
= 1;
2603 desc
->bytes_requested
= period_len
;
2604 fill_px(&desc
->px
, dst
, src
, period_len
);
2609 list_add_tail(&desc
->node
, &first
->node
);
2611 dma_addr
+= period_len
;
2618 desc
->txd
.flags
= flags
;
2623 static struct dma_async_tx_descriptor
*
2624 pl330_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dst
,
2625 dma_addr_t src
, size_t len
, unsigned long flags
)
2627 struct dma_pl330_desc
*desc
;
2628 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2629 struct pl330_dmac
*pl330
;
2632 if (unlikely(!pch
|| !len
))
2637 desc
= __pl330_prep_dma_memcpy(pch
, dst
, src
, len
);
2641 desc
->rqcfg
.src_inc
= 1;
2642 desc
->rqcfg
.dst_inc
= 1;
2643 desc
->rqtype
= DMA_MEM_TO_MEM
;
2645 /* Select max possible burst size */
2646 burst
= pl330
->pcfg
.data_bus_width
/ 8;
2649 * Make sure we use a burst size that aligns with all the memcpy
2650 * parameters because our DMA programming algorithm doesn't cope with
2651 * transfers which straddle an entry in the DMA device's MFIFO.
2653 while ((src
| dst
| len
) & (burst
- 1))
2656 desc
->rqcfg
.brst_size
= 0;
2657 while (burst
!= (1 << desc
->rqcfg
.brst_size
))
2658 desc
->rqcfg
.brst_size
++;
2661 * If burst size is smaller than bus width then make sure we only
2662 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2664 if (desc
->rqcfg
.brst_size
* 8 < pl330
->pcfg
.data_bus_width
)
2665 desc
->rqcfg
.brst_len
= 1;
2667 desc
->rqcfg
.brst_len
= get_burst_len(desc
, len
);
2668 desc
->bytes_requested
= len
;
2670 desc
->txd
.flags
= flags
;
2675 static void __pl330_giveback_desc(struct pl330_dmac
*pl330
,
2676 struct dma_pl330_desc
*first
)
2678 unsigned long flags
;
2679 struct dma_pl330_desc
*desc
;
2684 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2686 while (!list_empty(&first
->node
)) {
2687 desc
= list_entry(first
->node
.next
,
2688 struct dma_pl330_desc
, node
);
2689 list_move_tail(&desc
->node
, &pl330
->desc_pool
);
2692 list_move_tail(&first
->node
, &pl330
->desc_pool
);
2694 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2697 static struct dma_async_tx_descriptor
*
2698 pl330_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
2699 unsigned int sg_len
, enum dma_transfer_direction direction
,
2700 unsigned long flg
, void *context
)
2702 struct dma_pl330_desc
*first
, *desc
= NULL
;
2703 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2704 struct scatterlist
*sg
;
2707 if (unlikely(!pch
|| !sgl
|| !sg_len
))
2710 if (!pl330_prep_slave_fifo(pch
, direction
))
2715 for_each_sg(sgl
, sg
, sg_len
, i
) {
2717 desc
= pl330_get_desc(pch
);
2719 struct pl330_dmac
*pl330
= pch
->dmac
;
2721 dev_err(pch
->dmac
->ddma
.dev
,
2722 "%s:%d Unable to fetch desc\n",
2723 __func__
, __LINE__
);
2724 __pl330_giveback_desc(pl330
, first
);
2732 list_add_tail(&desc
->node
, &first
->node
);
2734 if (direction
== DMA_MEM_TO_DEV
) {
2735 desc
->rqcfg
.src_inc
= 1;
2736 desc
->rqcfg
.dst_inc
= 0;
2737 fill_px(&desc
->px
, pch
->fifo_dma
, sg_dma_address(sg
),
2740 desc
->rqcfg
.src_inc
= 0;
2741 desc
->rqcfg
.dst_inc
= 1;
2742 fill_px(&desc
->px
, sg_dma_address(sg
), pch
->fifo_dma
,
2746 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2747 desc
->rqcfg
.brst_len
= 1;
2748 desc
->rqtype
= direction
;
2749 desc
->bytes_requested
= sg_dma_len(sg
);
2752 /* Return the last desc in the chain */
2753 desc
->txd
.flags
= flg
;
2757 static irqreturn_t
pl330_irq_handler(int irq
, void *data
)
2759 if (pl330_update(data
))
2765 #define PL330_DMA_BUSWIDTHS \
2766 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2767 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2768 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2769 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2770 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2773 * Runtime PM callbacks are provided by amba/bus.c driver.
2775 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2776 * bus driver will only disable/enable the clock in runtime PM callbacks.
2778 static int __maybe_unused
pl330_suspend(struct device
*dev
)
2780 struct amba_device
*pcdev
= to_amba_device(dev
);
2782 pm_runtime_disable(dev
);
2784 if (!pm_runtime_status_suspended(dev
)) {
2785 /* amba did not disable the clock */
2786 amba_pclk_disable(pcdev
);
2788 amba_pclk_unprepare(pcdev
);
2793 static int __maybe_unused
pl330_resume(struct device
*dev
)
2795 struct amba_device
*pcdev
= to_amba_device(dev
);
2798 ret
= amba_pclk_prepare(pcdev
);
2802 if (!pm_runtime_status_suspended(dev
))
2803 ret
= amba_pclk_enable(pcdev
);
2805 pm_runtime_enable(dev
);
2810 static SIMPLE_DEV_PM_OPS(pl330_pm
, pl330_suspend
, pl330_resume
);
2813 pl330_probe(struct amba_device
*adev
, const struct amba_id
*id
)
2815 struct pl330_config
*pcfg
;
2816 struct pl330_dmac
*pl330
;
2817 struct dma_pl330_chan
*pch
, *_p
;
2818 struct dma_device
*pd
;
2819 struct resource
*res
;
2822 struct device_node
*np
= adev
->dev
.of_node
;
2824 ret
= dma_set_mask_and_coherent(&adev
->dev
, DMA_BIT_MASK(32));
2828 /* Allocate a new DMAC and its Channels */
2829 pl330
= devm_kzalloc(&adev
->dev
, sizeof(*pl330
), GFP_KERNEL
);
2834 pd
->dev
= &adev
->dev
;
2839 for (i
= 0; i
< ARRAY_SIZE(of_quirks
); i
++)
2840 if (of_property_read_bool(np
, of_quirks
[i
].quirk
))
2841 pl330
->quirks
|= of_quirks
[i
].id
;
2844 pl330
->base
= devm_ioremap_resource(&adev
->dev
, res
);
2845 if (IS_ERR(pl330
->base
))
2846 return PTR_ERR(pl330
->base
);
2848 amba_set_drvdata(adev
, pl330
);
2850 for (i
= 0; i
< AMBA_NR_IRQS
; i
++) {
2853 ret
= devm_request_irq(&adev
->dev
, irq
,
2854 pl330_irq_handler
, 0,
2855 dev_name(&adev
->dev
), pl330
);
2863 pcfg
= &pl330
->pcfg
;
2865 pcfg
->periph_id
= adev
->periphid
;
2866 ret
= pl330_add(pl330
);
2870 INIT_LIST_HEAD(&pl330
->desc_pool
);
2871 spin_lock_init(&pl330
->pool_lock
);
2873 /* Create a descriptor pool of default size */
2874 if (!add_desc(pl330
, GFP_KERNEL
, NR_DEFAULT_DESC
))
2875 dev_warn(&adev
->dev
, "unable to allocate desc\n");
2877 INIT_LIST_HEAD(&pd
->channels
);
2879 /* Initialize channel parameters */
2880 num_chan
= max_t(int, pcfg
->num_peri
, pcfg
->num_chan
);
2882 pl330
->num_peripherals
= num_chan
;
2884 pl330
->peripherals
= kzalloc(num_chan
* sizeof(*pch
), GFP_KERNEL
);
2885 if (!pl330
->peripherals
) {
2890 for (i
= 0; i
< num_chan
; i
++) {
2891 pch
= &pl330
->peripherals
[i
];
2893 pch
->chan
.private = adev
->dev
.of_node
;
2894 INIT_LIST_HEAD(&pch
->submitted_list
);
2895 INIT_LIST_HEAD(&pch
->work_list
);
2896 INIT_LIST_HEAD(&pch
->completed_list
);
2897 spin_lock_init(&pch
->lock
);
2899 pch
->chan
.device
= pd
;
2901 pch
->dir
= DMA_NONE
;
2903 /* Add the channel to the DMAC list */
2904 list_add_tail(&pch
->chan
.device_node
, &pd
->channels
);
2907 dma_cap_set(DMA_MEMCPY
, pd
->cap_mask
);
2908 if (pcfg
->num_peri
) {
2909 dma_cap_set(DMA_SLAVE
, pd
->cap_mask
);
2910 dma_cap_set(DMA_CYCLIC
, pd
->cap_mask
);
2911 dma_cap_set(DMA_PRIVATE
, pd
->cap_mask
);
2914 pd
->device_alloc_chan_resources
= pl330_alloc_chan_resources
;
2915 pd
->device_free_chan_resources
= pl330_free_chan_resources
;
2916 pd
->device_prep_dma_memcpy
= pl330_prep_dma_memcpy
;
2917 pd
->device_prep_dma_cyclic
= pl330_prep_dma_cyclic
;
2918 pd
->device_tx_status
= pl330_tx_status
;
2919 pd
->device_prep_slave_sg
= pl330_prep_slave_sg
;
2920 pd
->device_config
= pl330_config
;
2921 pd
->device_pause
= pl330_pause
;
2922 pd
->device_terminate_all
= pl330_terminate_all
;
2923 pd
->device_issue_pending
= pl330_issue_pending
;
2924 pd
->src_addr_widths
= PL330_DMA_BUSWIDTHS
;
2925 pd
->dst_addr_widths
= PL330_DMA_BUSWIDTHS
;
2926 pd
->directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
2927 pd
->residue_granularity
= DMA_RESIDUE_GRANULARITY_BURST
;
2928 pd
->max_burst
= ((pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
) ?
2929 1 : PL330_MAX_BURST
);
2931 ret
= dma_async_device_register(pd
);
2933 dev_err(&adev
->dev
, "unable to register DMAC\n");
2937 if (adev
->dev
.of_node
) {
2938 ret
= of_dma_controller_register(adev
->dev
.of_node
,
2939 of_dma_pl330_xlate
, pl330
);
2942 "unable to register DMA to the generic DT DMA helpers\n");
2946 adev
->dev
.dma_parms
= &pl330
->dma_parms
;
2949 * This is the limit for transfers with a buswidth of 1, larger
2950 * buswidths will have larger limits.
2952 ret
= dma_set_max_seg_size(&adev
->dev
, 1900800);
2954 dev_err(&adev
->dev
, "unable to set the seg size\n");
2957 dev_info(&adev
->dev
,
2958 "Loaded driver for PL330 DMAC-%x\n", adev
->periphid
);
2959 dev_info(&adev
->dev
,
2960 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2961 pcfg
->data_buf_dep
, pcfg
->data_bus_width
/ 8, pcfg
->num_chan
,
2962 pcfg
->num_peri
, pcfg
->num_events
);
2964 pm_runtime_irq_safe(&adev
->dev
);
2965 pm_runtime_use_autosuspend(&adev
->dev
);
2966 pm_runtime_set_autosuspend_delay(&adev
->dev
, PL330_AUTOSUSPEND_DELAY
);
2967 pm_runtime_mark_last_busy(&adev
->dev
);
2968 pm_runtime_put_autosuspend(&adev
->dev
);
2973 list_for_each_entry_safe(pch
, _p
, &pl330
->ddma
.channels
,
2976 /* Remove the channel */
2977 list_del(&pch
->chan
.device_node
);
2979 /* Flush the channel */
2981 pl330_terminate_all(&pch
->chan
);
2982 pl330_free_chan_resources(&pch
->chan
);
2991 static int pl330_remove(struct amba_device
*adev
)
2993 struct pl330_dmac
*pl330
= amba_get_drvdata(adev
);
2994 struct dma_pl330_chan
*pch
, *_p
;
2997 pm_runtime_get_noresume(pl330
->ddma
.dev
);
2999 if (adev
->dev
.of_node
)
3000 of_dma_controller_free(adev
->dev
.of_node
);
3002 for (i
= 0; i
< AMBA_NR_IRQS
; i
++) {
3005 devm_free_irq(&adev
->dev
, irq
, pl330
);
3008 dma_async_device_unregister(&pl330
->ddma
);
3011 list_for_each_entry_safe(pch
, _p
, &pl330
->ddma
.channels
,
3014 /* Remove the channel */
3015 list_del(&pch
->chan
.device_node
);
3017 /* Flush the channel */
3019 pl330_terminate_all(&pch
->chan
);
3020 pl330_free_chan_resources(&pch
->chan
);
3029 static const struct amba_id pl330_ids
[] = {
3037 MODULE_DEVICE_TABLE(amba
, pl330_ids
);
3039 static struct amba_driver pl330_driver
= {
3041 .owner
= THIS_MODULE
,
3042 .name
= "dma-pl330",
3045 .id_table
= pl330_ids
,
3046 .probe
= pl330_probe
,
3047 .remove
= pl330_remove
,
3050 module_amba_driver(pl330_driver
);
3052 MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3053 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3054 MODULE_LICENSE("GPL");