2 Madge Horizon ATM Adapter driver.
3 Copyright (C) 1995-1999 Madge Networks Ltd.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
20 system and in the file COPYING in the Linux kernel source.
24 IMPORTANT NOTE: Madge Networks no longer makes the adapters
25 supported by this driver and makes no commitment to maintain it.
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/sched/signal.h>
32 #include <linux/pci.h>
33 #include <linux/errno.h>
34 #include <linux/atm.h>
35 #include <linux/atmdev.h>
36 #include <linux/sonet.h>
37 #include <linux/skbuff.h>
38 #include <linux/time.h>
39 #include <linux/delay.h>
40 #include <linux/uio.h>
41 #include <linux/init.h>
42 #include <linux/interrupt.h>
43 #include <linux/ioport.h>
44 #include <linux/wait.h>
45 #include <linux/slab.h>
48 #include <linux/atomic.h>
49 #include <linux/uaccess.h>
50 #include <asm/string.h>
51 #include <asm/byteorder.h>
55 #define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>"
56 #define description_string "Madge ATM Horizon [Ultra] driver"
57 #define version_string "1.2.1"
59 static inline void __init
show_version (void) {
60 printk ("%s version %s\n", description_string
, version_string
);
67 Driver and documentation by:
69 Chris Aston Madge Networks
70 Giuliano Procida Madge Networks
71 Simon Benham Madge Networks
72 Simon Johnson Madge Networks
73 Various Others Madge Networks
75 Some inspiration taken from other drivers by:
78 Kari Mettinen University of Helsinki
79 Werner Almesberger EPFL LRC
83 I Hardware, detection, initialisation and shutdown.
87 This driver should handle all variants of the PCI Madge ATM adapters
88 with the Horizon chipset. These are all PCI cards supporting PIO, BM
89 DMA and a form of MMIO (registers only, not internal RAM).
91 The driver is only known to work with SONET and UTP Horizon Ultra
92 cards at 155Mb/s. However, code is in place to deal with both the
93 original Horizon and 25Mb/s operation.
95 There are two revisions of the Horizon ASIC: the original and the
96 Ultra. Details of hardware bugs are in section III.
98 The ASIC version can be distinguished by chip markings but is NOT
99 indicated by the PCI revision (all adapters seem to have PCI rev 1).
103 Horizon => Collage 25 PCI Adapter (UTP and STP)
104 Horizon Ultra => Collage 155 PCI Client (UTP or SONET)
105 Ambassador x => Collage 155 PCI Server (completely different)
107 Horizon (25Mb/s) is fitted with UTP and STP connectors. It seems to
108 have a Madge B154 plus glue logic serializer. I have also found a
109 really ancient version of this with slightly different glue. It
110 comes with the revision 0 (140-025-01) ASIC.
112 Horizon Ultra (155Mb/s) is fitted with either a Pulse Medialink
113 output (UTP) or an HP HFBR 5205 output (SONET). It has either
114 Madge's SAMBA framer or a SUNI-lite device (early versions). It
115 comes with the revision 1 (140-027-01) ASIC.
119 All Horizon-based cards present with the same PCI Vendor and Device
120 IDs. The standard Linux 2.2 PCI API is used to locate any cards and
121 to enable bus-mastering (with appropriate latency).
123 ATM_LAYER_STATUS in the control register distinguishes between the
124 two possible physical layers (25 and 155). It is not clear whether
125 the 155 cards can also operate at 25Mbps. We rely on the fact that a
126 card operates at 155 if and only if it has the newer Horizon Ultra
129 For 155 cards the two possible framers are probed for and then set
134 The card is reset and then put into a known state. The physical
135 layer is configured for normal operation at the appropriate speed;
136 in the case of the 155 cards, the framer is initialised with
137 line-based timing; the internal RAM is zeroed and the allocation of
138 buffers for RX and TX is made; the Burnt In Address is read and
139 copied to the ATM ESI; various policy settings for RX (VPI bits,
140 unknown VCs, oam cells) are made. Ideally all policy items should be
141 configurable at module load (if not actually on-demand), however,
142 only the vpi vs vci bit allocation can be specified at insmod.
146 This is in response to module_cleaup. No VCs are in use and the card
147 should be idle; it is reset.
149 II Driver software (as it should be)
151 0. Traffic Parameters
153 The traffic classes (not an enumeration) are currently: ATM_NONE (no
154 traffic), ATM_UBR, ATM_CBR, ATM_VBR and ATM_ABR, ATM_ANYCLASS
155 (compatible with everything). Together with (perhaps only some of)
156 the following items they make up the traffic specification.
159 unsigned char traffic_class; traffic class (ATM_UBR, ...)
160 int max_pcr; maximum PCR in cells per second
161 int pcr; desired PCR in cells per second
162 int min_pcr; minimum PCR in cells per second
163 int max_cdv; maximum CDV in microseconds
164 int max_sdu; maximum SDU in bytes
167 Note that these denote bandwidth available not bandwidth used; the
168 possibilities according to ATMF are:
170 Real Time (cdv and max CDT given)
172 CBR(pcr) pcr bandwidth always available
173 rtVBR(pcr,scr,mbs) scr bandwidth always available, up to pcr at mbs too
177 nrtVBR(pcr,scr,mbs) scr bandwidth always available, up to pcr at mbs too
179 ABR(mcr,pcr) mcr bandwidth always available, up to pcr (depending) too
181 mbs is max burst size (bucket)
182 pcr and scr have associated cdvt values
183 mcr is like scr but has no cdtv
184 cdtv may differ at each hop
186 Some of the above items are qos items (as opposed to traffic
187 parameters). We have nothing to do with qos. All except ABR can have
188 their traffic parameters converted to GCRA parameters. The GCRA may
189 be implemented as a (real-number) leaky bucket. The GCRA can be used
190 in complicated ways by switches and in simpler ways by end-stations.
191 It can be used both to filter incoming cells and shape out-going
194 ATM Linux actually supports:
196 ATM_NONE() (no traffic in this direction)
197 ATM_UBR(max_frame_size)
198 ATM_CBR(max/min_pcr, max_cdv, max_frame_size)
200 0 or ATM_MAX_PCR are used to indicate maximum available PCR
202 A traffic specification consists of the AAL type and separate
203 traffic specifications for either direction. In ATM Linux it is:
206 struct atm_trafprm txtp;
207 struct atm_trafprm rxtp;
213 ATM_NO_AAL AAL not specified
214 ATM_AAL0 "raw" ATM cells
217 ATM_AAL34 AAL3/4 (data)
219 ATM_SAAL signaling AAL
221 The Horizon has support for AAL frame types: 0, 3/4 and 5. However,
222 it does not implement AAL 3/4 SAR and it has a different notion of
223 "raw cell" to ATM Linux's (48 bytes vs. 52 bytes) so neither are
224 supported by this driver.
226 The Horizon has limited support for ABR (including UBR), VBR and
227 CBR. Each TX channel has a bucket (containing up to 31 cell units)
228 and two timers (PCR and SCR) associated with it that can be used to
229 govern cell emissions and host notification (in the case of ABR this
230 is presumably so that RM cells may be emitted at appropriate times).
231 The timers may either be disabled or may be set to any of 240 values
232 (determined by the clock crystal, a fixed (?) per-device divider, a
233 configurable divider and a configurable timer preload value).
235 At the moment only UBR and CBR are supported by the driver. VBR will
236 be supported as soon as ATM for Linux supports it. ABR support is
237 very unlikely as RM cell handling is completely up to the driver.
239 1. TX (TX channel setup and TX transfer)
241 The TX half of the driver owns the TX Horizon registers. The TX
242 component in the IRQ handler is the BM completion handler. This can
243 only be entered when tx_busy is true (enforced by hardware). The
244 other TX component can only be entered when tx_busy is false
245 (enforced by driver). So TX is single-threaded.
247 Apart from a minor optimisation to not re-select the last channel,
248 the TX send component works as follows:
250 Atomic test and set tx_busy until we succeed; we should implement
251 some sort of timeout so that tx_busy will never be stuck at true.
253 If no TX channel is set up for this VC we wait for an idle one (if
254 necessary) and set it up.
256 At this point we have a TX channel ready for use. We wait for enough
257 buffers to become available then start a TX transmit (set the TX
258 descriptor, schedule transfer, exit).
260 The IRQ component handles TX completion (stats, free buffer, tx_busy
261 unset, exit). We also re-schedule further transfers for the same
264 TX setup in more detail:
266 TX open is a nop, the relevant information is held in the hrz_vcc
267 (vcc->dev_data) structure and is "cached" on the card.
269 TX close gets the TX lock and clears the channel from the "cache".
271 2. RX (Data Available and RX transfer)
273 The RX half of the driver owns the RX registers. There are two RX
274 components in the IRQ handler: the data available handler deals with
275 fresh data that has arrived on the card, the BM completion handler
276 is very similar to the TX completion handler. The data available
277 handler grabs the rx_lock and it is only released once the data has
278 been discarded or completely transferred to the host. The BM
279 completion handler only runs when the lock is held; the data
280 available handler is locked out over the same period.
282 Data available on the card triggers an interrupt. If the data is not
283 suitable for our existing RX channels or we cannot allocate a buffer
284 it is flushed. Otherwise an RX receive is scheduled. Multiple RX
285 transfers may be scheduled for the same frame.
287 RX setup in more detail:
294 0. Byte vs Word addressing of adapter RAM.
296 A design feature; see the .h file (especially the memory map).
298 1. Bus Master Data Transfers (original Horizon only, fixed in Ultra)
300 The host must not start a transmit direction transfer at a
301 non-four-byte boundary in host memory. Instead the host should
302 perform a byte, or a two byte, or one byte followed by two byte
303 transfer in order to start the rest of the transfer on a four byte
306 Simultaneous transmit and receive direction bus master transfers are
309 The simplest solution to these two is to always do PIO (never DMA)
310 in the TX direction on the original Horizon. More complicated
311 solutions are likely to hurt my brain.
313 2. Loss of buffer on close VC
315 When a VC is being closed, the buffer associated with it is not
316 returned to the pool. The host must store the reference to this
317 buffer and when opening a new VC then give it to that new VC.
319 The host intervention currently consists of stacking such a buffer
320 pointer at VC close and checking the stack at VC open.
322 3. Failure to close a VC
324 If a VC is currently receiving a frame then closing the VC may fail
325 and the frame continues to be received.
327 The solution is to make sure any received frames are flushed when
328 ready. This is currently done just before the solution to 2.
330 4. PCI bus (original Horizon only, fixed in Ultra)
332 Reading from the data port prior to initialisation will hang the PCI
333 bus. Just don't do that then! We don't.
337 . Timer code may be broken.
339 . Allow users to specify buffer allocation split for TX and RX.
341 . Deal once and for all with buggy VC close.
343 . Handle interrupted and/or non-blocking operations.
345 . Change some macros to functions and move from .h to .c.
347 . Try to limit the number of TX frames each VC may have queued, in
348 order to reduce the chances of TX buffer exhaustion.
350 . Implement VBR (bucket and timers not understood) and ABR (need to
351 do RM cells manually); also no Linux support for either.
353 . Implement QoS changes on open VCs (involves extracting parts of VC open
354 and close into separate functions and using them to make changes).
358 /********** globals **********/
360 static void do_housekeeping (unsigned long arg
);
362 static unsigned short debug
= 0;
363 static unsigned short vpi_bits
= 0;
364 static int max_tx_size
= 9000;
365 static int max_rx_size
= 9000;
366 static unsigned char pci_lat
= 0;
368 /********** access functions **********/
370 /* Read / Write Horizon registers */
371 static inline void wr_regl (const hrz_dev
* dev
, unsigned char reg
, u32 data
) {
372 outl (cpu_to_le32 (data
), dev
->iobase
+ reg
);
375 static inline u32
rd_regl (const hrz_dev
* dev
, unsigned char reg
) {
376 return le32_to_cpu (inl (dev
->iobase
+ reg
));
379 static inline void wr_regw (const hrz_dev
* dev
, unsigned char reg
, u16 data
) {
380 outw (cpu_to_le16 (data
), dev
->iobase
+ reg
);
383 static inline u16
rd_regw (const hrz_dev
* dev
, unsigned char reg
) {
384 return le16_to_cpu (inw (dev
->iobase
+ reg
));
387 static inline void wrs_regb (const hrz_dev
* dev
, unsigned char reg
, void * addr
, u32 len
) {
388 outsb (dev
->iobase
+ reg
, addr
, len
);
391 static inline void rds_regb (const hrz_dev
* dev
, unsigned char reg
, void * addr
, u32 len
) {
392 insb (dev
->iobase
+ reg
, addr
, len
);
395 /* Read / Write to a given address in Horizon buffer memory.
396 Interrupts must be disabled between the address register and data
397 port accesses as these must form an atomic operation. */
398 static inline void wr_mem (const hrz_dev
* dev
, HDW
* addr
, u32 data
) {
399 // wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr);
400 wr_regl (dev
, MEM_WR_ADDR_REG_OFF
, (addr
- (HDW
*) 0) * sizeof(HDW
));
401 wr_regl (dev
, MEMORY_PORT_OFF
, data
);
404 static inline u32
rd_mem (const hrz_dev
* dev
, HDW
* addr
) {
405 // wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr);
406 wr_regl (dev
, MEM_RD_ADDR_REG_OFF
, (addr
- (HDW
*) 0) * sizeof(HDW
));
407 return rd_regl (dev
, MEMORY_PORT_OFF
);
410 static inline void wr_framer (const hrz_dev
* dev
, u32 addr
, u32 data
) {
411 wr_regl (dev
, MEM_WR_ADDR_REG_OFF
, (u32
) addr
| 0x80000000);
412 wr_regl (dev
, MEMORY_PORT_OFF
, data
);
415 static inline u32
rd_framer (const hrz_dev
* dev
, u32 addr
) {
416 wr_regl (dev
, MEM_RD_ADDR_REG_OFF
, (u32
) addr
| 0x80000000);
417 return rd_regl (dev
, MEMORY_PORT_OFF
);
420 /********** specialised access functions **********/
424 static inline void FLUSH_RX_CHANNEL (hrz_dev
* dev
, u16 channel
) {
425 wr_regw (dev
, RX_CHANNEL_PORT_OFF
, FLUSH_CHANNEL
| channel
);
429 static void WAIT_FLUSH_RX_COMPLETE (hrz_dev
* dev
) {
430 while (rd_regw (dev
, RX_CHANNEL_PORT_OFF
) & FLUSH_CHANNEL
)
435 static inline void SELECT_RX_CHANNEL (hrz_dev
* dev
, u16 channel
) {
436 wr_regw (dev
, RX_CHANNEL_PORT_OFF
, channel
);
440 static void WAIT_UPDATE_COMPLETE (hrz_dev
* dev
) {
441 while (rd_regw (dev
, RX_CHANNEL_PORT_OFF
) & RX_CHANNEL_UPDATE_IN_PROGRESS
)
448 static inline void SELECT_TX_CHANNEL (hrz_dev
* dev
, u16 tx_channel
) {
449 wr_regl (dev
, TX_CHANNEL_PORT_OFF
, tx_channel
);
453 /* Update or query one configuration parameter of a particular channel. */
455 static inline void update_tx_channel_config (hrz_dev
* dev
, short chan
, u8 mode
, u16 value
) {
456 wr_regw (dev
, TX_CHANNEL_CONFIG_COMMAND_OFF
,
457 chan
* TX_CHANNEL_CONFIG_MULT
| mode
);
458 wr_regw (dev
, TX_CHANNEL_CONFIG_DATA_OFF
, value
);
462 /********** dump functions **********/
464 static inline void dump_skb (char * prefix
, unsigned int vc
, struct sk_buff
* skb
) {
467 unsigned char * data
= skb
->data
;
468 PRINTDB (DBG_DATA
, "%s(%u) ", prefix
, vc
);
469 for (i
=0; i
<skb
->len
&& i
< 256;i
++)
470 PRINTDM (DBG_DATA
, "%02x ", data
[i
]);
471 PRINTDE (DBG_DATA
,"");
480 static inline void dump_regs (hrz_dev
* dev
) {
482 PRINTD (DBG_REGS
, "CONTROL 0: %#x", rd_regl (dev
, CONTROL_0_REG
));
483 PRINTD (DBG_REGS
, "RX CONFIG: %#x", rd_regw (dev
, RX_CONFIG_OFF
));
484 PRINTD (DBG_REGS
, "TX CONFIG: %#x", rd_regw (dev
, TX_CONFIG_OFF
));
485 PRINTD (DBG_REGS
, "TX STATUS: %#x", rd_regw (dev
, TX_STATUS_OFF
));
486 PRINTD (DBG_REGS
, "IRQ ENBLE: %#x", rd_regl (dev
, INT_ENABLE_REG_OFF
));
487 PRINTD (DBG_REGS
, "IRQ SORCE: %#x", rd_regl (dev
, INT_SOURCE_REG_OFF
));
494 static inline void dump_framer (hrz_dev
* dev
) {
497 PRINTDB (DBG_REGS
, "framer registers:");
498 for (i
= 0; i
< 0x10; ++i
)
499 PRINTDM (DBG_REGS
, " %02x", rd_framer (dev
, i
));
500 PRINTDE (DBG_REGS
,"");
507 /********** VPI/VCI <-> (RX) channel conversions **********/
509 /* RX channels are 10 bit integers, these fns are quite paranoid */
511 static inline int vpivci_to_channel (u16
* channel
, const short vpi
, const int vci
) {
512 unsigned short vci_bits
= 10 - vpi_bits
;
513 if (0 <= vpi
&& vpi
< 1<<vpi_bits
&& 0 <= vci
&& vci
< 1<<vci_bits
) {
514 *channel
= vpi
<<vci_bits
| vci
;
515 return *channel
? 0 : -EINVAL
;
520 /********** decode RX queue entries **********/
522 static inline u16
rx_q_entry_to_length (u32 x
) {
523 return x
& RX_Q_ENTRY_LENGTH_MASK
;
526 static inline u16
rx_q_entry_to_rx_channel (u32 x
) {
527 return (x
>>RX_Q_ENTRY_CHANNEL_SHIFT
) & RX_CHANNEL_MASK
;
530 /* Cell Transmit Rate Values
532 * the cell transmit rate (cells per sec) can be set to a variety of
533 * different values by specifying two parameters: a timer preload from
534 * 1 to 16 (stored as 0 to 15) and a clock divider (2 to the power of
535 * an exponent from 0 to 14; the special value 15 disables the timer).
537 * cellrate = baserate / (preload * 2^divider)
539 * The maximum cell rate that can be specified is therefore just the
540 * base rate. Halving the preload is equivalent to adding 1 to the
541 * divider and so values 1 to 8 of the preload are redundant except
542 * in the case of a maximal divider (14).
544 * Given a desired cell rate, an algorithm to determine the preload
547 * a) x = baserate / cellrate, want p * 2^d = x (as far as possible)
548 * b) if x > 16 * 2^14 then set p = 16, d = 14 (min rate), done
549 * if x <= 16 then set p = x, d = 0 (high rates), done
550 * c) now have 16 < x <= 2^18, or 1 < x/16 <= 2^14 and we want to
551 * know n such that 2^(n-1) < x/16 <= 2^n, so slide a bit until
552 * we find the range (n will be between 1 and 14), set d = n
553 * d) Also have 8 < x/2^n <= 16, so set p nearest x/2^n
555 * The algorithm used below is a minor variant of the above.
557 * The base rate is derived from the oscillator frequency (Hz) using a
560 * baserate = freq / 32 in the case of some Unknown Card
561 * baserate = freq / 8 in the case of the Horizon 25
562 * baserate = freq / 8 in the case of the Horizon Ultra 155
564 * The Horizon cards have oscillators and base rates as follows:
566 * Card Oscillator Base Rate
567 * Unknown Card 33 MHz 1.03125 MHz (33 MHz = PCI freq)
568 * Horizon 25 32 MHz 4 MHz
569 * Horizon Ultra 155 40 MHz 5 MHz
571 * The following defines give the base rates in Hz. These were
572 * previously a factor of 100 larger, no doubt someone was using
576 #define BR_UKN 1031250l
577 #define BR_HRZ 4000000l
578 #define BR_ULT 5000000l
584 // p ranges from 1 to a power of 2
587 static int make_rate (const hrz_dev
* dev
, u32 c
, rounding r
,
588 u16
* bits
, unsigned int * actual
)
590 // note: rounding the rate down means rounding 'p' up
591 const unsigned long br
= test_bit(ultra
, &dev
->flags
) ? BR_ULT
: BR_HRZ
;
596 // br_exp and br_man are used to avoid overflowing (c*maxp*2^d) in
597 // the tests below. We could think harder about exact possibilities
600 unsigned long br_man
= br
;
601 unsigned int br_exp
= 0;
603 PRINTD (DBG_QOS
|DBG_FLOW
, "make_rate b=%lu, c=%u, %s", br
, c
,
604 r
== round_up
? "up" : r
== round_down
? "down" : "nearest");
608 PRINTD (DBG_QOS
|DBG_ERR
, "zero rate is not allowed!");
612 while (br_exp
< CR_MAXPEXP
+ CR_MIND
&& (br_man
% 2 == 0)) {
613 br_man
= br_man
>> 1;
616 // (br >>br_exp) <<br_exp == br and
617 // br_exp <= CR_MAXPEXP+CR_MIND
619 if (br_man
<= (c
<< (CR_MAXPEXP
+CR_MIND
-br_exp
))) {
620 // Equivalent to: B <= (c << (MAXPEXP+MIND))
621 // take care of rounding
624 pre
= DIV_ROUND_UP(br
, c
<<div
);
625 // but p must be non-zero
630 pre
= DIV_ROUND_CLOSEST(br
, c
<<div
);
631 // but p must be non-zero
635 default: /* round_up */
637 // but p must be non-zero
641 PRINTD (DBG_QOS
, "A: p=%u, d=%u", pre
, div
);
645 // at this point we have
646 // d == MIND and (c << (MAXPEXP+MIND)) < B
647 while (div
< CR_MAXD
) {
649 if (br_man
<= (c
<< (CR_MAXPEXP
+div
-br_exp
))) {
650 // Equivalent to: B <= (c << (MAXPEXP+d))
651 // c << (MAXPEXP+d-1) < B <= c << (MAXPEXP+d)
652 // 1 << (MAXPEXP-1) < B/2^d/c <= 1 << MAXPEXP
653 // MAXP/2 < B/c2^d <= MAXP
654 // take care of rounding
657 pre
= DIV_ROUND_UP(br
, c
<<div
);
660 pre
= DIV_ROUND_CLOSEST(br
, c
<<div
);
662 default: /* round_up */
665 PRINTD (DBG_QOS
, "B: p=%u, d=%u", pre
, div
);
669 // at this point we have
670 // d == MAXD and (c << (MAXPEXP+MAXD)) < B
671 // but we cannot go any higher
672 // take care of rounding
675 pre
= 1 << CR_MAXPEXP
;
676 PRINTD (DBG_QOS
, "C: p=%u, d=%u", pre
, div
);
679 if (div
> CR_MAXD
|| (!pre
) || pre
> 1<<CR_MAXPEXP
) {
680 PRINTD (DBG_QOS
, "set_cr internal failure: d=%u p=%u",
685 *bits
= (div
<<CLOCK_SELECT_SHIFT
) | (pre
-1);
687 *actual
= DIV_ROUND_UP(br
, pre
<<div
);
688 PRINTD (DBG_QOS
, "actual rate: %u", *actual
);
694 static int make_rate_with_tolerance (const hrz_dev
* dev
, u32 c
, rounding r
, unsigned int tol
,
695 u16
* bit_pattern
, unsigned int * actual
) {
696 unsigned int my_actual
;
698 PRINTD (DBG_QOS
|DBG_FLOW
, "make_rate_with_tolerance c=%u, %s, tol=%u",
699 c
, (r
== round_up
) ? "up" : (r
== round_down
) ? "down" : "nearest", tol
);
702 // actual rate is not returned
705 if (make_rate (dev
, c
, round_nearest
, bit_pattern
, actual
))
706 // should never happen as round_nearest always succeeds
709 if (c
- tol
<= *actual
&& *actual
<= c
+ tol
)
713 // intolerant, try rounding instead
714 return make_rate (dev
, c
, r
, bit_pattern
, actual
);
717 /********** Listen on a VC **********/
719 static int hrz_open_rx (hrz_dev
* dev
, u16 channel
) {
720 // is there any guarantee that we don't get two simulataneous
721 // identical calls of this function from different processes? yes
724 u32 channel_type
; // u16?
726 u16 buf_ptr
= RX_CHANNEL_IDLE
;
728 rx_ch_desc
* rx_desc
= &memmap
->rx_descs
[channel
];
730 PRINTD (DBG_FLOW
, "hrz_open_rx %x", channel
);
732 spin_lock_irqsave (&dev
->mem_lock
, flags
);
733 channel_type
= rd_mem (dev
, &rx_desc
->wr_buf_type
) & BUFFER_PTR_MASK
;
734 spin_unlock_irqrestore (&dev
->mem_lock
, flags
);
736 // very serious error, should never occur
737 if (channel_type
!= RX_CHANNEL_DISABLED
) {
738 PRINTD (DBG_ERR
|DBG_VCC
, "RX channel for VC already open");
739 return -EBUSY
; // clean up?
742 // Give back spare buffer
743 if (dev
->noof_spare_buffers
) {
744 buf_ptr
= dev
->spare_buffers
[--dev
->noof_spare_buffers
];
745 PRINTD (DBG_VCC
, "using a spare buffer: %u", buf_ptr
);
746 // should never occur
747 if (buf_ptr
== RX_CHANNEL_DISABLED
|| buf_ptr
== RX_CHANNEL_IDLE
) {
748 // but easy to recover from
749 PRINTD (DBG_ERR
|DBG_VCC
, "bad spare buffer pointer, using IDLE");
750 buf_ptr
= RX_CHANNEL_IDLE
;
753 PRINTD (DBG_VCC
, "using IDLE buffer pointer");
756 // Channel is currently disabled so change its status to idle
758 // do we really need to save the flags again?
759 spin_lock_irqsave (&dev
->mem_lock
, flags
);
761 wr_mem (dev
, &rx_desc
->wr_buf_type
,
762 buf_ptr
| CHANNEL_TYPE_AAL5
| FIRST_CELL_OF_AAL5_FRAME
);
763 if (buf_ptr
!= RX_CHANNEL_IDLE
)
764 wr_mem (dev
, &rx_desc
->rd_buf_type
, buf_ptr
);
766 spin_unlock_irqrestore (&dev
->mem_lock
, flags
);
768 // rxer->rate = make_rate (qos->peak_cells);
770 PRINTD (DBG_FLOW
, "hrz_open_rx ok");
776 /********** change vc rate for a given vc **********/
778 static void hrz_change_vc_qos (ATM_RXER
* rxer
, MAAL_QOS
* qos
) {
779 rxer
->rate
= make_rate (qos
->peak_cells
);
783 /********** free an skb (as per ATM device driver documentation) **********/
785 static void hrz_kfree_skb (struct sk_buff
* skb
) {
786 if (ATM_SKB(skb
)->vcc
->pop
) {
787 ATM_SKB(skb
)->vcc
->pop (ATM_SKB(skb
)->vcc
, skb
);
789 dev_kfree_skb_any (skb
);
793 /********** cancel listen on a VC **********/
795 static void hrz_close_rx (hrz_dev
* dev
, u16 vc
) {
802 rx_ch_desc
* rx_desc
= &memmap
->rx_descs
[vc
];
806 spin_lock_irqsave (&dev
->mem_lock
, flags
);
807 value
= rd_mem (dev
, &rx_desc
->wr_buf_type
) & BUFFER_PTR_MASK
;
808 spin_unlock_irqrestore (&dev
->mem_lock
, flags
);
810 if (value
== RX_CHANNEL_DISABLED
) {
811 // I suppose this could happen once we deal with _NONE traffic properly
812 PRINTD (DBG_VCC
, "closing VC: RX channel %u already disabled", vc
);
815 if (value
== RX_CHANNEL_IDLE
)
818 spin_lock_irqsave (&dev
->mem_lock
, flags
);
821 wr_mem (dev
, &rx_desc
->wr_buf_type
, RX_CHANNEL_DISABLED
);
823 if ((rd_mem (dev
, &rx_desc
->wr_buf_type
) & BUFFER_PTR_MASK
) == RX_CHANNEL_DISABLED
)
830 spin_unlock_irqrestore (&dev
->mem_lock
, flags
);
834 WAIT_FLUSH_RX_COMPLETE(dev
);
836 // XXX Is this all really necessary? We can rely on the rx_data_av
837 // handler to discard frames that remain queued for delivery. If the
838 // worry is that immediately reopening the channel (perhaps by a
839 // different process) may cause some data to be mis-delivered then
840 // there may still be a simpler solution (such as busy-waiting on
841 // rx_busy once the channel is disabled or before a new one is
842 // opened - does this leave any holes?). Arguably setting up and
843 // tearing down the TX and RX halves of each virtual circuit could
844 // most safely be done within ?x_busy protected regions.
846 // OK, current changes are that Simon's marker is disabled and we DO
847 // look for NULL rxer elsewhere. The code here seems flush frames
848 // and then remember the last dead cell belonging to the channel
849 // just disabled - the cell gets relinked at the next vc_open.
850 // However, when all VCs are closed or only a few opened there are a
851 // handful of buffers that are unusable.
853 // Does anyone feel like documenting spare_buffers properly?
854 // Does anyone feel like fixing this in a nicer way?
856 // Flush any data which is left in the channel
858 // Change the rx channel port to something different to the RX
859 // channel we are trying to close to force Horizon to flush the rx
860 // channel read and write pointers.
862 u16 other
= vc
^(RX_CHANS
/2);
864 SELECT_RX_CHANNEL (dev
, other
);
865 WAIT_UPDATE_COMPLETE (dev
);
867 r1
= rd_mem (dev
, &rx_desc
->rd_buf_type
);
869 // Select this RX channel. Flush doesn't seem to work unless we
870 // select an RX channel before hand
872 SELECT_RX_CHANNEL (dev
, vc
);
873 WAIT_UPDATE_COMPLETE (dev
);
875 // Attempt to flush a frame on this RX channel
877 FLUSH_RX_CHANNEL (dev
, vc
);
878 WAIT_FLUSH_RX_COMPLETE (dev
);
880 // Force Horizon to flush rx channel read and write pointers as before
882 SELECT_RX_CHANNEL (dev
, other
);
883 WAIT_UPDATE_COMPLETE (dev
);
885 r2
= rd_mem (dev
, &rx_desc
->rd_buf_type
);
887 PRINTD (DBG_VCC
|DBG_RX
, "r1 = %u, r2 = %u", r1
, r2
);
890 dev
->spare_buffers
[dev
->noof_spare_buffers
++] = (u16
)r1
;
897 rx_q_entry
* wr_ptr
= &memmap
->rx_q_entries
[rd_regw (dev
, RX_QUEUE_WR_PTR_OFF
)];
898 rx_q_entry
* rd_ptr
= dev
->rx_q_entry
;
900 PRINTD (DBG_VCC
|DBG_RX
, "rd_ptr = %u, wr_ptr = %u", rd_ptr
, wr_ptr
);
902 while (rd_ptr
!= wr_ptr
) {
903 u32 x
= rd_mem (dev
, (HDW
*) rd_ptr
);
905 if (vc
== rx_q_entry_to_rx_channel (x
)) {
906 x
|= SIMONS_DODGEY_MARKER
;
908 PRINTD (DBG_RX
|DBG_VCC
|DBG_WARN
, "marking a frame as dodgey");
910 wr_mem (dev
, (HDW
*) rd_ptr
, x
);
913 if (rd_ptr
== dev
->rx_q_wrap
)
914 rd_ptr
= dev
->rx_q_reset
;
921 spin_unlock_irqrestore (&dev
->mem_lock
, flags
);
926 /********** schedule RX transfers **********/
928 // Note on tail recursion: a GCC developer said that it is not likely
929 // to be fixed soon, so do not define TAILRECUSRIONWORKS unless you
930 // are sure it does as you may otherwise overflow the kernel stack.
932 // giving this fn a return value would help GCC, allegedly
934 static void rx_schedule (hrz_dev
* dev
, int irq
) {
935 unsigned int rx_bytes
;
938 #ifndef TAILRECURSIONWORKS
940 while (pio_instead
) {
942 // bytes waiting for RX transfer
943 rx_bytes
= dev
->rx_bytes
;
947 while (rd_regl (dev
, MASTER_RX_COUNT_REG_OFF
)) {
948 PRINTD (DBG_RX
|DBG_WARN
, "RX error: other PCI Bus Master RX still in progress!");
949 if (++spin_count
> 10) {
950 PRINTD (DBG_RX
|DBG_ERR
, "spun out waiting PCI Bus Master RX completion");
951 wr_regl (dev
, MASTER_RX_COUNT_REG_OFF
, 0);
952 clear_bit (rx_busy
, &dev
->flags
);
953 hrz_kfree_skb (dev
->rx_skb
);
959 // this code follows the TX code but (at the moment) there is only
960 // one region - the skb itself. I don't know if this will change,
961 // but it doesn't hurt to have the code here, disabled.
964 // start next transfer within same region
965 if (rx_bytes
<= MAX_PIO_COUNT
) {
966 PRINTD (DBG_RX
|DBG_BUS
, "(pio)");
969 if (rx_bytes
<= MAX_TRANSFER_COUNT
) {
970 PRINTD (DBG_RX
|DBG_BUS
, "(simple or last multi)");
973 PRINTD (DBG_RX
|DBG_BUS
, "(continuing multi)");
974 dev
->rx_bytes
= rx_bytes
- MAX_TRANSFER_COUNT
;
975 rx_bytes
= MAX_TRANSFER_COUNT
;
978 // rx_bytes == 0 -- we're between regions
979 // regions remaining to transfer
981 unsigned int rx_regions
= dev
->rx_regions
;
983 unsigned int rx_regions
= 0;
988 // start a new region
989 dev
->rx_addr
= dev
->rx_iovec
->iov_base
;
990 rx_bytes
= dev
->rx_iovec
->iov_len
;
992 dev
->rx_regions
= rx_regions
- 1;
994 if (rx_bytes
<= MAX_PIO_COUNT
) {
995 PRINTD (DBG_RX
|DBG_BUS
, "(pio)");
998 if (rx_bytes
<= MAX_TRANSFER_COUNT
) {
999 PRINTD (DBG_RX
|DBG_BUS
, "(full region)");
1002 PRINTD (DBG_RX
|DBG_BUS
, "(start multi region)");
1003 dev
->rx_bytes
= rx_bytes
- MAX_TRANSFER_COUNT
;
1004 rx_bytes
= MAX_TRANSFER_COUNT
;
1009 // that's all folks - end of frame
1010 struct sk_buff
* skb
= dev
->rx_skb
;
1011 // dev->rx_iovec = 0;
1013 FLUSH_RX_CHANNEL (dev
, dev
->rx_channel
);
1015 dump_skb ("<<<", dev
->rx_channel
, skb
);
1017 PRINTD (DBG_RX
|DBG_SKB
, "push %p %u", skb
->data
, skb
->len
);
1020 struct atm_vcc
* vcc
= ATM_SKB(skb
)->vcc
;
1022 atomic_inc(&vcc
->stats
->rx
);
1023 __net_timestamp(skb
);
1024 // end of our responsibility
1025 vcc
->push (vcc
, skb
);
1030 // note: writing RX_COUNT clears any interrupt condition
1034 wr_regl (dev
, MASTER_RX_COUNT_REG_OFF
, 0);
1035 rds_regb (dev
, DATA_PORT_OFF
, dev
->rx_addr
, rx_bytes
);
1037 wr_regl (dev
, MASTER_RX_ADDR_REG_OFF
, virt_to_bus (dev
->rx_addr
));
1038 wr_regl (dev
, MASTER_RX_COUNT_REG_OFF
, rx_bytes
);
1040 dev
->rx_addr
+= rx_bytes
;
1043 wr_regl (dev
, MASTER_RX_COUNT_REG_OFF
, 0);
1044 // allow another RX thread to start
1046 clear_bit (rx_busy
, &dev
->flags
);
1047 PRINTD (DBG_RX
, "cleared rx_busy for dev %p", dev
);
1050 #ifdef TAILRECURSIONWORKS
1051 // and we all bless optimised tail calls
1053 return rx_schedule (dev
, 0);
1063 /********** handle RX bus master complete events **********/
1065 static void rx_bus_master_complete_handler (hrz_dev
* dev
) {
1066 if (test_bit (rx_busy
, &dev
->flags
)) {
1067 rx_schedule (dev
, 1);
1069 PRINTD (DBG_RX
|DBG_ERR
, "unexpected RX bus master completion");
1070 // clear interrupt condition on adapter
1071 wr_regl (dev
, MASTER_RX_COUNT_REG_OFF
, 0);
1076 /********** (queue to) become the next TX thread **********/
1078 static int tx_hold (hrz_dev
* dev
) {
1079 PRINTD (DBG_TX
, "sleeping at tx lock %p %lu", dev
, dev
->flags
);
1080 wait_event_interruptible(dev
->tx_queue
, (!test_and_set_bit(tx_busy
, &dev
->flags
)));
1081 PRINTD (DBG_TX
, "woken at tx lock %p %lu", dev
, dev
->flags
);
1082 if (signal_pending (current
))
1084 PRINTD (DBG_TX
, "set tx_busy for dev %p", dev
);
1088 /********** allow another TX thread to start **********/
1090 static inline void tx_release (hrz_dev
* dev
) {
1091 clear_bit (tx_busy
, &dev
->flags
);
1092 PRINTD (DBG_TX
, "cleared tx_busy for dev %p", dev
);
1093 wake_up_interruptible (&dev
->tx_queue
);
1096 /********** schedule TX transfers **********/
1098 static void tx_schedule (hrz_dev
* const dev
, int irq
) {
1099 unsigned int tx_bytes
;
1101 int append_desc
= 0;
1103 int pio_instead
= 0;
1104 #ifndef TAILRECURSIONWORKS
1106 while (pio_instead
) {
1108 // bytes in current region waiting for TX transfer
1109 tx_bytes
= dev
->tx_bytes
;
1113 while (rd_regl (dev
, MASTER_TX_COUNT_REG_OFF
)) {
1114 PRINTD (DBG_TX
|DBG_WARN
, "TX error: other PCI Bus Master TX still in progress!");
1115 if (++spin_count
> 10) {
1116 PRINTD (DBG_TX
|DBG_ERR
, "spun out waiting PCI Bus Master TX completion");
1117 wr_regl (dev
, MASTER_TX_COUNT_REG_OFF
, 0);
1119 hrz_kfree_skb (dev
->tx_skb
);
1126 // start next transfer within same region
1127 if (!test_bit (ultra
, &dev
->flags
) || tx_bytes
<= MAX_PIO_COUNT
) {
1128 PRINTD (DBG_TX
|DBG_BUS
, "(pio)");
1131 if (tx_bytes
<= MAX_TRANSFER_COUNT
) {
1132 PRINTD (DBG_TX
|DBG_BUS
, "(simple or last multi)");
1133 if (!dev
->tx_iovec
) {
1134 // end of last region
1139 PRINTD (DBG_TX
|DBG_BUS
, "(continuing multi)");
1140 dev
->tx_bytes
= tx_bytes
- MAX_TRANSFER_COUNT
;
1141 tx_bytes
= MAX_TRANSFER_COUNT
;
1144 // tx_bytes == 0 -- we're between regions
1145 // regions remaining to transfer
1146 unsigned int tx_regions
= dev
->tx_regions
;
1149 // start a new region
1150 dev
->tx_addr
= dev
->tx_iovec
->iov_base
;
1151 tx_bytes
= dev
->tx_iovec
->iov_len
;
1153 dev
->tx_regions
= tx_regions
- 1;
1155 if (!test_bit (ultra
, &dev
->flags
) || tx_bytes
<= MAX_PIO_COUNT
) {
1156 PRINTD (DBG_TX
|DBG_BUS
, "(pio)");
1159 if (tx_bytes
<= MAX_TRANSFER_COUNT
) {
1160 PRINTD (DBG_TX
|DBG_BUS
, "(full region)");
1163 PRINTD (DBG_TX
|DBG_BUS
, "(start multi region)");
1164 dev
->tx_bytes
= tx_bytes
- MAX_TRANSFER_COUNT
;
1165 tx_bytes
= MAX_TRANSFER_COUNT
;
1169 // that's all folks - end of frame
1170 struct sk_buff
* skb
= dev
->tx_skb
;
1171 dev
->tx_iovec
= NULL
;
1174 atomic_inc(&ATM_SKB(skb
)->vcc
->stats
->tx
);
1177 hrz_kfree_skb (skb
);
1181 // note: writing TX_COUNT clears any interrupt condition
1185 wr_regl (dev
, MASTER_TX_COUNT_REG_OFF
, 0);
1186 wrs_regb (dev
, DATA_PORT_OFF
, dev
->tx_addr
, tx_bytes
);
1188 wr_regl (dev
, TX_DESCRIPTOR_PORT_OFF
, cpu_to_be32 (dev
->tx_skb
->len
));
1190 wr_regl (dev
, MASTER_TX_ADDR_REG_OFF
, virt_to_bus (dev
->tx_addr
));
1192 wr_regl (dev
, TX_DESCRIPTOR_REG_OFF
, cpu_to_be32 (dev
->tx_skb
->len
));
1193 wr_regl (dev
, MASTER_TX_COUNT_REG_OFF
,
1195 ? tx_bytes
| MASTER_TX_AUTO_APPEND_DESC
1198 dev
->tx_addr
+= tx_bytes
;
1201 wr_regl (dev
, MASTER_TX_COUNT_REG_OFF
, 0);
1206 #ifdef TAILRECURSIONWORKS
1207 // and we all bless optimised tail calls
1209 return tx_schedule (dev
, 0);
1219 /********** handle TX bus master complete events **********/
1221 static void tx_bus_master_complete_handler (hrz_dev
* dev
) {
1222 if (test_bit (tx_busy
, &dev
->flags
)) {
1223 tx_schedule (dev
, 1);
1225 PRINTD (DBG_TX
|DBG_ERR
, "unexpected TX bus master completion");
1226 // clear interrupt condition on adapter
1227 wr_regl (dev
, MASTER_TX_COUNT_REG_OFF
, 0);
1232 /********** move RX Q pointer to next item in circular buffer **********/
1234 // called only from IRQ sub-handler
1235 static u32
rx_queue_entry_next (hrz_dev
* dev
) {
1237 spin_lock (&dev
->mem_lock
);
1238 rx_queue_entry
= rd_mem (dev
, &dev
->rx_q_entry
->entry
);
1239 if (dev
->rx_q_entry
== dev
->rx_q_wrap
)
1240 dev
->rx_q_entry
= dev
->rx_q_reset
;
1243 wr_regw (dev
, RX_QUEUE_RD_PTR_OFF
, dev
->rx_q_entry
- dev
->rx_q_reset
);
1244 spin_unlock (&dev
->mem_lock
);
1245 return rx_queue_entry
;
1248 /********** handle RX data received by device **********/
1250 // called from IRQ handler
1251 static void rx_data_av_handler (hrz_dev
* dev
) {
1253 u32 rx_queue_entry_flags
;
1257 PRINTD (DBG_FLOW
, "hrz_data_av_handler");
1259 // try to grab rx lock (not possible during RX bus mastering)
1260 if (test_and_set_bit (rx_busy
, &dev
->flags
)) {
1261 PRINTD (DBG_RX
, "locked out of rx lock");
1264 PRINTD (DBG_RX
, "set rx_busy for dev %p", dev
);
1265 // lock is cleared if we fail now, o/w after bus master completion
1267 YELLOW_LED_OFF(dev
);
1269 rx_queue_entry
= rx_queue_entry_next (dev
);
1271 rx_len
= rx_q_entry_to_length (rx_queue_entry
);
1272 rx_channel
= rx_q_entry_to_rx_channel (rx_queue_entry
);
1274 WAIT_FLUSH_RX_COMPLETE (dev
);
1276 SELECT_RX_CHANNEL (dev
, rx_channel
);
1278 PRINTD (DBG_RX
, "rx_queue_entry is: %#x", rx_queue_entry
);
1279 rx_queue_entry_flags
= rx_queue_entry
& (RX_CRC_32_OK
|RX_COMPLETE_FRAME
|SIMONS_DODGEY_MARKER
);
1282 // (at least) bus-mastering breaks if we try to handle a
1283 // zero-length frame, besides AAL5 does not support them
1284 PRINTK (KERN_ERR
, "zero-length frame!");
1285 rx_queue_entry_flags
&= ~RX_COMPLETE_FRAME
;
1288 if (rx_queue_entry_flags
& SIMONS_DODGEY_MARKER
) {
1289 PRINTD (DBG_RX
|DBG_ERR
, "Simon's marker detected!");
1291 if (rx_queue_entry_flags
== (RX_CRC_32_OK
| RX_COMPLETE_FRAME
)) {
1292 struct atm_vcc
* atm_vcc
;
1294 PRINTD (DBG_RX
, "got a frame on rx_channel %x len %u", rx_channel
, rx_len
);
1296 atm_vcc
= dev
->rxer
[rx_channel
];
1297 // if no vcc is assigned to this channel, we should drop the frame
1298 // (is this what SIMONS etc. was trying to achieve?)
1302 if (atm_vcc
->qos
.rxtp
.traffic_class
!= ATM_NONE
) {
1304 if (rx_len
<= atm_vcc
->qos
.rxtp
.max_sdu
) {
1306 struct sk_buff
* skb
= atm_alloc_charge (atm_vcc
, rx_len
, GFP_ATOMIC
);
1308 // remember this so we can push it later
1310 // remember this so we can flush it later
1311 dev
->rx_channel
= rx_channel
;
1313 // prepare socket buffer
1314 skb_put (skb
, rx_len
);
1315 ATM_SKB(skb
)->vcc
= atm_vcc
;
1318 // dev->rx_regions = 0;
1319 // dev->rx_iovec = 0;
1320 dev
->rx_bytes
= rx_len
;
1321 dev
->rx_addr
= skb
->data
;
1322 PRINTD (DBG_RX
, "RX start simple transfer (addr %p, len %d)",
1326 rx_schedule (dev
, 0);
1330 PRINTD (DBG_SKB
|DBG_WARN
, "failed to get skb");
1334 PRINTK (KERN_INFO
, "frame received on TX-only VC %x", rx_channel
);
1335 // do we count this?
1339 PRINTK (KERN_WARNING
, "dropped over-size frame");
1340 // do we count this?
1344 PRINTD (DBG_WARN
|DBG_VCC
|DBG_RX
, "no VCC for this frame (VC closed)");
1345 // do we count this?
1349 // Wait update complete ? SPONG
1355 FLUSH_RX_CHANNEL (dev
,rx_channel
);
1356 clear_bit (rx_busy
, &dev
->flags
);
1361 /********** interrupt handler **********/
1363 static irqreturn_t
interrupt_handler(int irq
, void *dev_id
)
1365 hrz_dev
*dev
= dev_id
;
1367 unsigned int irq_ok
;
1369 PRINTD (DBG_FLOW
, "interrupt_handler: %p", dev_id
);
1371 // definitely for us
1373 while ((int_source
= rd_regl (dev
, INT_SOURCE_REG_OFF
)
1374 & INTERESTING_INTERRUPTS
)) {
1375 // In the interests of fairness, the handlers below are
1376 // called in sequence and without immediate return to the head of
1377 // the while loop. This is only of issue for slow hosts (or when
1378 // debugging messages are on). Really slow hosts may find a fast
1379 // sender keeps them permanently in the IRQ handler. :(
1381 // (only an issue for slow hosts) RX completion goes before
1382 // rx_data_av as the former implies rx_busy and so the latter
1383 // would just abort. If it reschedules another transfer
1384 // (continuing the same frame) then it will not clear rx_busy.
1386 // (only an issue for slow hosts) TX completion goes before RX
1387 // data available as it is a much shorter routine - there is the
1388 // chance that any further transfers it schedules will be complete
1389 // by the time of the return to the head of the while loop
1391 if (int_source
& RX_BUS_MASTER_COMPLETE
) {
1393 PRINTD (DBG_IRQ
|DBG_BUS
|DBG_RX
, "rx_bus_master_complete asserted");
1394 rx_bus_master_complete_handler (dev
);
1396 if (int_source
& TX_BUS_MASTER_COMPLETE
) {
1398 PRINTD (DBG_IRQ
|DBG_BUS
|DBG_TX
, "tx_bus_master_complete asserted");
1399 tx_bus_master_complete_handler (dev
);
1401 if (int_source
& RX_DATA_AV
) {
1403 PRINTD (DBG_IRQ
|DBG_RX
, "rx_data_av asserted");
1404 rx_data_av_handler (dev
);
1408 PRINTD (DBG_IRQ
, "work done: %u", irq_ok
);
1410 PRINTD (DBG_IRQ
|DBG_WARN
, "spurious interrupt source: %#x", int_source
);
1413 PRINTD (DBG_IRQ
|DBG_FLOW
, "interrupt_handler done: %p", dev_id
);
1419 /********** housekeeping **********/
1421 static void do_housekeeping (unsigned long arg
) {
1422 // just stats at the moment
1423 hrz_dev
* dev
= (hrz_dev
*) arg
;
1425 // collect device-specific (not driver/atm-linux) stats here
1426 dev
->tx_cell_count
+= rd_regw (dev
, TX_CELL_COUNT_OFF
);
1427 dev
->rx_cell_count
+= rd_regw (dev
, RX_CELL_COUNT_OFF
);
1428 dev
->hec_error_count
+= rd_regw (dev
, HEC_ERROR_COUNT_OFF
);
1429 dev
->unassigned_cell_count
+= rd_regw (dev
, UNASSIGNED_CELL_COUNT_OFF
);
1431 mod_timer (&dev
->housekeeping
, jiffies
+ HZ
/10);
1436 /********** find an idle channel for TX and set it up **********/
1438 // called with tx_busy set
1439 static short setup_idle_tx_channel (hrz_dev
* dev
, hrz_vcc
* vcc
) {
1440 unsigned short idle_channels
;
1441 short tx_channel
= -1;
1442 unsigned int spin_count
;
1443 PRINTD (DBG_FLOW
|DBG_TX
, "setup_idle_tx_channel %p", dev
);
1445 // better would be to fail immediately, the caller can then decide whether
1446 // to wait or drop (depending on whether this is UBR etc.)
1448 while (!(idle_channels
= rd_regw (dev
, TX_STATUS_OFF
) & IDLE_CHANNELS_MASK
)) {
1449 PRINTD (DBG_TX
|DBG_WARN
, "waiting for idle TX channel");
1451 if (++spin_count
> 100) {
1452 PRINTD (DBG_TX
|DBG_ERR
, "spun out waiting for idle TX channel");
1457 // got an idle channel
1459 // tx_idle ensures we look for idle channels in RR order
1460 int chan
= dev
->tx_idle
;
1463 while (keep_going
) {
1464 if (idle_channels
& (1<<chan
)) {
1469 if (chan
== TX_CHANS
)
1473 dev
->tx_idle
= chan
;
1476 // set up the channel we found
1478 // Initialise the cell header in the transmit channel descriptor
1479 // a.k.a. prepare the channel and remember that we have done so.
1481 tx_ch_desc
* tx_desc
= &memmap
->tx_descs
[tx_channel
];
1484 u16 channel
= vcc
->channel
;
1486 unsigned long flags
;
1487 spin_lock_irqsave (&dev
->mem_lock
, flags
);
1489 // Update the transmit channel record.
1490 dev
->tx_channel_record
[tx_channel
] = channel
;
1493 update_tx_channel_config (dev
, tx_channel
, RATE_TYPE_ACCESS
,
1496 // Update the PCR counter preload value etc.
1497 update_tx_channel_config (dev
, tx_channel
, PCR_TIMER_ACCESS
,
1501 if (vcc
->tx_xbr_bits
== VBR_RATE_TYPE
) {
1503 update_tx_channel_config (dev
, tx_channel
, SCR_TIMER_ACCESS
,
1507 update_tx_channel_config (dev
, tx_channel
, BUCKET_CAPACITY_ACCESS
,
1508 vcc
->tx_bucket_bits
);
1511 update_tx_channel_config (dev
, tx_channel
, BUCKET_FULLNESS_ACCESS
,
1512 vcc
->tx_bucket_bits
);
1516 // Initialise the read and write buffer pointers
1517 rd_ptr
= rd_mem (dev
, &tx_desc
->rd_buf_type
) & BUFFER_PTR_MASK
;
1518 wr_ptr
= rd_mem (dev
, &tx_desc
->wr_buf_type
) & BUFFER_PTR_MASK
;
1520 // idle TX channels should have identical pointers
1521 if (rd_ptr
!= wr_ptr
) {
1522 PRINTD (DBG_TX
|DBG_ERR
, "TX buffer pointers are broken!");
1523 // spin_unlock... return -E...
1524 // I wonder if gcc would get rid of one of the pointer aliases
1526 PRINTD (DBG_TX
, "TX buffer pointers are: rd %x, wr %x.",
1531 PRINTD (DBG_QOS
|DBG_TX
, "tx_channel: aal0");
1532 rd_ptr
|= CHANNEL_TYPE_RAW_CELLS
;
1533 wr_ptr
|= CHANNEL_TYPE_RAW_CELLS
;
1536 PRINTD (DBG_QOS
|DBG_TX
, "tx_channel: aal34");
1537 rd_ptr
|= CHANNEL_TYPE_AAL3_4
;
1538 wr_ptr
|= CHANNEL_TYPE_AAL3_4
;
1541 rd_ptr
|= CHANNEL_TYPE_AAL5
;
1542 wr_ptr
|= CHANNEL_TYPE_AAL5
;
1543 // Initialise the CRC
1544 wr_mem (dev
, &tx_desc
->partial_crc
, INITIAL_CRC
);
1548 wr_mem (dev
, &tx_desc
->rd_buf_type
, rd_ptr
);
1549 wr_mem (dev
, &tx_desc
->wr_buf_type
, wr_ptr
);
1551 // Write the Cell Header
1552 // Payload Type, CLP and GFC would go here if non-zero
1553 wr_mem (dev
, &tx_desc
->cell_header
, channel
);
1555 spin_unlock_irqrestore (&dev
->mem_lock
, flags
);
1561 /********** send a frame **********/
1563 static int hrz_send (struct atm_vcc
* atm_vcc
, struct sk_buff
* skb
) {
1564 unsigned int spin_count
;
1566 hrz_dev
* dev
= HRZ_DEV(atm_vcc
->dev
);
1567 hrz_vcc
* vcc
= HRZ_VCC(atm_vcc
);
1568 u16 channel
= vcc
->channel
;
1570 u32 buffers_required
;
1572 /* signed for error return */
1575 PRINTD (DBG_FLOW
|DBG_TX
, "hrz_send vc %x data %p len %u",
1576 channel
, skb
->data
, skb
->len
);
1578 dump_skb (">>>", channel
, skb
);
1580 if (atm_vcc
->qos
.txtp
.traffic_class
== ATM_NONE
) {
1581 PRINTK (KERN_ERR
, "attempt to send on RX-only VC %x", channel
);
1582 hrz_kfree_skb (skb
);
1586 // don't understand this
1587 ATM_SKB(skb
)->vcc
= atm_vcc
;
1589 if (skb
->len
> atm_vcc
->qos
.txtp
.max_sdu
) {
1590 PRINTK (KERN_ERR
, "sk_buff length greater than agreed max_sdu, dropping...");
1591 hrz_kfree_skb (skb
);
1596 PRINTD (DBG_ERR
|DBG_TX
, "attempt to transmit on zero (rx_)channel");
1597 hrz_kfree_skb (skb
);
1603 // where would be a better place for this? housekeeping?
1605 pci_read_config_word (dev
->pci_dev
, PCI_STATUS
, &status
);
1606 if (status
& PCI_STATUS_REC_MASTER_ABORT
) {
1607 PRINTD (DBG_BUS
|DBG_ERR
, "Clearing PCI Master Abort (and cleaning up)");
1608 status
&= ~PCI_STATUS_REC_MASTER_ABORT
;
1609 pci_write_config_word (dev
->pci_dev
, PCI_STATUS
, status
);
1610 if (test_bit (tx_busy
, &dev
->flags
)) {
1611 hrz_kfree_skb (dev
->tx_skb
);
1618 #ifdef DEBUG_HORIZON
1620 if (channel
== 1023) {
1622 unsigned short d
= 0;
1623 char * s
= skb
->data
;
1625 for (i
= 0; i
< 4; ++i
)
1626 d
= (d
<< 4) | hex_to_bin(*s
++);
1627 PRINTK (KERN_INFO
, "debug bitmap is now %hx", debug
= d
);
1632 // wait until TX is free and grab lock
1633 if (tx_hold (dev
)) {
1634 hrz_kfree_skb (skb
);
1635 return -ERESTARTSYS
;
1638 // Wait for enough space to be available in transmit buffer memory.
1640 // should be number of cells needed + 2 (according to hardware docs)
1641 // = ((framelen+8)+47) / 48 + 2
1642 // = (framelen+7) / 48 + 3, hmm... faster to put addition inside XXX
1643 buffers_required
= (skb
->len
+(ATM_AAL5_TRAILER
-1)) / ATM_CELL_PAYLOAD
+ 3;
1645 // replace with timer and sleep, add dev->tx_buffers_queue (max 1 entry)
1647 while ((free_buffers
= rd_regw (dev
, TX_FREE_BUFFER_COUNT_OFF
)) < buffers_required
) {
1648 PRINTD (DBG_TX
, "waiting for free TX buffers, got %d of %d",
1649 free_buffers
, buffers_required
);
1650 // what is the appropriate delay? implement a timeout? (depending on line speed?)
1652 // what happens if we kill (current_pid, SIGKILL) ?
1654 if (++spin_count
> 1000) {
1655 PRINTD (DBG_TX
|DBG_ERR
, "spun out waiting for tx buffers, got %d of %d",
1656 free_buffers
, buffers_required
);
1658 hrz_kfree_skb (skb
);
1659 return -ERESTARTSYS
;
1663 // Select a channel to transmit the frame on.
1664 if (channel
== dev
->last_vc
) {
1665 PRINTD (DBG_TX
, "last vc hack: hit");
1666 tx_channel
= dev
->tx_last
;
1668 PRINTD (DBG_TX
, "last vc hack: miss");
1669 // Are we currently transmitting this VC on one of the channels?
1670 for (tx_channel
= 0; tx_channel
< TX_CHANS
; ++tx_channel
)
1671 if (dev
->tx_channel_record
[tx_channel
] == channel
) {
1672 PRINTD (DBG_TX
, "vc already on channel: hit");
1675 if (tx_channel
== TX_CHANS
) {
1676 PRINTD (DBG_TX
, "vc already on channel: miss");
1677 // Find and set up an idle channel.
1678 tx_channel
= setup_idle_tx_channel (dev
, vcc
);
1679 if (tx_channel
< 0) {
1680 PRINTD (DBG_TX
|DBG_ERR
, "failed to get channel");
1686 PRINTD (DBG_TX
, "got channel");
1687 SELECT_TX_CHANNEL(dev
, tx_channel
);
1689 dev
->last_vc
= channel
;
1690 dev
->tx_last
= tx_channel
;
1693 PRINTD (DBG_TX
, "using channel %u", tx_channel
);
1695 YELLOW_LED_OFF(dev
);
1697 // TX start transfer
1700 unsigned int tx_len
= skb
->len
;
1701 unsigned int tx_iovcnt
= skb_shinfo(skb
)->nr_frags
;
1702 // remember this so we can free it later
1706 // scatter gather transfer
1707 dev
->tx_regions
= tx_iovcnt
;
1708 dev
->tx_iovec
= NULL
; /* @@@ needs rewritten */
1710 PRINTD (DBG_TX
|DBG_BUS
, "TX start scatter-gather transfer (iovec %p, len %d)",
1713 hrz_kfree_skb (skb
);
1717 dev
->tx_regions
= 0;
1718 dev
->tx_iovec
= NULL
;
1719 dev
->tx_bytes
= tx_len
;
1720 dev
->tx_addr
= skb
->data
;
1721 PRINTD (DBG_TX
|DBG_BUS
, "TX start simple transfer (addr %p, len %d)",
1725 // and do the business
1726 tx_schedule (dev
, 0);
1733 /********** reset a card **********/
1735 static void hrz_reset (const hrz_dev
* dev
) {
1736 u32 control_0_reg
= rd_regl (dev
, CONTROL_0_REG
);
1738 // why not set RESET_HORIZON to one and wait for the card to
1739 // reassert that bit as zero? Like so:
1740 control_0_reg
= control_0_reg
& RESET_HORIZON
;
1741 wr_regl (dev
, CONTROL_0_REG
, control_0_reg
);
1742 while (control_0_reg
& RESET_HORIZON
)
1743 control_0_reg
= rd_regl (dev
, CONTROL_0_REG
);
1745 // old reset code retained:
1746 wr_regl (dev
, CONTROL_0_REG
, control_0_reg
|
1747 RESET_ATM
| RESET_RX
| RESET_TX
| RESET_HOST
);
1748 // just guessing here
1751 wr_regl (dev
, CONTROL_0_REG
, control_0_reg
);
1754 /********** read the burnt in address **********/
1756 static void WRITE_IT_WAIT (const hrz_dev
*dev
, u32 ctrl
)
1758 wr_regl (dev
, CONTROL_0_REG
, ctrl
);
1762 static void CLOCK_IT (const hrz_dev
*dev
, u32 ctrl
)
1764 // DI must be valid around rising SK edge
1765 WRITE_IT_WAIT(dev
, ctrl
& ~SEEPROM_SK
);
1766 WRITE_IT_WAIT(dev
, ctrl
| SEEPROM_SK
);
1769 static u16
read_bia(const hrz_dev
*dev
, u16 addr
)
1771 u32 ctrl
= rd_regl (dev
, CONTROL_0_REG
);
1773 const unsigned int addr_bits
= 6;
1774 const unsigned int data_bits
= 16;
1780 ctrl
&= ~(SEEPROM_CS
| SEEPROM_SK
| SEEPROM_DI
);
1781 WRITE_IT_WAIT(dev
, ctrl
);
1783 // wake Serial EEPROM and send 110 (READ) command
1784 ctrl
|= (SEEPROM_CS
| SEEPROM_DI
);
1785 CLOCK_IT(dev
, ctrl
);
1788 CLOCK_IT(dev
, ctrl
);
1790 ctrl
&= ~SEEPROM_DI
;
1791 CLOCK_IT(dev
, ctrl
);
1793 for (i
=0; i
<addr_bits
; i
++) {
1794 if (addr
& (1 << (addr_bits
-1)))
1797 ctrl
&= ~SEEPROM_DI
;
1799 CLOCK_IT(dev
, ctrl
);
1804 // we could check that we have DO = 0 here
1805 ctrl
&= ~SEEPROM_DI
;
1808 for (i
=0;i
<data_bits
;i
++) {
1811 CLOCK_IT(dev
, ctrl
);
1813 if (rd_regl (dev
, CONTROL_0_REG
) & SEEPROM_DO
)
1814 res
|= (1 << (data_bits
-1));
1817 ctrl
&= ~(SEEPROM_SK
| SEEPROM_CS
);
1818 WRITE_IT_WAIT(dev
, ctrl
);
1823 /********** initialise a card **********/
1825 static int hrz_init(hrz_dev
*dev
)
1840 ctrl
= rd_regl (dev
, CONTROL_0_REG
);
1841 PRINTD (DBG_INFO
, "ctrl0reg is %#x", ctrl
);
1842 onefivefive
= ctrl
& ATM_LAYER_STATUS
;
1845 printk (DEV_LABEL
": Horizon Ultra (at 155.52 MBps)");
1847 printk (DEV_LABEL
": Horizon (at 25 MBps)");
1850 // Reset the card to get everything in a known state
1855 // Clear all the buffer memory
1857 printk (" clearing memory");
1859 for (mem
= (HDW
*) memmap
; mem
< (HDW
*) (memmap
+ 1); ++mem
)
1860 wr_mem (dev
, mem
, 0);
1862 printk (" tx channels");
1864 // All transmit eight channels are set up as AAL5 ABR channels with
1865 // a 16us cell spacing. Why?
1867 // Channel 0 gets the free buffer at 100h, channel 1 gets the free
1868 // buffer at 110h etc.
1870 for (chan
= 0; chan
< TX_CHANS
; ++chan
) {
1871 tx_ch_desc
* tx_desc
= &memmap
->tx_descs
[chan
];
1872 cell_buf
* buf
= &memmap
->inittxbufs
[chan
];
1874 // initialise the read and write buffer pointers
1875 wr_mem (dev
, &tx_desc
->rd_buf_type
, BUF_PTR(buf
));
1876 wr_mem (dev
, &tx_desc
->wr_buf_type
, BUF_PTR(buf
));
1878 // set the status of the initial buffers to empty
1879 wr_mem (dev
, &buf
->next
, BUFF_STATUS_EMPTY
);
1882 // Use space bufn3 at the moment for tx buffers
1884 printk (" tx buffers");
1886 tx_desc
= memmap
->bufn3
;
1888 wr_mem (dev
, &memmap
->txfreebufstart
.next
, BUF_PTR(tx_desc
) | BUFF_STATUS_EMPTY
);
1890 for (buff_count
= 0; buff_count
< BUFN3_SIZE
-1; buff_count
++) {
1891 wr_mem (dev
, &tx_desc
->next
, BUF_PTR(tx_desc
+1) | BUFF_STATUS_EMPTY
);
1895 wr_mem (dev
, &tx_desc
->next
, BUF_PTR(&memmap
->txfreebufend
) | BUFF_STATUS_EMPTY
);
1897 // Initialise the transmit free buffer count
1898 wr_regw (dev
, TX_FREE_BUFFER_COUNT_OFF
, BUFN3_SIZE
);
1900 printk (" rx channels");
1902 // Initialise all of the receive channels to be AAL5 disabled with
1903 // an interrupt threshold of 0
1905 for (chan
= 0; chan
< RX_CHANS
; ++chan
) {
1906 rx_ch_desc
* rx_desc
= &memmap
->rx_descs
[chan
];
1908 wr_mem (dev
, &rx_desc
->wr_buf_type
, CHANNEL_TYPE_AAL5
| RX_CHANNEL_DISABLED
);
1911 printk (" rx buffers");
1913 // Use space bufn4 at the moment for rx buffers
1915 rx_desc
= memmap
->bufn4
;
1917 wr_mem (dev
, &memmap
->rxfreebufstart
.next
, BUF_PTR(rx_desc
) | BUFF_STATUS_EMPTY
);
1919 for (buff_count
= 0; buff_count
< BUFN4_SIZE
-1; buff_count
++) {
1920 wr_mem (dev
, &rx_desc
->next
, BUF_PTR(rx_desc
+1) | BUFF_STATUS_EMPTY
);
1925 wr_mem (dev
, &rx_desc
->next
, BUF_PTR(&memmap
->rxfreebufend
) | BUFF_STATUS_EMPTY
);
1927 // Initialise the receive free buffer count
1928 wr_regw (dev
, RX_FREE_BUFFER_COUNT_OFF
, BUFN4_SIZE
);
1930 // Initialize Horizons registers
1933 wr_regw (dev
, TX_CONFIG_OFF
,
1934 ABR_ROUND_ROBIN
| TX_NORMAL_OPERATION
| DRVR_DRVRBAR_ENABLE
);
1936 // RX config. Use 10-x VC bits, x VP bits, non user cells in channel 0.
1937 wr_regw (dev
, RX_CONFIG_OFF
,
1938 DISCARD_UNUSED_VPI_VCI_BITS_SET
| NON_USER_CELLS_IN_ONE_CHANNEL
| vpi_bits
);
1941 wr_regw (dev
, RX_LINE_CONFIG_OFF
,
1942 LOCK_DETECT_ENABLE
| FREQUENCY_DETECT_ENABLE
| GXTALOUT_SELECT_DIV4
);
1944 // Set the max AAL5 cell count to be just enough to contain the
1945 // largest AAL5 frame that the user wants to receive
1946 wr_regw (dev
, MAX_AAL5_CELL_COUNT_OFF
,
1947 DIV_ROUND_UP(max_rx_size
+ ATM_AAL5_TRAILER
, ATM_CELL_PAYLOAD
));
1950 wr_regw (dev
, RX_CONFIG_OFF
, rd_regw (dev
, RX_CONFIG_OFF
) | RX_ENABLE
);
1952 printk (" control");
1954 // Drive the OE of the LEDs then turn the green LED on
1955 ctrl
|= GREEN_LED_OE
| YELLOW_LED_OE
| GREEN_LED
| YELLOW_LED
;
1956 wr_regl (dev
, CONTROL_0_REG
, ctrl
);
1958 // Test for a 155-capable card
1961 // Select 155 mode... make this a choice (or: how do we detect
1962 // external line speed and switch?)
1963 ctrl
|= ATM_LAYER_SELECT
;
1964 wr_regl (dev
, CONTROL_0_REG
, ctrl
);
1966 // test SUNI-lite vs SAMBA
1968 // Register 0x00 in the SUNI will have some of bits 3-7 set, and
1969 // they will always be zero for the SAMBA. Ha! Bloody hardware
1970 // engineers. It'll never work.
1972 if (rd_framer (dev
, 0) & 0x00f0) {
1976 // Reset, just in case
1977 wr_framer (dev
, 0x00, 0x0080);
1978 wr_framer (dev
, 0x00, 0x0000);
1980 // Configure transmit FIFO
1981 wr_framer (dev
, 0x63, rd_framer (dev
, 0x63) | 0x0002);
1983 // Set line timed mode
1984 wr_framer (dev
, 0x05, rd_framer (dev
, 0x05) | 0x0001);
1989 // Reset, just in case
1990 wr_framer (dev
, 0, rd_framer (dev
, 0) | 0x0001);
1991 wr_framer (dev
, 0, rd_framer (dev
, 0) &~ 0x0001);
1993 // Turn off diagnostic loopback and enable line-timed mode
1994 wr_framer (dev
, 0, 0x0002);
1996 // Turn on transmit outputs
1997 wr_framer (dev
, 2, 0x0B80);
2001 ctrl
&= ~ATM_LAYER_SELECT
;
2017 u8
* esi
= dev
->atm_dev
->esi
;
2019 // in the card I have, EEPROM
2020 // addresses 0, 1, 2 contain 0
2021 // addresess 5, 6 etc. contain ffff
2022 // NB: Madge prefix is 00 00 f6 (which is 00 00 6f in Ethernet bit order)
2023 // the read_bia routine gets the BIA in Ethernet bit order
2025 for (i
=0; i
< ESI_LEN
; ++i
) {
2027 b
= read_bia (dev
, i
/2 + 2);
2031 printk ("%02x", esi
[i
]);
2035 // Enable RX_Q and ?X_COMPLETE interrupts only
2036 wr_regl (dev
, INT_ENABLE_REG_OFF
, INTERESTING_INTERRUPTS
);
2044 /********** check max_sdu **********/
2046 static int check_max_sdu (hrz_aal aal
, struct atm_trafprm
* tp
, unsigned int max_frame_size
) {
2047 PRINTD (DBG_FLOW
|DBG_QOS
, "check_max_sdu");
2051 if (!(tp
->max_sdu
)) {
2052 PRINTD (DBG_QOS
, "defaulting max_sdu");
2053 tp
->max_sdu
= ATM_AAL0_SDU
;
2054 } else if (tp
->max_sdu
!= ATM_AAL0_SDU
) {
2055 PRINTD (DBG_QOS
|DBG_ERR
, "rejecting max_sdu");
2060 if (tp
->max_sdu
== 0 || tp
->max_sdu
> ATM_MAX_AAL34_PDU
) {
2061 PRINTD (DBG_QOS
, "%sing max_sdu", tp
->max_sdu
? "capp" : "default");
2062 tp
->max_sdu
= ATM_MAX_AAL34_PDU
;
2066 if (tp
->max_sdu
== 0 || tp
->max_sdu
> max_frame_size
) {
2067 PRINTD (DBG_QOS
, "%sing max_sdu", tp
->max_sdu
? "capp" : "default");
2068 tp
->max_sdu
= max_frame_size
;
2075 /********** check pcr **********/
2077 // something like this should be part of ATM Linux
2078 static int atm_pcr_check (struct atm_trafprm
* tp
, unsigned int pcr
) {
2079 // we are assuming non-UBR, and non-special values of pcr
2080 if (tp
->min_pcr
== ATM_MAX_PCR
)
2081 PRINTD (DBG_QOS
, "luser gave min_pcr = ATM_MAX_PCR");
2082 else if (tp
->min_pcr
< 0)
2083 PRINTD (DBG_QOS
, "luser gave negative min_pcr");
2084 else if (tp
->min_pcr
&& tp
->min_pcr
> pcr
)
2085 PRINTD (DBG_QOS
, "pcr less than min_pcr");
2087 // !! max_pcr = UNSPEC (0) is equivalent to max_pcr = MAX (-1)
2088 // easier to #define ATM_MAX_PCR 0 and have all rates unsigned?
2089 // [this would get rid of next two conditionals]
2090 if ((0) && tp
->max_pcr
== ATM_MAX_PCR
)
2091 PRINTD (DBG_QOS
, "luser gave max_pcr = ATM_MAX_PCR");
2092 else if ((tp
->max_pcr
!= ATM_MAX_PCR
) && tp
->max_pcr
< 0)
2093 PRINTD (DBG_QOS
, "luser gave negative max_pcr");
2094 else if (tp
->max_pcr
&& tp
->max_pcr
!= ATM_MAX_PCR
&& tp
->max_pcr
< pcr
)
2095 PRINTD (DBG_QOS
, "pcr greater than max_pcr");
2097 // each limit unspecified or not violated
2098 PRINTD (DBG_QOS
, "xBR(pcr) OK");
2101 PRINTD (DBG_QOS
, "pcr=%u, tp: min_pcr=%d, pcr=%d, max_pcr=%d",
2102 pcr
, tp
->min_pcr
, tp
->pcr
, tp
->max_pcr
);
2106 /********** open VC **********/
2108 static int hrz_open (struct atm_vcc
*atm_vcc
)
2113 struct atm_qos
* qos
;
2114 struct atm_trafprm
* txtp
;
2115 struct atm_trafprm
* rxtp
;
2117 hrz_dev
* dev
= HRZ_DEV(atm_vcc
->dev
);
2119 hrz_vcc
* vccp
; // allocated late
2120 short vpi
= atm_vcc
->vpi
;
2121 int vci
= atm_vcc
->vci
;
2122 PRINTD (DBG_FLOW
|DBG_VCC
, "hrz_open %x %x", vpi
, vci
);
2124 #ifdef ATM_VPI_UNSPEC
2125 // UNSPEC is deprecated, remove this code eventually
2126 if (vpi
== ATM_VPI_UNSPEC
|| vci
== ATM_VCI_UNSPEC
) {
2127 PRINTK (KERN_WARNING
, "rejecting open with unspecified VPI/VCI (deprecated)");
2132 error
= vpivci_to_channel (&channel
, vpi
, vci
);
2134 PRINTD (DBG_WARN
|DBG_VCC
, "VPI/VCI out of range: %hd/%d", vpi
, vci
);
2138 vcc
.channel
= channel
;
2139 // max speed for the moment
2142 qos
= &atm_vcc
->qos
;
2144 // check AAL and remember it
2147 // we would if it were 48 bytes and not 52!
2148 PRINTD (DBG_QOS
|DBG_VCC
, "AAL0");
2152 // we would if I knew how do the SAR!
2153 PRINTD (DBG_QOS
|DBG_VCC
, "AAL3/4");
2157 PRINTD (DBG_QOS
|DBG_VCC
, "AAL5");
2161 PRINTD (DBG_QOS
|DBG_VCC
, "Bad AAL!");
2165 // TX traffic parameters
2167 // there are two, interrelated problems here: 1. the reservation of
2168 // PCR is not a binary choice, we are given bounds and/or a
2169 // desirable value; 2. the device is only capable of certain values,
2170 // most of which are not integers. It is almost certainly acceptable
2171 // to be off by a maximum of 1 to 10 cps.
2173 // Pragmatic choice: always store an integral PCR as that which has
2174 // been allocated, even if we allocate a little (or a lot) less,
2175 // after rounding. The actual allocation depends on what we can
2176 // manage with our rate selection algorithm. The rate selection
2177 // algorithm is given an integral PCR and a tolerance and told
2178 // whether it should round the value up or down if the tolerance is
2179 // exceeded; it returns: a) the actual rate selected (rounded up to
2180 // the nearest integer), b) a bit pattern to feed to the timer
2181 // register, and c) a failure value if no applicable rate exists.
2183 // Part of the job is done by atm_pcr_goal which gives us a PCR
2184 // specification which says: EITHER grab the maximum available PCR
2185 // (and perhaps a lower bound which we musn't pass), OR grab this
2186 // amount, rounding down if you have to (and perhaps a lower bound
2187 // which we musn't pass) OR grab this amount, rounding up if you
2188 // have to (and perhaps an upper bound which we musn't pass). If any
2189 // bounds ARE passed we fail. Note that rounding is only rounding to
2190 // match device limitations, we do not round down to satisfy
2191 // bandwidth availability even if this would not violate any given
2194 // Note: telephony = 64kb/s = 48 byte cell payload @ 500/3 cells/s
2195 // (say) so this is not even a binary fixpoint cell rate (but this
2196 // device can do it). To avoid this sort of hassle we use a
2197 // tolerance parameter (currently fixed at 10 cps).
2199 PRINTD (DBG_QOS
, "TX:");
2203 // set up defaults for no traffic
2205 // who knows what would actually happen if you try and send on this?
2206 vcc
.tx_xbr_bits
= IDLE_RATE_TYPE
;
2207 vcc
.tx_pcr_bits
= CLOCK_DISABLE
;
2209 vcc
.tx_scr_bits
= CLOCK_DISABLE
;
2210 vcc
.tx_bucket_bits
= 0;
2213 if (txtp
->traffic_class
!= ATM_NONE
) {
2214 error
= check_max_sdu (vcc
.aal
, txtp
, max_tx_size
);
2216 PRINTD (DBG_QOS
, "TX max_sdu check failed");
2220 switch (txtp
->traffic_class
) {
2222 // we take "the PCR" as a rate-cap
2225 make_rate (dev
, 1<<30, round_nearest
, &vcc
.tx_pcr_bits
, NULL
);
2226 vcc
.tx_xbr_bits
= ABR_RATE_TYPE
;
2231 // reserve min, allow up to max
2232 vcc
.tx_rate
= 0; // ?
2233 make_rate (dev
, 1<<30, round_nearest
, &vcc
.tx_pcr_bits
, 0);
2234 vcc
.tx_xbr_bits
= ABR_RATE_TYPE
;
2239 int pcr
= atm_pcr_goal (txtp
);
2242 // down vs. up, remaining bandwidth vs. unlimited bandwidth!!
2243 // should really have: once someone gets unlimited bandwidth
2244 // that no more non-UBR channels can be opened until the
2245 // unlimited one closes?? For the moment, round_down means
2246 // greedy people actually get something and not nothing
2248 // slight race (no locking) here so we may get -EAGAIN
2249 // later; the greedy bastards would deserve it :)
2250 PRINTD (DBG_QOS
, "snatching all remaining TX bandwidth");
2251 pcr
= dev
->tx_avail
;
2252 } else if (pcr
< 0) {
2258 error
= make_rate_with_tolerance (dev
, pcr
, r
, 10,
2259 &vcc
.tx_pcr_bits
, &vcc
.tx_rate
);
2261 PRINTD (DBG_QOS
, "could not make rate from TX PCR");
2264 // not really clear what further checking is needed
2265 error
= atm_pcr_check (txtp
, vcc
.tx_rate
);
2267 PRINTD (DBG_QOS
, "TX PCR failed consistency check");
2270 vcc
.tx_xbr_bits
= CBR_RATE_TYPE
;
2275 int pcr
= atm_pcr_goal (txtp
);
2276 // int scr = atm_scr_goal (txtp);
2277 int scr
= pcr
/2; // just for fun
2278 unsigned int mbs
= 60; // just for fun
2281 unsigned int bucket
;
2285 } else if (pcr
< 0) {
2291 error
= make_rate_with_tolerance (dev
, pcr
, pr
, 10,
2292 &vcc
.tx_pcr_bits
, 0);
2294 // see comments for PCR with CBR above
2296 // slight race (no locking) here so we may get -EAGAIN
2297 // later; the greedy bastards would deserve it :)
2298 PRINTD (DBG_QOS
, "snatching all remaining TX bandwidth");
2299 scr
= dev
->tx_avail
;
2300 } else if (scr
< 0) {
2306 error
= make_rate_with_tolerance (dev
, scr
, sr
, 10,
2307 &vcc
.tx_scr_bits
, &vcc
.tx_rate
);
2309 PRINTD (DBG_QOS
, "could not make rate from TX SCR");
2312 // not really clear what further checking is needed
2313 // error = atm_scr_check (txtp, vcc.tx_rate);
2315 PRINTD (DBG_QOS
, "TX SCR failed consistency check");
2318 // bucket calculations (from a piece of paper...) cell bucket
2319 // capacity must be largest integer smaller than m(p-s)/p + 1
2320 // where m = max burst size, p = pcr, s = scr
2321 bucket
= mbs
*(pcr
-scr
)/pcr
;
2322 if (bucket
*pcr
!= mbs
*(pcr
-scr
))
2324 if (bucket
> BUCKET_MAX_SIZE
) {
2325 PRINTD (DBG_QOS
, "shrinking bucket from %u to %u",
2326 bucket
, BUCKET_MAX_SIZE
);
2327 bucket
= BUCKET_MAX_SIZE
;
2329 vcc
.tx_xbr_bits
= VBR_RATE_TYPE
;
2330 vcc
.tx_bucket_bits
= bucket
;
2335 PRINTD (DBG_QOS
, "unsupported TX traffic class");
2341 // RX traffic parameters
2343 PRINTD (DBG_QOS
, "RX:");
2347 // set up defaults for no traffic
2350 if (rxtp
->traffic_class
!= ATM_NONE
) {
2351 error
= check_max_sdu (vcc
.aal
, rxtp
, max_rx_size
);
2353 PRINTD (DBG_QOS
, "RX max_sdu check failed");
2356 switch (rxtp
->traffic_class
) {
2364 vcc
.rx_rate
= 0; // ?
2369 int pcr
= atm_pcr_goal (rxtp
);
2371 // slight race (no locking) here so we may get -EAGAIN
2372 // later; the greedy bastards would deserve it :)
2373 PRINTD (DBG_QOS
, "snatching all remaining RX bandwidth");
2374 pcr
= dev
->rx_avail
;
2375 } else if (pcr
< 0) {
2379 // not really clear what further checking is needed
2380 error
= atm_pcr_check (rxtp
, vcc
.rx_rate
);
2382 PRINTD (DBG_QOS
, "RX PCR failed consistency check");
2389 // int scr = atm_scr_goal (rxtp);
2390 int scr
= 1<<16; // just for fun
2392 // slight race (no locking) here so we may get -EAGAIN
2393 // later; the greedy bastards would deserve it :)
2394 PRINTD (DBG_QOS
, "snatching all remaining RX bandwidth");
2395 scr
= dev
->rx_avail
;
2396 } else if (scr
< 0) {
2400 // not really clear what further checking is needed
2401 // error = atm_scr_check (rxtp, vcc.rx_rate);
2403 PRINTD (DBG_QOS
, "RX SCR failed consistency check");
2410 PRINTD (DBG_QOS
, "unsupported RX traffic class");
2417 // late abort useful for diagnostics
2418 if (vcc
.aal
!= aal5
) {
2419 PRINTD (DBG_QOS
, "AAL not supported");
2423 // get space for our vcc stuff and copy parameters into it
2424 vccp
= kmalloc (sizeof(hrz_vcc
), GFP_KERNEL
);
2426 PRINTK (KERN_ERR
, "out of memory!");
2431 // clear error and grab cell rate resource lock
2433 spin_lock (&dev
->rate_lock
);
2435 if (vcc
.tx_rate
> dev
->tx_avail
) {
2436 PRINTD (DBG_QOS
, "not enough TX PCR left");
2440 if (vcc
.rx_rate
> dev
->rx_avail
) {
2441 PRINTD (DBG_QOS
, "not enough RX PCR left");
2446 // really consume cell rates
2447 dev
->tx_avail
-= vcc
.tx_rate
;
2448 dev
->rx_avail
-= vcc
.rx_rate
;
2449 PRINTD (DBG_QOS
|DBG_VCC
, "reserving %u TX PCR and %u RX PCR",
2450 vcc
.tx_rate
, vcc
.rx_rate
);
2453 // release lock and exit on error
2454 spin_unlock (&dev
->rate_lock
);
2456 PRINTD (DBG_QOS
|DBG_VCC
, "insufficient cell rate resources");
2461 // this is "immediately before allocating the connection identifier
2462 // in hardware" - so long as the next call does not fail :)
2463 set_bit(ATM_VF_ADDR
,&atm_vcc
->flags
);
2465 // any errors here are very serious and should never occur
2467 if (rxtp
->traffic_class
!= ATM_NONE
) {
2468 if (dev
->rxer
[channel
]) {
2469 PRINTD (DBG_ERR
|DBG_VCC
, "VC already open for RX");
2473 error
= hrz_open_rx (dev
, channel
);
2478 // this link allows RX frames through
2479 dev
->rxer
[channel
] = atm_vcc
;
2482 // success, set elements of atm_vcc
2483 atm_vcc
->dev_data
= (void *) vccp
;
2485 // indicate readiness
2486 set_bit(ATM_VF_READY
,&atm_vcc
->flags
);
2491 /********** close VC **********/
2493 static void hrz_close (struct atm_vcc
* atm_vcc
) {
2494 hrz_dev
* dev
= HRZ_DEV(atm_vcc
->dev
);
2495 hrz_vcc
* vcc
= HRZ_VCC(atm_vcc
);
2496 u16 channel
= vcc
->channel
;
2497 PRINTD (DBG_VCC
|DBG_FLOW
, "hrz_close");
2499 // indicate unreadiness
2500 clear_bit(ATM_VF_READY
,&atm_vcc
->flags
);
2502 if (atm_vcc
->qos
.txtp
.traffic_class
!= ATM_NONE
) {
2505 // let any TX on this channel that has started complete
2506 // no restart, just keep trying
2507 while (tx_hold (dev
))
2509 // remove record of any tx_channel having been setup for this channel
2510 for (i
= 0; i
< TX_CHANS
; ++i
)
2511 if (dev
->tx_channel_record
[i
] == channel
) {
2512 dev
->tx_channel_record
[i
] = -1;
2515 if (dev
->last_vc
== channel
)
2520 if (atm_vcc
->qos
.rxtp
.traffic_class
!= ATM_NONE
) {
2521 // disable RXing - it tries quite hard
2522 hrz_close_rx (dev
, channel
);
2523 // forget the vcc - no more skbs will be pushed
2524 if (atm_vcc
!= dev
->rxer
[channel
])
2525 PRINTK (KERN_ERR
, "%s atm_vcc=%p rxer[channel]=%p",
2526 "arghhh! we're going to die!",
2527 atm_vcc
, dev
->rxer
[channel
]);
2528 dev
->rxer
[channel
] = NULL
;
2531 // atomically release our rate reservation
2532 spin_lock (&dev
->rate_lock
);
2533 PRINTD (DBG_QOS
|DBG_VCC
, "releasing %u TX PCR and %u RX PCR",
2534 vcc
->tx_rate
, vcc
->rx_rate
);
2535 dev
->tx_avail
+= vcc
->tx_rate
;
2536 dev
->rx_avail
+= vcc
->rx_rate
;
2537 spin_unlock (&dev
->rate_lock
);
2539 // free our structure
2541 // say the VPI/VCI is free again
2542 clear_bit(ATM_VF_ADDR
,&atm_vcc
->flags
);
2546 static int hrz_getsockopt (struct atm_vcc
* atm_vcc
, int level
, int optname
,
2547 void *optval
, int optlen
) {
2548 hrz_dev
* dev
= HRZ_DEV(atm_vcc
->dev
);
2549 PRINTD (DBG_FLOW
|DBG_VCC
, "hrz_getsockopt");
2558 return -ENOPROTOOPT
;
2565 static int hrz_setsockopt (struct atm_vcc
* atm_vcc
, int level
, int optname
,
2566 void *optval
, unsigned int optlen
) {
2567 hrz_dev
* dev
= HRZ_DEV(atm_vcc
->dev
);
2568 PRINTD (DBG_FLOW
|DBG_VCC
, "hrz_setsockopt");
2577 return -ENOPROTOOPT
;
2586 static int hrz_ioctl (struct atm_dev
* atm_dev
, unsigned int cmd
, void *arg
) {
2587 hrz_dev
* dev
= HRZ_DEV(atm_dev
);
2588 PRINTD (DBG_FLOW
, "hrz_ioctl");
2592 unsigned char hrz_phy_get (struct atm_dev
* atm_dev
, unsigned long addr
) {
2593 hrz_dev
* dev
= HRZ_DEV(atm_dev
);
2594 PRINTD (DBG_FLOW
, "hrz_phy_get");
2598 static void hrz_phy_put (struct atm_dev
* atm_dev
, unsigned char value
,
2599 unsigned long addr
) {
2600 hrz_dev
* dev
= HRZ_DEV(atm_dev
);
2601 PRINTD (DBG_FLOW
, "hrz_phy_put");
2604 static int hrz_change_qos (struct atm_vcc
* atm_vcc
, struct atm_qos
*qos
, int flgs
) {
2605 hrz_dev
* dev
= HRZ_DEV(vcc
->dev
);
2606 PRINTD (DBG_FLOW
, "hrz_change_qos");
2611 /********** proc file contents **********/
2613 static int hrz_proc_read (struct atm_dev
* atm_dev
, loff_t
* pos
, char * page
) {
2614 hrz_dev
* dev
= HRZ_DEV(atm_dev
);
2616 PRINTD (DBG_FLOW
, "hrz_proc_read");
2618 /* more diagnostics here? */
2622 unsigned int count
= sprintf (page
, "vbr buckets:");
2624 for (i
= 0; i
< TX_CHANS
; ++i
)
2625 count
+= sprintf (page
, " %u/%u",
2626 query_tx_channel_config (dev
, i
, BUCKET_FULLNESS_ACCESS
),
2627 query_tx_channel_config (dev
, i
, BUCKET_CAPACITY_ACCESS
));
2628 count
+= sprintf (page
+count
, ".\n");
2634 return sprintf (page
,
2635 "cells: TX %lu, RX %lu, HEC errors %lu, unassigned %lu.\n",
2636 dev
->tx_cell_count
, dev
->rx_cell_count
,
2637 dev
->hec_error_count
, dev
->unassigned_cell_count
);
2640 return sprintf (page
,
2641 "free cell buffers: TX %hu, RX %hu+%hu.\n",
2642 rd_regw (dev
, TX_FREE_BUFFER_COUNT_OFF
),
2643 rd_regw (dev
, RX_FREE_BUFFER_COUNT_OFF
),
2644 dev
->noof_spare_buffers
);
2647 return sprintf (page
,
2648 "cps remaining: TX %u, RX %u\n",
2649 dev
->tx_avail
, dev
->rx_avail
);
2654 static const struct atmdev_ops hrz_ops
= {
2658 .proc_read
= hrz_proc_read
,
2659 .owner
= THIS_MODULE
,
2662 static int hrz_probe(struct pci_dev
*pci_dev
,
2663 const struct pci_device_id
*pci_ent
)
2668 // adapter slot free, read resources from PCI configuration space
2669 u32 iobase
= pci_resource_start (pci_dev
, 0);
2670 u32
* membase
= bus_to_virt (pci_resource_start (pci_dev
, 1));
2674 PRINTD (DBG_FLOW
, "hrz_probe");
2676 if (pci_enable_device(pci_dev
))
2679 /* XXX DEV_LABEL is a guess */
2680 if (!request_region(iobase
, HRZ_IO_EXTENT
, DEV_LABEL
)) {
2685 dev
= kzalloc(sizeof(hrz_dev
), GFP_KERNEL
);
2687 // perhaps we should be nice: deregister all adapters and abort?
2688 PRINTD(DBG_ERR
, "out of memory");
2693 pci_set_drvdata(pci_dev
, dev
);
2695 // grab IRQ and install handler - move this someplace more sensible
2697 if (request_irq(irq
,
2699 IRQF_SHARED
, /* irqflags guess */
2700 DEV_LABEL
, /* name guess */
2702 PRINTD(DBG_WARN
, "request IRQ failed!");
2707 PRINTD(DBG_INFO
, "found Madge ATM adapter (hrz) at: IO %x, IRQ %u, MEM %p",
2708 iobase
, irq
, membase
);
2710 dev
->atm_dev
= atm_dev_register(DEV_LABEL
, &pci_dev
->dev
, &hrz_ops
, -1,
2712 if (!(dev
->atm_dev
)) {
2713 PRINTD(DBG_ERR
, "failed to register Madge ATM adapter");
2718 PRINTD(DBG_INFO
, "registered Madge ATM adapter (no. %d) (%p) at %p",
2719 dev
->atm_dev
->number
, dev
, dev
->atm_dev
);
2720 dev
->atm_dev
->dev_data
= (void *) dev
;
2721 dev
->pci_dev
= pci_dev
;
2723 // enable bus master accesses
2724 pci_set_master(pci_dev
);
2726 // frobnicate latency (upwards, usually)
2727 pci_read_config_byte(pci_dev
, PCI_LATENCY_TIMER
, &lat
);
2729 PRINTD(DBG_INFO
, "%s PCI latency timer from %hu to %hu",
2730 "changing", lat
, pci_lat
);
2731 pci_write_config_byte(pci_dev
, PCI_LATENCY_TIMER
, pci_lat
);
2732 } else if (lat
< MIN_PCI_LATENCY
) {
2733 PRINTK(KERN_INFO
, "%s PCI latency timer from %hu to %hu",
2734 "increasing", lat
, MIN_PCI_LATENCY
);
2735 pci_write_config_byte(pci_dev
, PCI_LATENCY_TIMER
, MIN_PCI_LATENCY
);
2738 dev
->iobase
= iobase
;
2740 dev
->membase
= membase
;
2742 dev
->rx_q_entry
= dev
->rx_q_reset
= &memmap
->rx_q_entries
[0];
2743 dev
->rx_q_wrap
= &memmap
->rx_q_entries
[RX_CHANS
-1];
2745 // these next three are performance hacks
2750 dev
->tx_regions
= 0;
2753 dev
->tx_iovec
= NULL
;
2755 dev
->tx_cell_count
= 0;
2756 dev
->rx_cell_count
= 0;
2757 dev
->hec_error_count
= 0;
2758 dev
->unassigned_cell_count
= 0;
2760 dev
->noof_spare_buffers
= 0;
2764 for (i
= 0; i
< TX_CHANS
; ++i
)
2765 dev
->tx_channel_record
[i
] = -1;
2770 // Allocate cell rates and remember ASIC version
2771 // Fibre: ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53
2772 // Copper: (WRONG) we want 6 into the above, close to 25Mb/s
2773 // Copper: (plagarise!) 25600000/8/270*260/53 - n/53
2775 if (hrz_init(dev
)) {
2776 // to be really pedantic, this should be ATM_OC3c_PCR
2777 dev
->tx_avail
= ATM_OC3_PCR
;
2778 dev
->rx_avail
= ATM_OC3_PCR
;
2779 set_bit(ultra
, &dev
->flags
); // NOT "|= ultra" !
2781 dev
->tx_avail
= ((25600000/8)*26)/(27*53);
2782 dev
->rx_avail
= ((25600000/8)*26)/(27*53);
2783 PRINTD(DBG_WARN
, "Buggy ASIC: no TX bus-mastering.");
2786 // rate changes spinlock
2787 spin_lock_init(&dev
->rate_lock
);
2789 // on-board memory access spinlock; we want atomic reads and
2790 // writes to adapter memory (handles IRQ and SMP)
2791 spin_lock_init(&dev
->mem_lock
);
2793 init_waitqueue_head(&dev
->tx_queue
);
2795 // vpi in 0..4, vci in 6..10
2796 dev
->atm_dev
->ci_range
.vpi_bits
= vpi_bits
;
2797 dev
->atm_dev
->ci_range
.vci_bits
= 10-vpi_bits
;
2799 setup_timer(&dev
->housekeeping
, do_housekeeping
, (unsigned long) dev
);
2800 mod_timer(&dev
->housekeeping
, jiffies
);
2810 release_region(iobase
, HRZ_IO_EXTENT
);
2812 pci_disable_device(pci_dev
);
2816 static void hrz_remove_one(struct pci_dev
*pci_dev
)
2820 dev
= pci_get_drvdata(pci_dev
);
2822 PRINTD(DBG_INFO
, "closing %p (atm_dev = %p)", dev
, dev
->atm_dev
);
2823 del_timer_sync(&dev
->housekeeping
);
2825 atm_dev_deregister(dev
->atm_dev
);
2826 free_irq(dev
->irq
, dev
);
2827 release_region(dev
->iobase
, HRZ_IO_EXTENT
);
2830 pci_disable_device(pci_dev
);
2833 static void __init
hrz_check_args (void) {
2834 #ifdef DEBUG_HORIZON
2835 PRINTK (KERN_NOTICE
, "debug bitmap is %hx", debug
&= DBG_MASK
);
2838 PRINTK (KERN_NOTICE
, "no debug support in this image");
2841 if (vpi_bits
> HRZ_MAX_VPI
)
2842 PRINTK (KERN_ERR
, "vpi_bits has been limited to %hu",
2843 vpi_bits
= HRZ_MAX_VPI
);
2845 if (max_tx_size
< 0 || max_tx_size
> TX_AAL5_LIMIT
)
2846 PRINTK (KERN_NOTICE
, "max_tx_size has been limited to %hu",
2847 max_tx_size
= TX_AAL5_LIMIT
);
2849 if (max_rx_size
< 0 || max_rx_size
> RX_AAL5_LIMIT
)
2850 PRINTK (KERN_NOTICE
, "max_rx_size has been limited to %hu",
2851 max_rx_size
= RX_AAL5_LIMIT
);
2856 MODULE_AUTHOR(maintainer_string
);
2857 MODULE_DESCRIPTION(description_string
);
2858 MODULE_LICENSE("GPL");
2859 module_param(debug
, ushort
, 0644);
2860 module_param(vpi_bits
, ushort
, 0);
2861 module_param(max_tx_size
, int, 0);
2862 module_param(max_rx_size
, int, 0);
2863 module_param(pci_lat
, byte
, 0);
2864 MODULE_PARM_DESC(debug
, "debug bitmap, see .h file");
2865 MODULE_PARM_DESC(vpi_bits
, "number of bits (0..4) to allocate to VPIs");
2866 MODULE_PARM_DESC(max_tx_size
, "maximum size of TX AAL5 frames");
2867 MODULE_PARM_DESC(max_rx_size
, "maximum size of RX AAL5 frames");
2868 MODULE_PARM_DESC(pci_lat
, "PCI latency in bus cycles");
2870 static const struct pci_device_id hrz_pci_tbl
[] = {
2871 { PCI_VENDOR_ID_MADGE
, PCI_DEVICE_ID_MADGE_HORIZON
, PCI_ANY_ID
, PCI_ANY_ID
,
2876 MODULE_DEVICE_TABLE(pci
, hrz_pci_tbl
);
2878 static struct pci_driver hrz_driver
= {
2881 .remove
= hrz_remove_one
,
2882 .id_table
= hrz_pci_tbl
,
2885 /********** module entry **********/
2887 static int __init
hrz_module_init (void) {
2888 BUILD_BUG_ON(sizeof(struct MEMMAP
) != 128*1024/4);
2896 return pci_register_driver(&hrz_driver
);
2899 /********** module exit **********/
2901 static void __exit
hrz_module_exit (void) {
2902 PRINTD (DBG_FLOW
, "cleanup_module");
2904 pci_unregister_driver(&hrz_driver
);
2907 module_init(hrz_module_init
);
2908 module_exit(hrz_module_exit
);