2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/regmap.h>
20 #include <linux/mfd/core.h>
21 #include <linux/mfd/mt6397/core.h>
22 #include <linux/mfd/mt6323/core.h>
23 #include <linux/mfd/mt6397/registers.h>
24 #include <linux/mfd/mt6323/registers.h>
26 #define MT6397_RTC_BASE 0xe000
27 #define MT6397_RTC_SIZE 0x3e
29 #define MT6323_CID_CODE 0x23
30 #define MT6391_CID_CODE 0x91
31 #define MT6397_CID_CODE 0x97
33 static const struct resource mt6397_rtc_resources
[] = {
35 .start
= MT6397_RTC_BASE
,
36 .end
= MT6397_RTC_BASE
+ MT6397_RTC_SIZE
,
37 .flags
= IORESOURCE_MEM
,
40 .start
= MT6397_IRQ_RTC
,
41 .end
= MT6397_IRQ_RTC
,
42 .flags
= IORESOURCE_IRQ
,
46 static const struct mfd_cell mt6323_devs
[] = {
48 .name
= "mt6323-regulator",
49 .of_compatible
= "mediatek,mt6323-regulator"
52 .of_compatible
= "mediatek,mt6323-led"
56 static const struct mfd_cell mt6397_devs
[] = {
59 .num_resources
= ARRAY_SIZE(mt6397_rtc_resources
),
60 .resources
= mt6397_rtc_resources
,
61 .of_compatible
= "mediatek,mt6397-rtc",
63 .name
= "mt6397-regulator",
64 .of_compatible
= "mediatek,mt6397-regulator",
66 .name
= "mt6397-codec",
67 .of_compatible
= "mediatek,mt6397-codec",
70 .of_compatible
= "mediatek,mt6397-clk",
72 .name
= "mt6397-pinctrl",
73 .of_compatible
= "mediatek,mt6397-pinctrl",
77 static void mt6397_irq_lock(struct irq_data
*data
)
79 struct mt6397_chip
*mt6397
= irq_data_get_irq_chip_data(data
);
81 mutex_lock(&mt6397
->irqlock
);
84 static void mt6397_irq_sync_unlock(struct irq_data
*data
)
86 struct mt6397_chip
*mt6397
= irq_data_get_irq_chip_data(data
);
88 regmap_write(mt6397
->regmap
, mt6397
->int_con
[0],
89 mt6397
->irq_masks_cur
[0]);
90 regmap_write(mt6397
->regmap
, mt6397
->int_con
[1],
91 mt6397
->irq_masks_cur
[1]);
93 mutex_unlock(&mt6397
->irqlock
);
96 static void mt6397_irq_disable(struct irq_data
*data
)
98 struct mt6397_chip
*mt6397
= irq_data_get_irq_chip_data(data
);
99 int shift
= data
->hwirq
& 0xf;
100 int reg
= data
->hwirq
>> 4;
102 mt6397
->irq_masks_cur
[reg
] &= ~BIT(shift
);
105 static void mt6397_irq_enable(struct irq_data
*data
)
107 struct mt6397_chip
*mt6397
= irq_data_get_irq_chip_data(data
);
108 int shift
= data
->hwirq
& 0xf;
109 int reg
= data
->hwirq
>> 4;
111 mt6397
->irq_masks_cur
[reg
] |= BIT(shift
);
114 #ifdef CONFIG_PM_SLEEP
115 static int mt6397_irq_set_wake(struct irq_data
*irq_data
, unsigned int on
)
117 struct mt6397_chip
*mt6397
= irq_data_get_irq_chip_data(irq_data
);
118 int shift
= irq_data
->hwirq
& 0xf;
119 int reg
= irq_data
->hwirq
>> 4;
122 mt6397
->wake_mask
[reg
] |= BIT(shift
);
124 mt6397
->wake_mask
[reg
] &= ~BIT(shift
);
129 #define mt6397_irq_set_wake NULL
132 static struct irq_chip mt6397_irq_chip
= {
133 .name
= "mt6397-irq",
134 .irq_bus_lock
= mt6397_irq_lock
,
135 .irq_bus_sync_unlock
= mt6397_irq_sync_unlock
,
136 .irq_enable
= mt6397_irq_enable
,
137 .irq_disable
= mt6397_irq_disable
,
138 .irq_set_wake
= mt6397_irq_set_wake
,
141 static void mt6397_irq_handle_reg(struct mt6397_chip
*mt6397
, int reg
,
147 ret
= regmap_read(mt6397
->regmap
, reg
, &status
);
149 dev_err(mt6397
->dev
, "Failed to read irq status: %d\n", ret
);
153 for (i
= 0; i
< 16; i
++) {
154 if (status
& BIT(i
)) {
155 irq
= irq_find_mapping(mt6397
->irq_domain
, irqbase
+ i
);
157 handle_nested_irq(irq
);
161 regmap_write(mt6397
->regmap
, reg
, status
);
164 static irqreturn_t
mt6397_irq_thread(int irq
, void *data
)
166 struct mt6397_chip
*mt6397
= data
;
168 mt6397_irq_handle_reg(mt6397
, mt6397
->int_status
[0], 0);
169 mt6397_irq_handle_reg(mt6397
, mt6397
->int_status
[1], 16);
174 static int mt6397_irq_domain_map(struct irq_domain
*d
, unsigned int irq
,
177 struct mt6397_chip
*mt6397
= d
->host_data
;
179 irq_set_chip_data(irq
, mt6397
);
180 irq_set_chip_and_handler(irq
, &mt6397_irq_chip
, handle_level_irq
);
181 irq_set_nested_thread(irq
, 1);
182 irq_set_noprobe(irq
);
187 static const struct irq_domain_ops mt6397_irq_domain_ops
= {
188 .map
= mt6397_irq_domain_map
,
191 static int mt6397_irq_init(struct mt6397_chip
*mt6397
)
195 mutex_init(&mt6397
->irqlock
);
197 /* Mask all interrupt sources */
198 regmap_write(mt6397
->regmap
, mt6397
->int_con
[0], 0x0);
199 regmap_write(mt6397
->regmap
, mt6397
->int_con
[1], 0x0);
201 mt6397
->irq_domain
= irq_domain_add_linear(mt6397
->dev
->of_node
,
202 MT6397_IRQ_NR
, &mt6397_irq_domain_ops
, mt6397
);
203 if (!mt6397
->irq_domain
) {
204 dev_err(mt6397
->dev
, "could not create irq domain\n");
208 ret
= devm_request_threaded_irq(mt6397
->dev
, mt6397
->irq
, NULL
,
209 mt6397_irq_thread
, IRQF_ONESHOT
, "mt6397-pmic", mt6397
);
211 dev_err(mt6397
->dev
, "failed to register irq=%d; err: %d\n",
219 #ifdef CONFIG_PM_SLEEP
220 static int mt6397_irq_suspend(struct device
*dev
)
222 struct mt6397_chip
*chip
= dev_get_drvdata(dev
);
224 regmap_write(chip
->regmap
, chip
->int_con
[0], chip
->wake_mask
[0]);
225 regmap_write(chip
->regmap
, chip
->int_con
[1], chip
->wake_mask
[1]);
227 enable_irq_wake(chip
->irq
);
232 static int mt6397_irq_resume(struct device
*dev
)
234 struct mt6397_chip
*chip
= dev_get_drvdata(dev
);
236 regmap_write(chip
->regmap
, chip
->int_con
[0], chip
->irq_masks_cur
[0]);
237 regmap_write(chip
->regmap
, chip
->int_con
[1], chip
->irq_masks_cur
[1]);
239 disable_irq_wake(chip
->irq
);
245 static SIMPLE_DEV_PM_OPS(mt6397_pm_ops
, mt6397_irq_suspend
,
248 static int mt6397_probe(struct platform_device
*pdev
)
252 struct mt6397_chip
*pmic
;
254 pmic
= devm_kzalloc(&pdev
->dev
, sizeof(*pmic
), GFP_KERNEL
);
258 pmic
->dev
= &pdev
->dev
;
261 * mt6397 MFD is child device of soc pmic wrapper.
262 * Regmap is set from its parent.
264 pmic
->regmap
= dev_get_regmap(pdev
->dev
.parent
, NULL
);
268 platform_set_drvdata(pdev
, pmic
);
270 ret
= regmap_read(pmic
->regmap
, MT6397_CID
, &id
);
272 dev_err(pmic
->dev
, "Failed to read chip id: %d\n", ret
);
276 pmic
->irq
= platform_get_irq(pdev
, 0);
281 case MT6323_CID_CODE
:
282 pmic
->int_con
[0] = MT6323_INT_CON0
;
283 pmic
->int_con
[1] = MT6323_INT_CON1
;
284 pmic
->int_status
[0] = MT6323_INT_STATUS0
;
285 pmic
->int_status
[1] = MT6323_INT_STATUS1
;
286 ret
= mt6397_irq_init(pmic
);
290 ret
= devm_mfd_add_devices(&pdev
->dev
, -1, mt6323_devs
,
291 ARRAY_SIZE(mt6323_devs
), NULL
,
295 case MT6397_CID_CODE
:
296 case MT6391_CID_CODE
:
297 pmic
->int_con
[0] = MT6397_INT_CON0
;
298 pmic
->int_con
[1] = MT6397_INT_CON1
;
299 pmic
->int_status
[0] = MT6397_INT_STATUS0
;
300 pmic
->int_status
[1] = MT6397_INT_STATUS1
;
301 ret
= mt6397_irq_init(pmic
);
305 ret
= devm_mfd_add_devices(&pdev
->dev
, -1, mt6397_devs
,
306 ARRAY_SIZE(mt6397_devs
), NULL
,
311 dev_err(&pdev
->dev
, "unsupported chip: %d\n", id
);
316 irq_domain_remove(pmic
->irq_domain
);
317 dev_err(&pdev
->dev
, "failed to add child devices: %d\n", ret
);
323 static const struct of_device_id mt6397_of_match
[] = {
324 { .compatible
= "mediatek,mt6397" },
325 { .compatible
= "mediatek,mt6323" },
328 MODULE_DEVICE_TABLE(of
, mt6397_of_match
);
330 static const struct platform_device_id mt6397_id
[] = {
334 MODULE_DEVICE_TABLE(platform
, mt6397_id
);
336 static struct platform_driver mt6397_driver
= {
337 .probe
= mt6397_probe
,
340 .of_match_table
= of_match_ptr(mt6397_of_match
),
341 .pm
= &mt6397_pm_ops
,
343 .id_table
= mt6397_id
,
346 module_platform_driver(mt6397_driver
);
348 MODULE_AUTHOR("Flora Fu, MediaTek");
349 MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
350 MODULE_LICENSE("GPL");