atomic64: no need for CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
[linux-stable.git] / drivers / mfd / rts5209.c
blobb95beecf767fffffbb06ca18c82dbd3f5aa18673
1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/mfd/rtsx_pci.h>
26 #include "rtsx_pcr.h"
28 static u8 rts5209_get_ic_version(struct rtsx_pcr *pcr)
30 u8 val;
32 val = rtsx_pci_readb(pcr, 0x1C);
33 return val & 0x0F;
36 static void rts5209_fetch_vendor_settings(struct rtsx_pcr *pcr)
38 u32 reg;
40 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
41 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
43 if (rts5209_vendor_setting1_valid(reg)) {
44 if (rts5209_reg_check_ms_pmos(reg))
45 pcr->flags |= PCR_MS_PMOS;
46 pcr->aspm_en = rts5209_reg_to_aspm(reg);
49 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
50 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
52 if (rts5209_vendor_setting2_valid(reg)) {
53 pcr->sd30_drive_sel_1v8 =
54 rts5209_reg_to_sd30_drive_sel_1v8(reg);
55 pcr->sd30_drive_sel_3v3 =
56 rts5209_reg_to_sd30_drive_sel_3v3(reg);
57 pcr->card_drive_sel = rts5209_reg_to_card_drive_sel(reg);
61 static void rts5209_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
63 rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07);
66 static int rts5209_extra_init_hw(struct rtsx_pcr *pcr)
68 rtsx_pci_init_cmd(pcr);
70 /* Turn off LED */
71 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO, 0xFF, 0x03);
72 /* Reset ASPM state to default value */
73 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
74 /* Force CLKREQ# PIN to drive 0 to request clock */
75 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
76 /* Configure GPIO as output */
77 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO_DIR, 0xFF, 0x03);
78 /* Configure driving */
79 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
80 0xFF, pcr->sd30_drive_sel_3v3);
82 return rtsx_pci_send_cmd(pcr, 100);
85 static int rts5209_optimize_phy(struct rtsx_pcr *pcr)
87 return rtsx_pci_write_phy_register(pcr, 0x00, 0xB966);
90 static int rts5209_turn_on_led(struct rtsx_pcr *pcr)
92 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
95 static int rts5209_turn_off_led(struct rtsx_pcr *pcr)
97 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
100 static int rts5209_enable_auto_blink(struct rtsx_pcr *pcr)
102 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
105 static int rts5209_disable_auto_blink(struct rtsx_pcr *pcr)
107 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
110 static int rts5209_card_power_on(struct rtsx_pcr *pcr, int card)
112 int err;
113 u8 pwr_mask, partial_pwr_on, pwr_on;
115 pwr_mask = SD_POWER_MASK;
116 partial_pwr_on = SD_PARTIAL_POWER_ON;
117 pwr_on = SD_POWER_ON;
119 if ((pcr->flags & PCR_MS_PMOS) && (card == RTSX_MS_CARD)) {
120 pwr_mask = MS_POWER_MASK;
121 partial_pwr_on = MS_PARTIAL_POWER_ON;
122 pwr_on = MS_POWER_ON;
125 rtsx_pci_init_cmd(pcr);
126 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
127 pwr_mask, partial_pwr_on);
128 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
129 LDO3318_PWR_MASK, 0x04);
130 err = rtsx_pci_send_cmd(pcr, 100);
131 if (err < 0)
132 return err;
134 /* To avoid too large in-rush current */
135 udelay(150);
137 rtsx_pci_init_cmd(pcr);
138 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, pwr_mask, pwr_on);
139 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
140 LDO3318_PWR_MASK, 0x00);
141 return rtsx_pci_send_cmd(pcr, 100);
144 static int rts5209_card_power_off(struct rtsx_pcr *pcr, int card)
146 u8 pwr_mask, pwr_off;
148 pwr_mask = SD_POWER_MASK;
149 pwr_off = SD_POWER_OFF;
151 if ((pcr->flags & PCR_MS_PMOS) && (card == RTSX_MS_CARD)) {
152 pwr_mask = MS_POWER_MASK;
153 pwr_off = MS_POWER_OFF;
156 rtsx_pci_init_cmd(pcr);
157 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
158 pwr_mask | PMOS_STRG_MASK, pwr_off | PMOS_STRG_400mA);
159 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
160 LDO3318_PWR_MASK, 0x06);
161 return rtsx_pci_send_cmd(pcr, 100);
164 static int rts5209_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
166 int err;
168 if (voltage == OUTPUT_3V3) {
169 err = rtsx_pci_write_register(pcr,
170 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
171 if (err < 0)
172 return err;
173 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
174 if (err < 0)
175 return err;
176 } else if (voltage == OUTPUT_1V8) {
177 err = rtsx_pci_write_register(pcr,
178 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
179 if (err < 0)
180 return err;
181 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24);
182 if (err < 0)
183 return err;
184 } else {
185 return -EINVAL;
188 return 0;
191 static const struct pcr_ops rts5209_pcr_ops = {
192 .fetch_vendor_settings = rts5209_fetch_vendor_settings,
193 .extra_init_hw = rts5209_extra_init_hw,
194 .optimize_phy = rts5209_optimize_phy,
195 .turn_on_led = rts5209_turn_on_led,
196 .turn_off_led = rts5209_turn_off_led,
197 .enable_auto_blink = rts5209_enable_auto_blink,
198 .disable_auto_blink = rts5209_disable_auto_blink,
199 .card_power_on = rts5209_card_power_on,
200 .card_power_off = rts5209_card_power_off,
201 .switch_output_voltage = rts5209_switch_output_voltage,
202 .cd_deglitch = NULL,
203 .conv_clk_and_div_n = NULL,
204 .force_power_down = rts5209_force_power_down,
207 /* SD Pull Control Enable:
208 * SD_DAT[3:0] ==> pull up
209 * SD_CD ==> pull up
210 * SD_WP ==> pull up
211 * SD_CMD ==> pull up
212 * SD_CLK ==> pull down
214 static const u32 rts5209_sd_pull_ctl_enable_tbl[] = {
215 RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
216 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
217 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
221 /* SD Pull Control Disable:
222 * SD_DAT[3:0] ==> pull down
223 * SD_CD ==> pull up
224 * SD_WP ==> pull down
225 * SD_CMD ==> pull down
226 * SD_CLK ==> pull down
228 static const u32 rts5209_sd_pull_ctl_disable_tbl[] = {
229 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x55),
230 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
231 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
235 /* MS Pull Control Enable:
236 * MS CD ==> pull up
237 * others ==> pull down
239 static const u32 rts5209_ms_pull_ctl_enable_tbl[] = {
240 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
241 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
242 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
246 /* MS Pull Control Disable:
247 * MS CD ==> pull up
248 * others ==> pull down
250 static const u32 rts5209_ms_pull_ctl_disable_tbl[] = {
251 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
252 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
253 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
257 void rts5209_init_params(struct rtsx_pcr *pcr)
259 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 |
260 EXTRA_CAPS_SD_SDR104 | EXTRA_CAPS_MMC_8BIT;
261 pcr->num_slots = 2;
262 pcr->ops = &rts5209_pcr_ops;
264 pcr->flags = 0;
265 pcr->card_drive_sel = RTS5209_CARD_DRIVE_DEFAULT;
266 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
267 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
268 pcr->aspm_en = ASPM_L1_EN;
269 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 16);
270 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
272 pcr->ic_version = rts5209_get_ic_version(pcr);
273 pcr->sd_pull_ctl_enable_tbl = rts5209_sd_pull_ctl_enable_tbl;
274 pcr->sd_pull_ctl_disable_tbl = rts5209_sd_pull_ctl_disable_tbl;
275 pcr->ms_pull_ctl_enable_tbl = rts5209_ms_pull_ctl_enable_tbl;
276 pcr->ms_pull_ctl_disable_tbl = rts5209_ms_pull_ctl_disable_tbl;