2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/export.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
48 #include <asm/io_apic.h>
56 #include <asm/hypervisor.h>
57 #include <asm/cpu_device_id.h>
58 #include <asm/intel-family.h>
60 unsigned int num_processors
;
62 unsigned disabled_cpus
;
64 /* Processor that is doing the boot up */
65 unsigned int boot_cpu_physical_apicid
= -1U;
66 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid
);
68 u8 boot_cpu_apic_version
;
71 * The highest APIC ID seen during enumeration.
73 static unsigned int max_physical_apicid
;
76 * Bitmask of physically existing CPUs:
78 physid_mask_t phys_cpu_present_map
;
81 * Processor to be disabled specified by kernel parameter
82 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
83 * avoid undefined behaviour caused by sending INIT from AP to BSP.
85 static unsigned int disabled_cpu_apicid __read_mostly
= BAD_APICID
;
88 * This variable controls which CPUs receive external NMIs. By default,
89 * external NMIs are delivered only to the BSP.
91 static int apic_extnmi
= APIC_EXTNMI_BSP
;
94 * Map cpu index to physical APIC ID
96 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16
, x86_cpu_to_apicid
, BAD_APICID
);
97 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32
, x86_cpu_to_acpiid
, U32_MAX
);
99 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
100 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid
);
106 * On x86_32, the mapping between cpu and logical apicid may vary
107 * depending on apic in use. The following early percpu variable is
108 * used for the mapping. This is where the behaviors of x86_64 and 32
109 * actually diverge. Let's keep it ugly for now.
111 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid
, BAD_APICID
);
113 /* Local APIC was disabled by the BIOS and enabled by the kernel */
114 static int enabled_via_apicbase
;
117 * Handle interrupt mode configuration register (IMCR).
118 * This register controls whether the interrupt signals
119 * that reach the BSP come from the master PIC or from the
120 * local APIC. Before entering Symmetric I/O Mode, either
121 * the BIOS or the operating system must switch out of
122 * PIC Mode by changing the IMCR.
124 static inline void imcr_pic_to_apic(void)
126 /* select IMCR register */
128 /* NMI and 8259 INTR go through APIC */
132 static inline void imcr_apic_to_pic(void)
134 /* select IMCR register */
136 /* NMI and 8259 INTR go directly to BSP */
142 * Knob to control our willingness to enable the local APIC.
146 static int force_enable_local_apic __initdata
;
149 * APIC command line parameters
151 static int __init
parse_lapic(char *arg
)
153 if (IS_ENABLED(CONFIG_X86_32
) && !arg
)
154 force_enable_local_apic
= 1;
155 else if (arg
&& !strncmp(arg
, "notscdeadline", 13))
156 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER
);
159 early_param("lapic", parse_lapic
);
162 static int apic_calibrate_pmtmr __initdata
;
163 static __init
int setup_apicpmtimer(char *s
)
165 apic_calibrate_pmtmr
= 1;
169 __setup("apicpmtimer", setup_apicpmtimer
);
172 unsigned long mp_lapic_addr
;
174 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
175 static int disable_apic_timer __initdata
;
176 /* Local APIC timer works in C2 */
177 int local_apic_timer_c2_ok
;
178 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
181 * Debug level, exported for io_apic.c
183 unsigned int apic_verbosity
;
187 /* Have we found an MP table */
188 int smp_found_config
;
190 static struct resource lapic_resource
= {
191 .name
= "Local APIC",
192 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
195 unsigned int lapic_timer_frequency
= 0;
197 static void apic_pm_activate(void);
199 static unsigned long apic_phys
;
202 * Get the LAPIC version
204 static inline int lapic_get_version(void)
206 return GET_APIC_VERSION(apic_read(APIC_LVR
));
210 * Check, if the APIC is integrated or a separate chip
212 static inline int lapic_is_integrated(void)
217 return APIC_INTEGRATED(lapic_get_version());
222 * Check, whether this is a modern or a first generation APIC
224 static int modern_apic(void)
226 /* AMD systems use old APIC versions, so check the CPU */
227 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
228 boot_cpu_data
.x86
>= 0xf)
230 return lapic_get_version() >= 0x14;
234 * right after this call apic become NOOP driven
235 * so apic->write/read doesn't do anything
237 static void __init
apic_disable(void)
239 pr_info("APIC: switched to apic NOOP\n");
243 void native_apic_wait_icr_idle(void)
245 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
249 u32
native_safe_apic_wait_icr_idle(void)
256 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
259 inc_irq_stat(icr_read_retry_count
);
261 } while (timeout
++ < 1000);
266 void native_apic_icr_write(u32 low
, u32 id
)
270 local_irq_save(flags
);
271 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
272 apic_write(APIC_ICR
, low
);
273 local_irq_restore(flags
);
276 u64
native_apic_icr_read(void)
280 icr2
= apic_read(APIC_ICR2
);
281 icr1
= apic_read(APIC_ICR
);
283 return icr1
| ((u64
)icr2
<< 32);
288 * get_physical_broadcast - Get number of physical broadcast IDs
290 int get_physical_broadcast(void)
292 return modern_apic() ? 0xff : 0xf;
297 * lapic_get_maxlvt - get the maximum number of local vector table entries
299 int lapic_get_maxlvt(void)
303 v
= apic_read(APIC_LVR
);
305 * - we always have APIC integrated on 64bit mode
306 * - 82489DXs do not report # of LVT entries
308 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
316 #define APIC_DIVISOR 16
317 #define TSC_DIVISOR 8
320 * This function sets up the local APIC timer, with a timeout of
321 * 'clocks' APIC bus clock. During calibration we actually call
322 * this function twice on the boot CPU, once with a bogus timeout
323 * value, second time for real. The other (noncalibrating) CPUs
324 * call this function only once, with the real, calibrated value.
326 * We do reads before writes even if unnecessary, to get around the
327 * P5 APIC double write bug.
329 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
331 unsigned int lvtt_value
, tmp_value
;
333 lvtt_value
= LOCAL_TIMER_VECTOR
;
335 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
336 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
))
337 lvtt_value
|= APIC_LVT_TIMER_TSCDEADLINE
;
339 if (!lapic_is_integrated())
340 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
343 lvtt_value
|= APIC_LVT_MASKED
;
345 apic_write(APIC_LVTT
, lvtt_value
);
347 if (lvtt_value
& APIC_LVT_TIMER_TSCDEADLINE
) {
349 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
350 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
351 * According to Intel, MFENCE can do the serialization here.
353 asm volatile("mfence" : : : "memory");
355 printk_once(KERN_DEBUG
"TSC deadline timer enabled\n");
362 tmp_value
= apic_read(APIC_TDCR
);
363 apic_write(APIC_TDCR
,
364 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
368 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
372 * Setup extended LVT, AMD specific
374 * Software should use the LVT offsets the BIOS provides. The offsets
375 * are determined by the subsystems using it like those for MCE
376 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
377 * are supported. Beginning with family 10h at least 4 offsets are
380 * Since the offsets must be consistent for all cores, we keep track
381 * of the LVT offsets in software and reserve the offset for the same
382 * vector also to be used on other cores. An offset is freed by
383 * setting the entry to APIC_EILVT_MASKED.
385 * If the BIOS is right, there should be no conflicts. Otherwise a
386 * "[Firmware Bug]: ..." error message is generated. However, if
387 * software does not properly determines the offsets, it is not
388 * necessarily a BIOS bug.
391 static atomic_t eilvt_offsets
[APIC_EILVT_NR_MAX
];
393 static inline int eilvt_entry_is_changeable(unsigned int old
, unsigned int new)
395 return (old
& APIC_EILVT_MASKED
)
396 || (new == APIC_EILVT_MASKED
)
397 || ((new & ~APIC_EILVT_MASKED
) == old
);
400 static unsigned int reserve_eilvt_offset(int offset
, unsigned int new)
402 unsigned int rsvd
, vector
;
404 if (offset
>= APIC_EILVT_NR_MAX
)
407 rsvd
= atomic_read(&eilvt_offsets
[offset
]);
409 vector
= rsvd
& ~APIC_EILVT_MASKED
; /* 0: unassigned */
410 if (vector
&& !eilvt_entry_is_changeable(vector
, new))
411 /* may not change if vectors are different */
413 rsvd
= atomic_cmpxchg(&eilvt_offsets
[offset
], rsvd
, new);
414 } while (rsvd
!= new);
416 rsvd
&= ~APIC_EILVT_MASKED
;
417 if (rsvd
&& rsvd
!= vector
)
418 pr_info("LVT offset %d assigned for vector 0x%02x\n",
425 * If mask=1, the LVT entry does not generate interrupts while mask=0
426 * enables the vector. See also the BKDGs. Must be called with
427 * preemption disabled.
430 int setup_APIC_eilvt(u8 offset
, u8 vector
, u8 msg_type
, u8 mask
)
432 unsigned long reg
= APIC_EILVTn(offset
);
433 unsigned int new, old
, reserved
;
435 new = (mask
<< 16) | (msg_type
<< 8) | vector
;
436 old
= apic_read(reg
);
437 reserved
= reserve_eilvt_offset(offset
, new);
439 if (reserved
!= new) {
440 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
441 "vector 0x%x, but the register is already in use for "
442 "vector 0x%x on another cpu\n",
443 smp_processor_id(), reg
, offset
, new, reserved
);
447 if (!eilvt_entry_is_changeable(old
, new)) {
448 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
449 "vector 0x%x, but the register is already in use for "
450 "vector 0x%x on this cpu\n",
451 smp_processor_id(), reg
, offset
, new, old
);
455 apic_write(reg
, new);
459 EXPORT_SYMBOL_GPL(setup_APIC_eilvt
);
462 * Program the next event, relative to now
464 static int lapic_next_event(unsigned long delta
,
465 struct clock_event_device
*evt
)
467 apic_write(APIC_TMICT
, delta
);
471 static int lapic_next_deadline(unsigned long delta
,
472 struct clock_event_device
*evt
)
477 wrmsrl(MSR_IA32_TSC_DEADLINE
, tsc
+ (((u64
) delta
) * TSC_DIVISOR
));
481 static int lapic_timer_shutdown(struct clock_event_device
*evt
)
485 /* Lapic used as dummy for broadcast ? */
486 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
489 v
= apic_read(APIC_LVTT
);
490 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
491 apic_write(APIC_LVTT
, v
);
492 apic_write(APIC_TMICT
, 0);
497 lapic_timer_set_periodic_oneshot(struct clock_event_device
*evt
, bool oneshot
)
499 /* Lapic used as dummy for broadcast ? */
500 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
503 __setup_APIC_LVTT(lapic_timer_frequency
, oneshot
, 1);
507 static int lapic_timer_set_periodic(struct clock_event_device
*evt
)
509 return lapic_timer_set_periodic_oneshot(evt
, false);
512 static int lapic_timer_set_oneshot(struct clock_event_device
*evt
)
514 return lapic_timer_set_periodic_oneshot(evt
, true);
518 * Local APIC timer broadcast function
520 static void lapic_timer_broadcast(const struct cpumask
*mask
)
523 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
529 * The local apic timer can be used for any function which is CPU local.
531 static struct clock_event_device lapic_clockevent
= {
533 .features
= CLOCK_EVT_FEAT_PERIODIC
|
534 CLOCK_EVT_FEAT_ONESHOT
| CLOCK_EVT_FEAT_C3STOP
535 | CLOCK_EVT_FEAT_DUMMY
,
537 .set_state_shutdown
= lapic_timer_shutdown
,
538 .set_state_periodic
= lapic_timer_set_periodic
,
539 .set_state_oneshot
= lapic_timer_set_oneshot
,
540 .set_state_oneshot_stopped
= lapic_timer_shutdown
,
541 .set_next_event
= lapic_next_event
,
542 .broadcast
= lapic_timer_broadcast
,
546 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
548 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \
549 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
551 #define DEADLINE_MODEL_MATCH_REV(model, rev) \
552 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
554 static u32
hsx_deadline_rev(void)
556 switch (boot_cpu_data
.x86_mask
) {
557 case 0x02: return 0x3a; /* EP */
558 case 0x04: return 0x0f; /* EX */
564 static u32
bdx_deadline_rev(void)
566 switch (boot_cpu_data
.x86_mask
) {
567 case 0x02: return 0x00000011;
568 case 0x03: return 0x0700000e;
569 case 0x04: return 0x0f00000c;
570 case 0x05: return 0x0e000003;
576 static const struct x86_cpu_id deadline_match
[] = {
577 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X
, hsx_deadline_rev
),
578 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X
, 0x0b000020),
579 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D
, bdx_deadline_rev
),
580 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_X
, 0x02000014),
582 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE
, 0x22),
583 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT
, 0x20),
584 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E
, 0x17),
586 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE
, 0x25),
587 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E
, 0x17),
589 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE
, 0xb2),
590 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP
, 0xb2),
592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE
, 0x52),
593 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP
, 0x52),
598 static void apic_check_deadline_errata(void)
600 const struct x86_cpu_id
*m
= x86_match_cpu(deadline_match
);
607 * Function pointers will have the MSB set due to address layout,
608 * immediate revisions will not.
610 if ((long)m
->driver_data
< 0)
611 rev
= ((u32 (*)(void))(m
->driver_data
))();
613 rev
= (u32
)m
->driver_data
;
615 if (boot_cpu_data
.microcode
>= rev
)
618 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER
);
619 pr_err(FW_BUG
"TSC_DEADLINE disabled due to Errata; "
620 "please update microcode to version: 0x%x (or later)\n", rev
);
624 * Setup the local APIC timer for this CPU. Copy the initialized values
625 * of the boot CPU and register the clock event in the framework.
627 static void setup_APIC_timer(void)
629 struct clock_event_device
*levt
= this_cpu_ptr(&lapic_events
);
631 if (this_cpu_has(X86_FEATURE_ARAT
)) {
632 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
633 /* Make LAPIC timer preferrable over percpu HPET */
634 lapic_clockevent
.rating
= 150;
637 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
638 levt
->cpumask
= cpumask_of(smp_processor_id());
640 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
)) {
641 levt
->name
= "lapic-deadline";
642 levt
->features
&= ~(CLOCK_EVT_FEAT_PERIODIC
|
643 CLOCK_EVT_FEAT_DUMMY
);
644 levt
->set_next_event
= lapic_next_deadline
;
645 clockevents_config_and_register(levt
,
646 tsc_khz
* (1000 / TSC_DIVISOR
),
649 clockevents_register_device(levt
);
653 * Install the updated TSC frequency from recalibration at the TSC
654 * deadline clockevent devices.
656 static void __lapic_update_tsc_freq(void *info
)
658 struct clock_event_device
*levt
= this_cpu_ptr(&lapic_events
);
660 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
))
663 clockevents_update_freq(levt
, tsc_khz
* (1000 / TSC_DIVISOR
));
666 void lapic_update_tsc_freq(void)
669 * The clockevent device's ->mult and ->shift can both be
670 * changed. In order to avoid races, schedule the frequency
671 * update code on each CPU.
673 on_each_cpu(__lapic_update_tsc_freq
, NULL
, 0);
677 * In this functions we calibrate APIC bus clocks to the external timer.
679 * We want to do the calibration only once since we want to have local timer
680 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
683 * This was previously done by reading the PIT/HPET and waiting for a wrap
684 * around to find out, that a tick has elapsed. I have a box, where the PIT
685 * readout is broken, so it never gets out of the wait loop again. This was
686 * also reported by others.
688 * Monitoring the jiffies value is inaccurate and the clockevents
689 * infrastructure allows us to do a simple substitution of the interrupt
692 * The calibration routine also uses the pm_timer when possible, as the PIT
693 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
694 * back to normal later in the boot process).
697 #define LAPIC_CAL_LOOPS (HZ/10)
699 static __initdata
int lapic_cal_loops
= -1;
700 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
701 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
702 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
703 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
706 * Temporary interrupt handler.
708 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
710 unsigned long long tsc
= 0;
711 long tapic
= apic_read(APIC_TMCCT
);
712 unsigned long pm
= acpi_pm_read_early();
714 if (boot_cpu_has(X86_FEATURE_TSC
))
717 switch (lapic_cal_loops
++) {
719 lapic_cal_t1
= tapic
;
720 lapic_cal_tsc1
= tsc
;
722 lapic_cal_j1
= jiffies
;
725 case LAPIC_CAL_LOOPS
:
726 lapic_cal_t2
= tapic
;
727 lapic_cal_tsc2
= tsc
;
728 if (pm
< lapic_cal_pm1
)
729 pm
+= ACPI_PM_OVRRUN
;
731 lapic_cal_j2
= jiffies
;
737 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
739 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
740 const long pm_thresh
= pm_100ms
/ 100;
744 #ifndef CONFIG_X86_PM_TIMER
748 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
750 /* Check, if the PM timer is available */
754 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
756 if (deltapm
> (pm_100ms
- pm_thresh
) &&
757 deltapm
< (pm_100ms
+ pm_thresh
)) {
758 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
762 res
= (((u64
)deltapm
) * mult
) >> 22;
763 do_div(res
, 1000000);
764 pr_warning("APIC calibration not consistent "
765 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
767 /* Correct the lapic counter value */
768 res
= (((u64
)(*delta
)) * pm_100ms
);
769 do_div(res
, deltapm
);
770 pr_info("APIC delta adjusted to PM-Timer: "
771 "%lu (%ld)\n", (unsigned long)res
, *delta
);
774 /* Correct the tsc counter value */
775 if (boot_cpu_has(X86_FEATURE_TSC
)) {
776 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
777 do_div(res
, deltapm
);
778 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
779 "PM-Timer: %lu (%ld)\n",
780 (unsigned long)res
, *deltatsc
);
781 *deltatsc
= (long)res
;
787 static int __init
calibrate_APIC_clock(void)
789 struct clock_event_device
*levt
= this_cpu_ptr(&lapic_events
);
790 void (*real_handler
)(struct clock_event_device
*dev
);
791 unsigned long deltaj
;
792 long delta
, deltatsc
;
793 int pm_referenced
= 0;
796 * check if lapic timer has already been calibrated by platform
797 * specific routine, such as tsc calibration code. if so, we just fill
798 * in the clockevent structure and return.
801 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER
)) {
803 } else if (lapic_timer_frequency
) {
804 apic_printk(APIC_VERBOSE
, "lapic timer already calibrated %d\n",
805 lapic_timer_frequency
);
806 lapic_clockevent
.mult
= div_sc(lapic_timer_frequency
/APIC_DIVISOR
,
807 TICK_NSEC
, lapic_clockevent
.shift
);
808 lapic_clockevent
.max_delta_ns
=
809 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
810 lapic_clockevent
.max_delta_ticks
= 0x7FFFFF;
811 lapic_clockevent
.min_delta_ns
=
812 clockevent_delta2ns(0xF, &lapic_clockevent
);
813 lapic_clockevent
.min_delta_ticks
= 0xF;
814 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
818 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
819 "calibrating APIC timer ...\n");
823 /* Replace the global interrupt handler */
824 real_handler
= global_clock_event
->event_handler
;
825 global_clock_event
->event_handler
= lapic_cal_handler
;
828 * Setup the APIC counter to maximum. There is no way the lapic
829 * can underflow in the 100ms detection time frame
831 __setup_APIC_LVTT(0xffffffff, 0, 0);
833 /* Let the interrupts run */
836 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
841 /* Restore the real event handler */
842 global_clock_event
->event_handler
= real_handler
;
844 /* Build delta t1-t2 as apic timer counts down */
845 delta
= lapic_cal_t1
- lapic_cal_t2
;
846 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
848 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
850 /* we trust the PM based calibration if possible */
851 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
854 /* Calculate the scaled math multiplication factor */
855 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
856 lapic_clockevent
.shift
);
857 lapic_clockevent
.max_delta_ns
=
858 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent
);
859 lapic_clockevent
.max_delta_ticks
= 0x7FFFFFFF;
860 lapic_clockevent
.min_delta_ns
=
861 clockevent_delta2ns(0xF, &lapic_clockevent
);
862 lapic_clockevent
.min_delta_ticks
= 0xF;
864 lapic_timer_frequency
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
866 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
867 apic_printk(APIC_VERBOSE
, "..... mult: %u\n", lapic_clockevent
.mult
);
868 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
869 lapic_timer_frequency
);
871 if (boot_cpu_has(X86_FEATURE_TSC
)) {
872 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
874 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
875 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
878 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
880 lapic_timer_frequency
/ (1000000 / HZ
),
881 lapic_timer_frequency
% (1000000 / HZ
));
884 * Do a sanity check on the APIC calibration result
886 if (lapic_timer_frequency
< (1000000 / HZ
)) {
888 pr_warning("APIC frequency too slow, disabling apic timer\n");
892 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
895 * PM timer calibration failed or not turned on
896 * so lets try APIC timer based calibration
898 if (!pm_referenced
) {
899 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
902 * Setup the apic timer manually
904 levt
->event_handler
= lapic_cal_handler
;
905 lapic_timer_set_periodic(levt
);
906 lapic_cal_loops
= -1;
908 /* Let the interrupts run */
911 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
914 /* Stop the lapic timer */
916 lapic_timer_shutdown(levt
);
919 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
920 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
922 /* Check, if the jiffies result is consistent */
923 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
924 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
926 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
930 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
931 pr_warning("APIC timer disabled due to verification failure\n");
939 * Setup the boot APIC
941 * Calibrate and verify the result.
943 void __init
setup_boot_APIC_clock(void)
946 * The local apic timer can be disabled via the kernel
947 * commandline or from the CPU detection code. Register the lapic
948 * timer as a dummy clock event source on SMP systems, so the
949 * broadcast mechanism is used. On UP systems simply ignore it.
951 if (disable_apic_timer
) {
952 pr_info("Disabling APIC timer\n");
953 /* No broadcast on UP ! */
954 if (num_possible_cpus() > 1) {
955 lapic_clockevent
.mult
= 1;
961 if (calibrate_APIC_clock()) {
962 /* No broadcast on UP ! */
963 if (num_possible_cpus() > 1)
969 * If nmi_watchdog is set to IO_APIC, we need the
970 * PIT/HPET going. Otherwise register lapic as a dummy
973 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
975 /* Setup the lapic or request the broadcast */
977 amd_e400_c1e_apic_setup();
980 void setup_secondary_APIC_clock(void)
983 amd_e400_c1e_apic_setup();
987 * The guts of the apic timer interrupt
989 static void local_apic_timer_interrupt(void)
991 int cpu
= smp_processor_id();
992 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
995 * Normally we should not be here till LAPIC has been initialized but
996 * in some cases like kdump, its possible that there is a pending LAPIC
997 * timer interrupt from previous kernel's context and is delivered in
998 * new kernel the moment interrupts are enabled.
1000 * Interrupts are enabled early and LAPIC is setup much later, hence
1001 * its possible that when we get here evt->event_handler is NULL.
1002 * Check for event_handler being NULL and discard the interrupt as
1005 if (!evt
->event_handler
) {
1006 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
1008 lapic_timer_shutdown(evt
);
1013 * the NMI deadlock-detector uses this.
1015 inc_irq_stat(apic_timer_irqs
);
1017 evt
->event_handler(evt
);
1021 * Local APIC timer interrupt. This is the most natural way for doing
1022 * local interrupts, but local timer interrupts can be emulated by
1023 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1025 * [ if a single-CPU system runs an SMP kernel then we call the local
1026 * interrupt as well. Thus we cannot inline the local irq ... ]
1028 __visible
void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
1030 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1033 * NOTE! We'd better ACK the irq immediately,
1034 * because timer handling can be slow.
1036 * update_process_times() expects us to have done irq_enter().
1037 * Besides, if we don't timer interrupts ignore the global
1038 * interrupt lock, which is the WrongThing (tm) to do.
1041 trace_local_timer_entry(LOCAL_TIMER_VECTOR
);
1042 local_apic_timer_interrupt();
1043 trace_local_timer_exit(LOCAL_TIMER_VECTOR
);
1046 set_irq_regs(old_regs
);
1049 int setup_profiling_timer(unsigned int multiplier
)
1055 * Local APIC start and shutdown
1059 * clear_local_APIC - shutdown the local APIC
1061 * This is called, when a CPU is disabled and before rebooting, so the state of
1062 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1063 * leftovers during boot.
1065 void clear_local_APIC(void)
1070 /* APIC hasn't been mapped yet */
1071 if (!x2apic_mode
&& !apic_phys
)
1074 maxlvt
= lapic_get_maxlvt();
1076 * Masking an LVT entry can trigger a local APIC error
1077 * if the vector is zero. Mask LVTERR first to prevent this.
1080 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
1081 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
1084 * Careful: we have to set masks only first to deassert
1085 * any level-triggered sources.
1087 v
= apic_read(APIC_LVTT
);
1088 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
1089 v
= apic_read(APIC_LVT0
);
1090 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1091 v
= apic_read(APIC_LVT1
);
1092 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
1094 v
= apic_read(APIC_LVTPC
);
1095 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
1098 /* lets not touch this if we didn't frob it */
1099 #ifdef CONFIG_X86_THERMAL_VECTOR
1101 v
= apic_read(APIC_LVTTHMR
);
1102 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
1105 #ifdef CONFIG_X86_MCE_INTEL
1107 v
= apic_read(APIC_LVTCMCI
);
1108 if (!(v
& APIC_LVT_MASKED
))
1109 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
1114 * Clean APIC state for other OSs:
1116 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
1117 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1118 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
1120 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
1122 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
1124 /* Integrated APIC (!82489DX) ? */
1125 if (lapic_is_integrated()) {
1127 /* Clear ESR due to Pentium errata 3AP and 11AP */
1128 apic_write(APIC_ESR
, 0);
1129 apic_read(APIC_ESR
);
1134 * disable_local_APIC - clear and disable the local APIC
1136 void disable_local_APIC(void)
1140 /* APIC hasn't been mapped yet */
1141 if (!x2apic_mode
&& !apic_phys
)
1147 * Disable APIC (implies clearing of registers
1150 value
= apic_read(APIC_SPIV
);
1151 value
&= ~APIC_SPIV_APIC_ENABLED
;
1152 apic_write(APIC_SPIV
, value
);
1154 #ifdef CONFIG_X86_32
1156 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1157 * restore the disabled state.
1159 if (enabled_via_apicbase
) {
1162 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1163 l
&= ~MSR_IA32_APICBASE_ENABLE
;
1164 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1170 * If Linux enabled the LAPIC against the BIOS default disable it down before
1171 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1172 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1173 * for the case where Linux didn't enable the LAPIC.
1175 void lapic_shutdown(void)
1177 unsigned long flags
;
1179 if (!boot_cpu_has(X86_FEATURE_APIC
) && !apic_from_smp_config())
1182 local_irq_save(flags
);
1184 #ifdef CONFIG_X86_32
1185 if (!enabled_via_apicbase
)
1189 disable_local_APIC();
1192 local_irq_restore(flags
);
1196 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1198 void __init
sync_Arb_IDs(void)
1201 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1204 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1210 apic_wait_icr_idle();
1212 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1213 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1214 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1218 * An initial setup of the virtual wire mode.
1220 void __init
init_bsp_APIC(void)
1225 * Don't do the setup now if we have a SMP BIOS as the
1226 * through-I/O-APIC virtual wire mode might be active.
1228 if (smp_found_config
|| !boot_cpu_has(X86_FEATURE_APIC
))
1232 * Do not trust the local APIC being empty at bootup.
1239 value
= apic_read(APIC_SPIV
);
1240 value
&= ~APIC_VECTOR_MASK
;
1241 value
|= APIC_SPIV_APIC_ENABLED
;
1243 #ifdef CONFIG_X86_32
1244 /* This bit is reserved on P4/Xeon and should be cleared */
1245 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1246 (boot_cpu_data
.x86
== 15))
1247 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1250 value
|= APIC_SPIV_FOCUS_DISABLED
;
1251 value
|= SPURIOUS_APIC_VECTOR
;
1252 apic_write(APIC_SPIV
, value
);
1255 * Set up the virtual wire mode.
1257 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1258 value
= APIC_DM_NMI
;
1259 if (!lapic_is_integrated()) /* 82489DX */
1260 value
|= APIC_LVT_LEVEL_TRIGGER
;
1261 if (apic_extnmi
== APIC_EXTNMI_NONE
)
1262 value
|= APIC_LVT_MASKED
;
1263 apic_write(APIC_LVT1
, value
);
1266 static void lapic_setup_esr(void)
1268 unsigned int oldvalue
, value
, maxlvt
;
1270 if (!lapic_is_integrated()) {
1271 pr_info("No ESR for 82489DX.\n");
1275 if (apic
->disable_esr
) {
1277 * Something untraceable is creating bad interrupts on
1278 * secondary quads ... for the moment, just leave the
1279 * ESR disabled - we can't do anything useful with the
1280 * errors anyway - mbligh
1282 pr_info("Leaving ESR disabled.\n");
1286 maxlvt
= lapic_get_maxlvt();
1287 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1288 apic_write(APIC_ESR
, 0);
1289 oldvalue
= apic_read(APIC_ESR
);
1291 /* enables sending errors */
1292 value
= ERROR_APIC_VECTOR
;
1293 apic_write(APIC_LVTERR
, value
);
1296 * spec says clear errors after enabling vector.
1299 apic_write(APIC_ESR
, 0);
1300 value
= apic_read(APIC_ESR
);
1301 if (value
!= oldvalue
)
1302 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1303 "vector: 0x%08x after: 0x%08x\n",
1308 * setup_local_APIC - setup the local APIC
1310 * Used to setup local APIC while initializing BSP or bringing up APs.
1311 * Always called with preemption disabled.
1313 void setup_local_APIC(void)
1315 int cpu
= smp_processor_id();
1316 unsigned int value
, queued
;
1317 int i
, j
, acked
= 0;
1318 unsigned long long tsc
= 0, ntsc
;
1319 long long max_loops
= cpu_khz
? cpu_khz
: 1000000;
1321 if (boot_cpu_has(X86_FEATURE_TSC
))
1325 disable_ioapic_support();
1329 #ifdef CONFIG_X86_32
1330 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1331 if (lapic_is_integrated() && apic
->disable_esr
) {
1332 apic_write(APIC_ESR
, 0);
1333 apic_write(APIC_ESR
, 0);
1334 apic_write(APIC_ESR
, 0);
1335 apic_write(APIC_ESR
, 0);
1338 perf_events_lapic_init();
1341 * Double-check whether this APIC is really registered.
1342 * This is meaningless in clustered apic mode, so we skip it.
1344 BUG_ON(!apic
->apic_id_registered());
1347 * Intel recommends to set DFR, LDR and TPR before enabling
1348 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1349 * document number 292116). So here it goes...
1351 apic
->init_apic_ldr();
1353 #ifdef CONFIG_X86_32
1355 * APIC LDR is initialized. If logical_apicid mapping was
1356 * initialized during get_smp_config(), make sure it matches the
1359 i
= early_per_cpu(x86_cpu_to_logical_apicid
, cpu
);
1360 WARN_ON(i
!= BAD_APICID
&& i
!= logical_smp_processor_id());
1361 /* always use the value from LDR */
1362 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) =
1363 logical_smp_processor_id();
1367 * Set Task Priority to 'accept all'. We never change this
1370 value
= apic_read(APIC_TASKPRI
);
1371 value
&= ~APIC_TPRI_MASK
;
1372 apic_write(APIC_TASKPRI
, value
);
1375 * After a crash, we no longer service the interrupts and a pending
1376 * interrupt from previous kernel might still have ISR bit set.
1378 * Most probably by now CPU has serviced that pending interrupt and
1379 * it might not have done the ack_APIC_irq() because it thought,
1380 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1381 * does not clear the ISR bit and cpu thinks it has already serivced
1382 * the interrupt. Hence a vector might get locked. It was noticed
1383 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1387 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--)
1388 queued
|= apic_read(APIC_IRR
+ i
*0x10);
1390 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1391 value
= apic_read(APIC_ISR
+ i
*0x10);
1392 for (j
= 31; j
>= 0; j
--) {
1393 if (value
& (1<<j
)) {
1400 printk(KERN_ERR
"LAPIC pending interrupts after %d EOI\n",
1405 if (boot_cpu_has(X86_FEATURE_TSC
) && cpu_khz
) {
1407 max_loops
= (cpu_khz
<< 10) - (ntsc
- tsc
);
1411 } while (queued
&& max_loops
> 0);
1412 WARN_ON(max_loops
<= 0);
1415 * Now that we are all set up, enable the APIC
1417 value
= apic_read(APIC_SPIV
);
1418 value
&= ~APIC_VECTOR_MASK
;
1422 value
|= APIC_SPIV_APIC_ENABLED
;
1424 #ifdef CONFIG_X86_32
1426 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1427 * certain networking cards. If high frequency interrupts are
1428 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1429 * entry is masked/unmasked at a high rate as well then sooner or
1430 * later IOAPIC line gets 'stuck', no more interrupts are received
1431 * from the device. If focus CPU is disabled then the hang goes
1434 * [ This bug can be reproduced easily with a level-triggered
1435 * PCI Ne2000 networking cards and PII/PIII processors, dual
1439 * Actually disabling the focus CPU check just makes the hang less
1440 * frequent as it makes the interrupt distributon model be more
1441 * like LRU than MRU (the short-term load is more even across CPUs).
1445 * - enable focus processor (bit==0)
1446 * - 64bit mode always use processor focus
1447 * so no need to set it
1449 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1453 * Set spurious IRQ vector
1455 value
|= SPURIOUS_APIC_VECTOR
;
1456 apic_write(APIC_SPIV
, value
);
1459 * Set up LVT0, LVT1:
1461 * set up through-local-APIC on the BP's LINT0. This is not
1462 * strictly necessary in pure symmetric-IO mode, but sometimes
1463 * we delegate interrupts to the 8259A.
1466 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1468 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1469 if (!cpu
&& (pic_mode
|| !value
)) {
1470 value
= APIC_DM_EXTINT
;
1471 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n", cpu
);
1473 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1474 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n", cpu
);
1476 apic_write(APIC_LVT0
, value
);
1479 * Only the BSP sees the LINT1 NMI signal by default. This can be
1480 * modified by apic_extnmi= boot option.
1482 if ((!cpu
&& apic_extnmi
!= APIC_EXTNMI_NONE
) ||
1483 apic_extnmi
== APIC_EXTNMI_ALL
)
1484 value
= APIC_DM_NMI
;
1486 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1487 if (!lapic_is_integrated()) /* 82489DX */
1488 value
|= APIC_LVT_LEVEL_TRIGGER
;
1489 apic_write(APIC_LVT1
, value
);
1491 #ifdef CONFIG_X86_MCE_INTEL
1492 /* Recheck CMCI information after local APIC is up on CPU #0 */
1498 static void end_local_APIC_setup(void)
1502 #ifdef CONFIG_X86_32
1505 /* Disable the local apic timer */
1506 value
= apic_read(APIC_LVTT
);
1507 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1508 apic_write(APIC_LVTT
, value
);
1516 * APIC setup function for application processors. Called from smpboot.c
1518 void apic_ap_setup(void)
1521 end_local_APIC_setup();
1524 #ifdef CONFIG_X86_X2APIC
1532 static int x2apic_state
;
1534 static void __x2apic_disable(void)
1538 if (!boot_cpu_has(X86_FEATURE_APIC
))
1541 rdmsrl(MSR_IA32_APICBASE
, msr
);
1542 if (!(msr
& X2APIC_ENABLE
))
1544 /* Disable xapic and x2apic first and then reenable xapic mode */
1545 wrmsrl(MSR_IA32_APICBASE
, msr
& ~(X2APIC_ENABLE
| XAPIC_ENABLE
));
1546 wrmsrl(MSR_IA32_APICBASE
, msr
& ~X2APIC_ENABLE
);
1547 printk_once(KERN_INFO
"x2apic disabled\n");
1550 static void __x2apic_enable(void)
1554 rdmsrl(MSR_IA32_APICBASE
, msr
);
1555 if (msr
& X2APIC_ENABLE
)
1557 wrmsrl(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
);
1558 printk_once(KERN_INFO
"x2apic enabled\n");
1561 static int __init
setup_nox2apic(char *str
)
1563 if (x2apic_enabled()) {
1564 int apicid
= native_apic_msr_read(APIC_ID
);
1566 if (apicid
>= 255) {
1567 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1571 pr_warning("x2apic already enabled.\n");
1574 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
1575 x2apic_state
= X2APIC_DISABLED
;
1579 early_param("nox2apic", setup_nox2apic
);
1581 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1582 void x2apic_setup(void)
1585 * If x2apic is not in ON state, disable it if already enabled
1588 if (x2apic_state
!= X2APIC_ON
) {
1595 static __init
void x2apic_disable(void)
1597 u32 x2apic_id
, state
= x2apic_state
;
1600 x2apic_state
= X2APIC_DISABLED
;
1602 if (state
!= X2APIC_ON
)
1605 x2apic_id
= read_apic_id();
1606 if (x2apic_id
>= 255)
1607 panic("Cannot disable x2apic, id: %08x\n", x2apic_id
);
1610 register_lapic_address(mp_lapic_addr
);
1613 static __init
void x2apic_enable(void)
1615 if (x2apic_state
!= X2APIC_OFF
)
1619 x2apic_state
= X2APIC_ON
;
1623 static __init
void try_to_enable_x2apic(int remap_mode
)
1625 if (x2apic_state
== X2APIC_DISABLED
)
1628 if (remap_mode
!= IRQ_REMAP_X2APIC_MODE
) {
1629 /* IR is required if there is APIC ID > 255 even when running
1632 if (max_physical_apicid
> 255 ||
1633 !hypervisor_x2apic_available()) {
1634 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1640 * without IR all CPUs can be addressed by IOAPIC/MSI
1641 * only in physical mode
1648 void __init
check_x2apic(void)
1650 if (x2apic_enabled()) {
1651 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1653 x2apic_state
= X2APIC_ON
;
1654 } else if (!boot_cpu_has(X86_FEATURE_X2APIC
)) {
1655 x2apic_state
= X2APIC_DISABLED
;
1658 #else /* CONFIG_X86_X2APIC */
1659 static int __init
validate_x2apic(void)
1661 if (!apic_is_x2apic_enabled())
1664 * Checkme: Can we simply turn off x2apic here instead of panic?
1666 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1668 early_initcall(validate_x2apic
);
1670 static inline void try_to_enable_x2apic(int remap_mode
) { }
1671 static inline void __x2apic_enable(void) { }
1672 #endif /* !CONFIG_X86_X2APIC */
1674 void __init
enable_IR_x2apic(void)
1676 unsigned long flags
;
1679 if (skip_ioapic_setup
) {
1680 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1684 ir_stat
= irq_remapping_prepare();
1685 if (ir_stat
< 0 && !x2apic_supported())
1688 ret
= save_ioapic_entries();
1690 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1694 local_irq_save(flags
);
1695 legacy_pic
->mask_all();
1696 mask_ioapic_entries();
1698 /* If irq_remapping_prepare() succeeded, try to enable it */
1700 ir_stat
= irq_remapping_enable();
1701 /* ir_stat contains the remap mode or an error code */
1702 try_to_enable_x2apic(ir_stat
);
1705 restore_ioapic_entries();
1706 legacy_pic
->restore_mask();
1707 local_irq_restore(flags
);
1710 #ifdef CONFIG_X86_64
1712 * Detect and enable local APICs on non-SMP boards.
1713 * Original code written by Keir Fraser.
1714 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1715 * not correctly set up (usually the APIC timer won't work etc.)
1717 static int __init
detect_init_APIC(void)
1719 if (!boot_cpu_has(X86_FEATURE_APIC
)) {
1720 pr_info("No local APIC present\n");
1724 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1729 static int __init
apic_verify(void)
1734 * The APIC feature bit should now be enabled
1737 features
= cpuid_edx(1);
1738 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1739 pr_warning("Could not enable APIC!\n");
1742 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1743 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1745 /* The BIOS may have set up the APIC at some other address */
1746 if (boot_cpu_data
.x86
>= 6) {
1747 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1748 if (l
& MSR_IA32_APICBASE_ENABLE
)
1749 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1752 pr_info("Found and enabled local APIC!\n");
1756 int __init
apic_force_enable(unsigned long addr
)
1764 * Some BIOSes disable the local APIC in the APIC_BASE
1765 * MSR. This can only be done in software for Intel P6 or later
1766 * and AMD K7 (Model > 1) or later.
1768 if (boot_cpu_data
.x86
>= 6) {
1769 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1770 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1771 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1772 l
&= ~MSR_IA32_APICBASE_BASE
;
1773 l
|= MSR_IA32_APICBASE_ENABLE
| addr
;
1774 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1775 enabled_via_apicbase
= 1;
1778 return apic_verify();
1782 * Detect and initialize APIC
1784 static int __init
detect_init_APIC(void)
1786 /* Disabled by kernel option? */
1790 switch (boot_cpu_data
.x86_vendor
) {
1791 case X86_VENDOR_AMD
:
1792 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1793 (boot_cpu_data
.x86
>= 15))
1796 case X86_VENDOR_INTEL
:
1797 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1798 (boot_cpu_data
.x86
== 5 && boot_cpu_has(X86_FEATURE_APIC
)))
1805 if (!boot_cpu_has(X86_FEATURE_APIC
)) {
1807 * Over-ride BIOS and try to enable the local APIC only if
1808 * "lapic" specified.
1810 if (!force_enable_local_apic
) {
1811 pr_info("Local APIC disabled by BIOS -- "
1812 "you can enable it with \"lapic\"\n");
1815 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE
))
1827 pr_info("No local APIC present or hardware disabled\n");
1833 * init_apic_mappings - initialize APIC mappings
1835 void __init
init_apic_mappings(void)
1837 unsigned int new_apicid
;
1839 apic_check_deadline_errata();
1842 boot_cpu_physical_apicid
= read_apic_id();
1846 /* If no local APIC can be found return early */
1847 if (!smp_found_config
&& detect_init_APIC()) {
1848 /* lets NOP'ify apic operations */
1849 pr_info("APIC: disable apic facility\n");
1852 apic_phys
= mp_lapic_addr
;
1855 * If the system has ACPI MADT tables or MP info, the LAPIC
1856 * address is already registered.
1858 if (!acpi_lapic
&& !smp_found_config
)
1859 register_lapic_address(apic_phys
);
1863 * Fetch the APIC ID of the BSP in case we have a
1864 * default configuration (or the MP table is broken).
1866 new_apicid
= read_apic_id();
1867 if (boot_cpu_physical_apicid
!= new_apicid
) {
1868 boot_cpu_physical_apicid
= new_apicid
;
1870 * yeah -- we lie about apic_version
1871 * in case if apic was disabled via boot option
1872 * but it's not a problem for SMP compiled kernel
1873 * since smp_sanity_check is prepared for such a case
1874 * and disable smp mode
1876 boot_cpu_apic_version
= GET_APIC_VERSION(apic_read(APIC_LVR
));
1880 void __init
register_lapic_address(unsigned long address
)
1882 mp_lapic_addr
= address
;
1885 set_fixmap_nocache(FIX_APIC_BASE
, address
);
1886 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1887 APIC_BASE
, address
);
1889 if (boot_cpu_physical_apicid
== -1U) {
1890 boot_cpu_physical_apicid
= read_apic_id();
1891 boot_cpu_apic_version
= GET_APIC_VERSION(apic_read(APIC_LVR
));
1896 * Local APIC interrupts
1900 * This interrupt should _never_ happen with our APIC/SMP architecture
1902 static void __smp_spurious_interrupt(u8 vector
)
1907 * Check if this really is a spurious interrupt and ACK it
1908 * if it is a vectored one. Just in case...
1909 * Spurious interrupts should not be ACKed.
1911 v
= apic_read(APIC_ISR
+ ((vector
& ~0x1f) >> 1));
1912 if (v
& (1 << (vector
& 0x1f)))
1915 inc_irq_stat(irq_spurious_count
);
1917 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1918 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
1919 "should never happen.\n", vector
, smp_processor_id());
1922 __visible
void __irq_entry
smp_spurious_interrupt(struct pt_regs
*regs
)
1925 __smp_spurious_interrupt(~regs
->orig_ax
);
1929 __visible
void __irq_entry
smp_trace_spurious_interrupt(struct pt_regs
*regs
)
1931 u8 vector
= ~regs
->orig_ax
;
1934 trace_spurious_apic_entry(vector
);
1935 __smp_spurious_interrupt(vector
);
1936 trace_spurious_apic_exit(vector
);
1941 * This interrupt should never happen with our APIC/SMP architecture
1943 static void __smp_error_interrupt(struct pt_regs
*regs
)
1947 static const char * const error_interrupt_reason
[] = {
1948 "Send CS error", /* APIC Error Bit 0 */
1949 "Receive CS error", /* APIC Error Bit 1 */
1950 "Send accept error", /* APIC Error Bit 2 */
1951 "Receive accept error", /* APIC Error Bit 3 */
1952 "Redirectable IPI", /* APIC Error Bit 4 */
1953 "Send illegal vector", /* APIC Error Bit 5 */
1954 "Received illegal vector", /* APIC Error Bit 6 */
1955 "Illegal register address", /* APIC Error Bit 7 */
1958 /* First tickle the hardware, only then report what went on. -- REW */
1959 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1960 apic_write(APIC_ESR
, 0);
1961 v
= apic_read(APIC_ESR
);
1963 atomic_inc(&irq_err_count
);
1965 apic_printk(APIC_DEBUG
, KERN_DEBUG
"APIC error on CPU%d: %02x",
1966 smp_processor_id(), v
);
1971 apic_printk(APIC_DEBUG
, KERN_CONT
" : %s", error_interrupt_reason
[i
]);
1976 apic_printk(APIC_DEBUG
, KERN_CONT
"\n");
1980 __visible
void __irq_entry
smp_error_interrupt(struct pt_regs
*regs
)
1983 __smp_error_interrupt(regs
);
1987 __visible
void __irq_entry
smp_trace_error_interrupt(struct pt_regs
*regs
)
1990 trace_error_apic_entry(ERROR_APIC_VECTOR
);
1991 __smp_error_interrupt(regs
);
1992 trace_error_apic_exit(ERROR_APIC_VECTOR
);
1997 * connect_bsp_APIC - attach the APIC to the interrupt system
1999 static void __init
connect_bsp_APIC(void)
2001 #ifdef CONFIG_X86_32
2004 * Do not trust the local APIC being empty at bootup.
2008 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2009 * local APIC to INT and NMI lines.
2011 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
2012 "enabling APIC mode.\n");
2019 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2020 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2022 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2025 void disconnect_bsp_APIC(int virt_wire_setup
)
2029 #ifdef CONFIG_X86_32
2032 * Put the board back into PIC mode (has an effect only on
2033 * certain older boards). Note that APIC interrupts, including
2034 * IPIs, won't work beyond this point! The only exception are
2037 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
2038 "entering PIC mode.\n");
2044 /* Go back to Virtual Wire compatibility mode */
2046 /* For the spurious interrupt use vector F, and enable it */
2047 value
= apic_read(APIC_SPIV
);
2048 value
&= ~APIC_VECTOR_MASK
;
2049 value
|= APIC_SPIV_APIC_ENABLED
;
2051 apic_write(APIC_SPIV
, value
);
2053 if (!virt_wire_setup
) {
2055 * For LVT0 make it edge triggered, active high,
2056 * external and enabled
2058 value
= apic_read(APIC_LVT0
);
2059 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
2060 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
2061 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
2062 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
2063 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
2064 apic_write(APIC_LVT0
, value
);
2067 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
2071 * For LVT1 make it edge triggered, active high,
2074 value
= apic_read(APIC_LVT1
);
2075 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
2076 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
2077 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
2078 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
2079 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
2080 apic_write(APIC_LVT1
, value
);
2084 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2085 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2086 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2087 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2089 * NOTE: Reserve 0 for BSP.
2091 static int nr_logical_cpuids
= 1;
2094 * Used to store mapping between logical CPU IDs and APIC IDs.
2096 static int cpuid_to_apicid
[] = {
2097 [0 ... NR_CPUS
- 1] = -1,
2101 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2102 * and cpuid_to_apicid[] synchronized.
2104 static int allocate_logical_cpuid(int apicid
)
2109 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2110 * check if the kernel has allocated a cpuid for it.
2112 for (i
= 0; i
< nr_logical_cpuids
; i
++) {
2113 if (cpuid_to_apicid
[i
] == apicid
)
2117 /* Allocate a new cpuid. */
2118 if (nr_logical_cpuids
>= nr_cpu_ids
) {
2119 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %i reached. "
2120 "Processor %d/0x%x and the rest are ignored.\n",
2121 nr_cpu_ids
, nr_logical_cpuids
, apicid
);
2125 cpuid_to_apicid
[nr_logical_cpuids
] = apicid
;
2126 return nr_logical_cpuids
++;
2129 int generic_processor_info(int apicid
, int version
)
2131 int cpu
, max
= nr_cpu_ids
;
2132 bool boot_cpu_detected
= physid_isset(boot_cpu_physical_apicid
,
2133 phys_cpu_present_map
);
2136 * boot_cpu_physical_apicid is designed to have the apicid
2137 * returned by read_apic_id(), i.e, the apicid of the
2138 * currently booting-up processor. However, on some platforms,
2139 * it is temporarily modified by the apicid reported as BSP
2140 * through MP table. Concretely:
2142 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2143 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2145 * This function is executed with the modified
2146 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2147 * parameter doesn't work to disable APs on kdump 2nd kernel.
2149 * Since fixing handling of boot_cpu_physical_apicid requires
2150 * another discussion and tests on each platform, we leave it
2151 * for now and here we use read_apic_id() directly in this
2152 * function, __generic_processor_info().
2154 if (disabled_cpu_apicid
!= BAD_APICID
&&
2155 disabled_cpu_apicid
!= read_apic_id() &&
2156 disabled_cpu_apicid
== apicid
) {
2157 int thiscpu
= num_processors
+ disabled_cpus
;
2159 pr_warning("APIC: Disabling requested cpu."
2160 " Processor %d/0x%x ignored.\n",
2168 * If boot cpu has not been detected yet, then only allow upto
2169 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2171 if (!boot_cpu_detected
&& num_processors
>= nr_cpu_ids
- 1 &&
2172 apicid
!= boot_cpu_physical_apicid
) {
2173 int thiscpu
= max
+ disabled_cpus
- 1;
2176 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2177 " reached. Keeping one slot for boot cpu."
2178 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
2184 if (num_processors
>= nr_cpu_ids
) {
2185 int thiscpu
= max
+ disabled_cpus
;
2187 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2188 "reached. Processor %d/0x%x ignored.\n",
2189 max
, thiscpu
, apicid
);
2195 if (apicid
== boot_cpu_physical_apicid
) {
2197 * x86_bios_cpu_apicid is required to have processors listed
2198 * in same order as logical cpu numbers. Hence the first
2199 * entry is BSP, and so on.
2200 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2205 /* Logical cpuid 0 is reserved for BSP. */
2206 cpuid_to_apicid
[0] = apicid
;
2208 cpu
= allocate_logical_cpuid(apicid
);
2218 if (version
== 0x0) {
2219 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2224 if (version
!= boot_cpu_apic_version
) {
2225 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2226 boot_cpu_apic_version
, cpu
, version
);
2229 if (apicid
> max_physical_apicid
)
2230 max_physical_apicid
= apicid
;
2232 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2233 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
2234 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
2236 #ifdef CONFIG_X86_32
2237 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) =
2238 apic
->x86_32_early_logical_apicid(cpu
);
2240 set_cpu_possible(cpu
, true);
2241 physid_set(apicid
, phys_cpu_present_map
);
2242 set_cpu_present(cpu
, true);
2248 int hard_smp_processor_id(void)
2250 return read_apic_id();
2253 void default_init_apic_ldr(void)
2257 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
2258 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
2259 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2260 apic_write(APIC_LDR
, val
);
2263 int default_cpu_mask_to_apicid(const struct cpumask
*mask
,
2264 struct irq_data
*irqdata
,
2265 unsigned int *apicid
)
2267 unsigned int cpu
= cpumask_first(mask
);
2269 if (cpu
>= nr_cpu_ids
)
2271 *apicid
= per_cpu(x86_cpu_to_apicid
, cpu
);
2272 irq_data_update_effective_affinity(irqdata
, cpumask_of(cpu
));
2276 int flat_cpu_mask_to_apicid(const struct cpumask
*mask
,
2277 struct irq_data
*irqdata
,
2278 unsigned int *apicid
)
2281 struct cpumask
*effmsk
= irq_data_get_effective_affinity_mask(irqdata
);
2282 unsigned long cpu_mask
= cpumask_bits(mask
)[0] & APIC_ALL_CPUS
;
2286 *apicid
= (unsigned int)cpu_mask
;
2287 cpumask_bits(effmsk
)[0] = cpu_mask
;
2292 * Override the generic EOI implementation with an optimized version.
2293 * Only called during early boot when only one CPU is active and with
2294 * interrupts disabled, so we know this does not race with actual APIC driver
2297 void __init
apic_set_eoi_write(void (*eoi_write
)(u32 reg
, u32 v
))
2301 for (drv
= __apicdrivers
; drv
< __apicdrivers_end
; drv
++) {
2302 /* Should happen once for each apic */
2303 WARN_ON((*drv
)->eoi_write
== eoi_write
);
2304 (*drv
)->native_eoi_write
= (*drv
)->eoi_write
;
2305 (*drv
)->eoi_write
= eoi_write
;
2309 static void __init
apic_bsp_up_setup(void)
2311 #ifdef CONFIG_X86_64
2312 apic_write(APIC_ID
, apic
->set_apic_id(boot_cpu_physical_apicid
));
2315 * Hack: In case of kdump, after a crash, kernel might be booting
2316 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2317 * might be zero if read from MP tables. Get it from LAPIC.
2319 # ifdef CONFIG_CRASH_DUMP
2320 boot_cpu_physical_apicid
= read_apic_id();
2323 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
2327 * apic_bsp_setup - Setup function for local apic and io-apic
2328 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2331 * apic_id of BSP APIC
2333 int __init
apic_bsp_setup(bool upmode
)
2339 apic_bsp_up_setup();
2343 id
= apic_read(APIC_LDR
);
2345 id
= GET_APIC_LOGICAL_ID(apic_read(APIC_LDR
));
2348 end_local_APIC_setup();
2349 irq_remap_enable_fault_handling();
2351 /* Setup local timer */
2352 x86_init
.timers
.setup_percpu_clockev();
2357 * This initializes the IO-APIC and APIC hardware if this is
2360 int __init
APIC_init_uniprocessor(void)
2363 pr_info("Apic disabled\n");
2366 #ifdef CONFIG_X86_64
2367 if (!boot_cpu_has(X86_FEATURE_APIC
)) {
2369 pr_info("Apic disabled by BIOS\n");
2373 if (!smp_found_config
&& !boot_cpu_has(X86_FEATURE_APIC
))
2377 * Complain if the BIOS pretends there is one.
2379 if (!boot_cpu_has(X86_FEATURE_APIC
) &&
2380 APIC_INTEGRATED(boot_cpu_apic_version
)) {
2381 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2382 boot_cpu_physical_apicid
);
2387 if (!smp_found_config
)
2388 disable_ioapic_support();
2390 default_setup_apic_routing();
2391 apic_bsp_setup(true);
2395 #ifdef CONFIG_UP_LATE_INIT
2396 void __init
up_late_init(void)
2398 APIC_init_uniprocessor();
2409 * 'active' is true if the local APIC was enabled by us and
2410 * not the BIOS; this signifies that we are also responsible
2411 * for disabling it before entering apm/acpi suspend
2414 /* r/w apic fields */
2415 unsigned int apic_id
;
2416 unsigned int apic_taskpri
;
2417 unsigned int apic_ldr
;
2418 unsigned int apic_dfr
;
2419 unsigned int apic_spiv
;
2420 unsigned int apic_lvtt
;
2421 unsigned int apic_lvtpc
;
2422 unsigned int apic_lvt0
;
2423 unsigned int apic_lvt1
;
2424 unsigned int apic_lvterr
;
2425 unsigned int apic_tmict
;
2426 unsigned int apic_tdcr
;
2427 unsigned int apic_thmr
;
2428 unsigned int apic_cmci
;
2431 static int lapic_suspend(void)
2433 unsigned long flags
;
2436 if (!apic_pm_state
.active
)
2439 maxlvt
= lapic_get_maxlvt();
2441 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
2442 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
2443 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
2444 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
2445 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
2446 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
2448 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
2449 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2450 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2451 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2452 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2453 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2454 #ifdef CONFIG_X86_THERMAL_VECTOR
2456 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2458 #ifdef CONFIG_X86_MCE_INTEL
2460 apic_pm_state
.apic_cmci
= apic_read(APIC_LVTCMCI
);
2463 local_irq_save(flags
);
2464 disable_local_APIC();
2466 irq_remapping_disable();
2468 local_irq_restore(flags
);
2472 static void lapic_resume(void)
2475 unsigned long flags
;
2478 if (!apic_pm_state
.active
)
2481 local_irq_save(flags
);
2484 * IO-APIC and PIC have their own resume routines.
2485 * We just mask them here to make sure the interrupt
2486 * subsystem is completely quiet while we enable x2apic
2487 * and interrupt-remapping.
2489 mask_ioapic_entries();
2490 legacy_pic
->mask_all();
2496 * Make sure the APICBASE points to the right address
2498 * FIXME! This will be wrong if we ever support suspend on
2499 * SMP! We'll need to do this as part of the CPU restore!
2501 if (boot_cpu_data
.x86
>= 6) {
2502 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2503 l
&= ~MSR_IA32_APICBASE_BASE
;
2504 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2505 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2509 maxlvt
= lapic_get_maxlvt();
2510 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2511 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2512 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2513 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2514 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2515 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2516 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2517 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2518 #ifdef CONFIG_X86_THERMAL_VECTOR
2520 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2522 #ifdef CONFIG_X86_MCE_INTEL
2524 apic_write(APIC_LVTCMCI
, apic_pm_state
.apic_cmci
);
2527 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2528 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2529 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2530 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2531 apic_write(APIC_ESR
, 0);
2532 apic_read(APIC_ESR
);
2533 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2534 apic_write(APIC_ESR
, 0);
2535 apic_read(APIC_ESR
);
2537 irq_remapping_reenable(x2apic_mode
);
2539 local_irq_restore(flags
);
2543 * This device has no shutdown method - fully functioning local APICs
2544 * are needed on every CPU up until machine_halt/restart/poweroff.
2547 static struct syscore_ops lapic_syscore_ops
= {
2548 .resume
= lapic_resume
,
2549 .suspend
= lapic_suspend
,
2552 static void apic_pm_activate(void)
2554 apic_pm_state
.active
= 1;
2557 static int __init
init_lapic_sysfs(void)
2559 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2560 if (boot_cpu_has(X86_FEATURE_APIC
))
2561 register_syscore_ops(&lapic_syscore_ops
);
2566 /* local apic needs to resume before other devices access its registers. */
2567 core_initcall(init_lapic_sysfs
);
2569 #else /* CONFIG_PM */
2571 static void apic_pm_activate(void) { }
2573 #endif /* CONFIG_PM */
2575 #ifdef CONFIG_X86_64
2577 static int multi_checked
;
2580 static int set_multi(const struct dmi_system_id
*d
)
2584 pr_info("APIC: %s detected, Multi Chassis\n", d
->ident
);
2589 static const struct dmi_system_id multi_dmi_table
[] = {
2591 .callback
= set_multi
,
2592 .ident
= "IBM System Summit2",
2594 DMI_MATCH(DMI_SYS_VENDOR
, "IBM"),
2595 DMI_MATCH(DMI_PRODUCT_NAME
, "Summit2"),
2601 static void dmi_check_multi(void)
2606 dmi_check_system(multi_dmi_table
);
2611 * apic_is_clustered_box() -- Check if we can expect good TSC
2613 * Thus far, the major user of this is IBM's Summit2 series:
2614 * Clustered boxes may have unsynced TSC problems if they are
2616 * Use DMI to check them
2618 int apic_is_clustered_box(void)
2626 * APIC command line parameters
2628 static int __init
setup_disableapic(char *arg
)
2631 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2634 early_param("disableapic", setup_disableapic
);
2636 /* same as disableapic, for compatibility */
2637 static int __init
setup_nolapic(char *arg
)
2639 return setup_disableapic(arg
);
2641 early_param("nolapic", setup_nolapic
);
2643 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2645 local_apic_timer_c2_ok
= 1;
2648 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2650 static int __init
parse_disable_apic_timer(char *arg
)
2652 disable_apic_timer
= 1;
2655 early_param("noapictimer", parse_disable_apic_timer
);
2657 static int __init
parse_nolapic_timer(char *arg
)
2659 disable_apic_timer
= 1;
2662 early_param("nolapic_timer", parse_nolapic_timer
);
2664 static int __init
apic_set_verbosity(char *arg
)
2667 #ifdef CONFIG_X86_64
2668 skip_ioapic_setup
= 0;
2674 if (strcmp("debug", arg
) == 0)
2675 apic_verbosity
= APIC_DEBUG
;
2676 else if (strcmp("verbose", arg
) == 0)
2677 apic_verbosity
= APIC_VERBOSE
;
2679 pr_warning("APIC Verbosity level %s not recognised"
2680 " use apic=verbose or apic=debug\n", arg
);
2686 early_param("apic", apic_set_verbosity
);
2688 static int __init
lapic_insert_resource(void)
2693 /* Put local APIC into the resource map. */
2694 lapic_resource
.start
= apic_phys
;
2695 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2696 insert_resource(&iomem_resource
, &lapic_resource
);
2702 * need call insert after e820__reserve_resources()
2703 * that is using request_resource
2705 late_initcall(lapic_insert_resource
);
2707 static int __init
apic_set_disabled_cpu_apicid(char *arg
)
2709 if (!arg
|| !get_option(&arg
, &disabled_cpu_apicid
))
2714 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid
);
2716 static int __init
apic_set_extnmi(char *arg
)
2721 if (!strncmp("all", arg
, 3))
2722 apic_extnmi
= APIC_EXTNMI_ALL
;
2723 else if (!strncmp("none", arg
, 4))
2724 apic_extnmi
= APIC_EXTNMI_NONE
;
2725 else if (!strncmp("bsp", arg
, 3))
2726 apic_extnmi
= APIC_EXTNMI_BSP
;
2728 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg
);
2734 early_param("apic_extnmi", apic_set_extnmi
);