arch/x86/kernel/cpu/perf_event_intel_ds.c

   1 #ifdef CONFIG_CPU_SUP_INTEL
   2
   3 /* The maximal number of PEBS events: */
   4 #define MAX_PEBS_EVENTS         4
   5
   6 /* The size of a BTS record in bytes: */
   7 #define BTS_RECORD_SIZE         24
   8
   9 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
  10 #define PEBS_BUFFER_SIZE        PAGE_SIZE
  11
  12 /*
  13  * pebs_record_32 for p4 and core not supported
  14
  15 struct pebs_record_32 {
  16         u32 flags, ip;
  17         u32 ax, bc, cx, dx;
  18         u32 si, di, bp, sp;
  19 };
  20
  21  */
  22
  23 struct pebs_record_core {
  24         u64 flags, ip;
  25         u64 ax, bx, cx, dx;
  26         u64 si, di, bp, sp;
  27         u64 r8,  r9,  r10, r11;
  28         u64 r12, r13, r14, r15;
  29 };
  30
  31 struct pebs_record_nhm {
  32         u64 flags, ip;
  33         u64 ax, bx, cx, dx;
  34         u64 si, di, bp, sp;
  35         u64 r8,  r9,  r10, r11;
  36         u64 r12, r13, r14, r15;
  37         u64 status, dla, dse, lat;
  38 };
  39
  40 /*
  41  * Bits in the debugctlmsr controlling branch tracing.
  42  */
  43 #define X86_DEBUGCTL_TR                 (1 << 6)
  44 #define X86_DEBUGCTL_BTS                (1 << 7)
  45 #define X86_DEBUGCTL_BTINT              (1 << 8)
  46 #define X86_DEBUGCTL_BTS_OFF_OS         (1 << 9)
  47 #define X86_DEBUGCTL_BTS_OFF_USR        (1 << 10)
  48
  49 /*
  50  * A debug store configuration.
  51  *
  52  * We only support architectures that use 64bit fields.
  53  */
  54 struct debug_store {
  55         u64     bts_buffer_base;
  56         u64     bts_index;
  57         u64     bts_absolute_maximum;
  58         u64     bts_interrupt_threshold;
  59         u64     pebs_buffer_base;
  60         u64     pebs_index;
  61         u64     pebs_absolute_maximum;
  62         u64     pebs_interrupt_threshold;
  63         u64     pebs_event_reset[MAX_PEBS_EVENTS];
  64 };
  65
  66 static void init_debug_store_on_cpu(int cpu)
  67 {
  68         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
  69
  70         if (!ds)
  71                 return;
  72
  73         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
  74                      (u32)((u64)(unsigned long)ds),
  75                      (u32)((u64)(unsigned long)ds >> 32));
  76 }
  77
  78 static void fini_debug_store_on_cpu(int cpu)
  79 {
  80         if (!per_cpu(cpu_hw_events, cpu).ds)
  81                 return;
  82
  83         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
  84 }
  85
  86 static void release_ds_buffers(void)
  87 {
  88         int cpu;
  89
  90         if (!x86_pmu.bts && !x86_pmu.pebs)
  91                 return;
  92
  93         get_online_cpus();
  94
  95         for_each_online_cpu(cpu)
  96                 fini_debug_store_on_cpu(cpu);
  97
  98         for_each_possible_cpu(cpu) {
  99                 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 100
 101                 if (!ds)
 102                         continue;
 103
 104                 per_cpu(cpu_hw_events, cpu).ds = NULL;
 105
 106                 kfree((void *)(unsigned long)ds->pebs_buffer_base);
 107                 kfree((void *)(unsigned long)ds->bts_buffer_base);
 108                 kfree(ds);
 109         }
 110
 111         put_online_cpus();
 112 }
 113
 114 static int reserve_ds_buffers(void)
 115 {
 116         int cpu, err = 0;
 117
 118         if (!x86_pmu.bts && !x86_pmu.pebs)
 119                 return 0;
 120
 121         get_online_cpus();
 122
 123         for_each_possible_cpu(cpu) {
 124                 struct debug_store *ds;
 125                 void *buffer;
 126                 int max, thresh;
 127
 128                 err = -ENOMEM;
 129                 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
 130                 if (unlikely(!ds))
 131                         break;
 132                 per_cpu(cpu_hw_events, cpu).ds = ds;
 133
 134                 if (x86_pmu.bts) {
 135                         buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
 136                         if (unlikely(!buffer))
 137                                 break;
 138
 139                         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 140                         thresh = max / 16;
 141
 142                         ds->bts_buffer_base = (u64)(unsigned long)buffer;
 143                         ds->bts_index = ds->bts_buffer_base;
 144                         ds->bts_absolute_maximum = ds->bts_buffer_base +
 145                                 max * BTS_RECORD_SIZE;
 146                         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 147                                 thresh * BTS_RECORD_SIZE;
 148                 }
 149
 150                 if (x86_pmu.pebs) {
 151                         buffer = kzalloc(PEBS_BUFFER_SIZE, GFP_KERNEL);
 152                         if (unlikely(!buffer))
 153                                 break;
 154
 155                         max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
 156
 157                         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
 158                         ds->pebs_index = ds->pebs_buffer_base;
 159                         ds->pebs_absolute_maximum = ds->pebs_buffer_base +
 160                                 max * x86_pmu.pebs_record_size;
 161                         /*
 162                          * Always use single record PEBS
 163                          */
 164                         ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
 165                                 x86_pmu.pebs_record_size;
 166                 }
 167
 168                 err = 0;
 169         }
 170
 171         if (err)
 172                 release_ds_buffers();
 173         else {
 174                 for_each_online_cpu(cpu)
 175                         init_debug_store_on_cpu(cpu);
 176         }
 177
 178         put_online_cpus();
 179
 180         return err;
 181 }
 182
 183 /*
 184  * BTS
 185  */
 186
 187 static struct event_constraint bts_constraint =
 188         EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
 189
 190 static void intel_pmu_enable_bts(u64 config)
 191 {
 192         unsigned long debugctlmsr;
 193
 194         debugctlmsr = get_debugctlmsr();
 195
 196         debugctlmsr |= X86_DEBUGCTL_TR;
 197         debugctlmsr |= X86_DEBUGCTL_BTS;
 198         debugctlmsr |= X86_DEBUGCTL_BTINT;
 199
 200         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 201                 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
 202
 203         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 204                 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
 205
 206         update_debugctlmsr(debugctlmsr);
 207 }
 208
 209 static void intel_pmu_disable_bts(void)
 210 {
 211         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 212         unsigned long debugctlmsr;
 213
 214         if (!cpuc->ds)
 215                 return;
 216
 217         debugctlmsr = get_debugctlmsr();
 218
 219         debugctlmsr &=
 220                 ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
 221                   X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
 222
 223         update_debugctlmsr(debugctlmsr);
 224 }
 225
 226 static void intel_pmu_drain_bts_buffer(void)
 227 {
 228         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 229         struct debug_store *ds = cpuc->ds;
 230         struct bts_record {
 231                 u64     from;
 232                 u64     to;
 233                 u64     flags;
 234         };
 235         struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
 236         struct bts_record *at, *top;
 237         struct perf_output_handle handle;
 238         struct perf_event_header header;
 239         struct perf_sample_data data;
 240         struct pt_regs regs;
 241
 242         if (!event)
 243                 return;
 244
 245         if (!ds)
 246                 return;
 247
 248         at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 249         top = (struct bts_record *)(unsigned long)ds->bts_index;
 250
 251         if (top <= at)
 252                 return;
 253
 254         ds->bts_index = ds->bts_buffer_base;
 255
 256         perf_sample_data_init(&data, 0);
 257         data.period = event->hw.last_period;
 258         regs.ip     = 0;
 259
 260         /*
 261          * Prepare a generic sample, i.e. fill in the invariant fields.
 262          * We will overwrite the from and to address before we output
 263          * the sample.
 264          */
 265         perf_prepare_sample(&header, &data, event, &regs);
 266
 267         if (perf_output_begin(&handle, event, header.size * (top - at), 1, 1))
 268                 return;
 269
 270         for (; at < top; at++) {
 271                 data.ip         = at->from;
 272                 data.addr       = at->to;
 273
 274                 perf_output_sample(&handle, &header, &data, event);
 275         }
 276
 277         perf_output_end(&handle);
 278
 279         /* There's new data available. */
 280         event->hw.interrupts++;
 281         event->pending_kill = POLL_IN;
 282 }
 283
 284 /*
 285  * PEBS
 286  */
 287
 288 static struct event_constraint intel_core_pebs_events[] = {
 289         PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */
 290         PEBS_EVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 291         PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 292         PEBS_EVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 293         PEBS_EVENT_CONSTRAINT(0x01cb, 0x1), /* MEM_LOAD_RETIRED.L1D_MISS */
 294         PEBS_EVENT_CONSTRAINT(0x02cb, 0x1), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
 295         PEBS_EVENT_CONSTRAINT(0x04cb, 0x1), /* MEM_LOAD_RETIRED.L2_MISS */
 296         PEBS_EVENT_CONSTRAINT(0x08cb, 0x1), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
 297         PEBS_EVENT_CONSTRAINT(0x10cb, 0x1), /* MEM_LOAD_RETIRED.DTLB_MISS */
 298         EVENT_CONSTRAINT_END
 299 };
 300
 301 static struct event_constraint intel_nehalem_pebs_events[] = {
 302         PEBS_EVENT_CONSTRAINT(0x00c0, 0xf), /* INSTR_RETIRED.ANY */
 303         PEBS_EVENT_CONSTRAINT(0xfec1, 0xf), /* X87_OPS_RETIRED.ANY */
 304         PEBS_EVENT_CONSTRAINT(0x00c5, 0xf), /* BR_INST_RETIRED.MISPRED */
 305         PEBS_EVENT_CONSTRAINT(0x1fc7, 0xf), /* SIMD_INST_RETURED.ANY */
 306         PEBS_EVENT_CONSTRAINT(0x01cb, 0xf), /* MEM_LOAD_RETIRED.L1D_MISS */
 307         PEBS_EVENT_CONSTRAINT(0x02cb, 0xf), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
 308         PEBS_EVENT_CONSTRAINT(0x04cb, 0xf), /* MEM_LOAD_RETIRED.L2_MISS */
 309         PEBS_EVENT_CONSTRAINT(0x08cb, 0xf), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
 310         PEBS_EVENT_CONSTRAINT(0x10cb, 0xf), /* MEM_LOAD_RETIRED.DTLB_MISS */
 311         EVENT_CONSTRAINT_END
 312 };
 313
 314 static struct event_constraint *
 315 intel_pebs_constraints(struct perf_event *event)
 316 {
 317         struct event_constraint *c;
 318
 319         if (!event->attr.precise)
 320                 return NULL;
 321
 322         if (x86_pmu.pebs_constraints) {
 323                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 324                         if ((event->hw.config & c->cmask) == c->code)
 325                                 return c;
 326                 }
 327         }
 328
 329         return &emptyconstraint;
 330 }
 331
 332 static void intel_pmu_pebs_enable(struct perf_event *event)
 333 {
 334         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 335         struct hw_perf_event *hwc = &event->hw;
 336         u64 val = cpuc->pebs_enabled;
 337
 338         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 339
 340         val |= 1ULL << hwc->idx;
 341         wrmsrl(MSR_IA32_PEBS_ENABLE, val);
 342
 343         if (x86_pmu.intel_cap.pebs_trap)
 344                 intel_pmu_lbr_enable(event);
 345 }
 346
 347 static void intel_pmu_pebs_disable(struct perf_event *event)
 348 {
 349         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 350         struct hw_perf_event *hwc = &event->hw;
 351         u64 val = cpuc->pebs_enabled;
 352
 353         val &= ~(1ULL << hwc->idx);
 354         wrmsrl(MSR_IA32_PEBS_ENABLE, val);
 355
 356         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
 357
 358         if (x86_pmu.intel_cap.pebs_trap)
 359                 intel_pmu_lbr_disable(event);
 360 }
 361
 362 static void intel_pmu_pebs_enable_all(void)
 363 {
 364         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 365
 366         if (cpuc->pebs_enabled)
 367                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 368 }
 369
 370 static void intel_pmu_pebs_disable_all(void)
 371 {
 372         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 373
 374         if (cpuc->pebs_enabled)
 375                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 376 }
 377
 378 #include <asm/insn.h>
 379
 380 static inline bool kernel_ip(unsigned long ip)
 381 {
 382 #ifdef CONFIG_X86_32
 383         return ip > PAGE_OFFSET;
 384 #else
 385         return (long)ip < 0;
 386 #endif
 387 }
 388
 389 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 390 {
 391         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 392         unsigned long from = cpuc->lbr_entries[0].from;
 393         unsigned long old_to, to = cpuc->lbr_entries[0].to;
 394         unsigned long ip = regs->ip;
 395
 396         /*
 397          * We don't need to fixup if the PEBS assist is fault like
 398          */
 399         if (!x86_pmu.intel_cap.pebs_trap)
 400                 return 1;
 401
 402         /*
 403          * No LBR entry, no basic block, no rewinding
 404          */
 405         if (!cpuc->lbr_stack.nr || !from || !to)
 406                 return 0;
 407
 408         /*
 409          * Basic blocks should never cross user/kernel boundaries
 410          */
 411         if (kernel_ip(ip) != kernel_ip(to))
 412                 return 0;
 413
 414         /*
 415          * unsigned math, either ip is before the start (impossible) or
 416          * the basic block is larger than 1 page (sanity)
 417          */
 418         if ((ip - to) > PAGE_SIZE)
 419                 return 0;
 420
 421         /*
 422          * We sampled a branch insn, rewind using the LBR stack
 423          */
 424         if (ip == to) {
 425                 regs->ip = from;
 426                 return 1;
 427         }
 428
 429         do {
 430                 struct insn insn;
 431                 u8 buf[MAX_INSN_SIZE];
 432                 void *kaddr;
 433
 434                 old_to = to;
 435                 if (!kernel_ip(ip)) {
 436                         int bytes, size = MAX_INSN_SIZE;
 437
 438                         bytes = copy_from_user_nmi(buf, (void __user *)to, size);
 439                         if (bytes != size)
 440                                 return 0;
 441
 442                         kaddr = buf;
 443                 } else
 444                         kaddr = (void *)to;
 445
 446                 kernel_insn_init(&insn, kaddr);
 447                 insn_get_length(&insn);
 448                 to += insn.length;
 449         } while (to < ip);
 450
 451         if (to == ip) {
 452                 regs->ip = old_to;
 453                 return 1;
 454         }
 455
 456         /*
 457          * Even though we decoded the basic block, the instruction stream
 458          * never matched the given IP, either the TO or the IP got corrupted.
 459          */
 460         return 0;
 461 }
 462
 463 static int intel_pmu_save_and_restart(struct perf_event *event);
 464
 465 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
 466 {
 467         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 468         struct debug_store *ds = cpuc->ds;
 469         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
 470         struct pebs_record_core *at, *top;
 471         struct perf_sample_data data;
 472         struct perf_raw_record raw;
 473         struct pt_regs regs;
 474         int n;
 475
 476         if (!event || !ds || !x86_pmu.pebs)
 477                 return;
 478
 479         intel_pmu_pebs_disable_all();
 480
 481         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
 482         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
 483
 484         if (top <= at)
 485                 goto out;
 486
 487         ds->pebs_index = ds->pebs_buffer_base;
 488
 489         if (!intel_pmu_save_and_restart(event))
 490                 goto out;
 491
 492         perf_sample_data_init(&data, 0);
 493         data.period = event->hw.last_period;
 494
 495         if (event->attr.sample_type & PERF_SAMPLE_RAW) {
 496                 raw.size = x86_pmu.pebs_record_size;
 497                 raw.data = at;
 498                 data.raw = &raw;
 499         }
 500
 501         n = top - at;
 502
 503         /*
 504          * Should not happen, we program the threshold at 1 and do not
 505          * set a reset value.
 506          */
 507         WARN_ON_ONCE(n > 1);
 508
 509         /*
 510          * We use the interrupt regs as a base because the PEBS record
 511          * does not contain a full regs set, specifically it seems to
 512          * lack segment descriptors, which get used by things like
 513          * user_mode().
 514          *
 515          * In the simple case fix up only the IP and BP,SP regs, for
 516          * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
 517          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
 518          */
 519         regs = *iregs;
 520         regs.ip = at->ip;
 521         regs.bp = at->bp;
 522         regs.sp = at->sp;
 523
 524         if (intel_pmu_pebs_fixup_ip(&regs))
 525                 regs.flags |= PERF_EFLAGS_EXACT;
 526         else
 527                 regs.flags &= ~PERF_EFLAGS_EXACT;
 528
 529         if (perf_event_overflow(event, 1, &data, &regs))
 530                 x86_pmu_stop(event);
 531
 532 out:
 533         intel_pmu_pebs_enable_all();
 534 }
 535
 536 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
 537 {
 538         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 539         struct debug_store *ds = cpuc->ds;
 540         struct pebs_record_nhm *at, *top;
 541         struct perf_sample_data data;
 542         struct perf_event *event = NULL;
 543         struct perf_raw_record raw;
 544         struct pt_regs regs;
 545         int bit, n;
 546
 547         if (!ds || !x86_pmu.pebs)
 548                 return;
 549
 550         intel_pmu_pebs_disable_all();
 551
 552         at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
 553         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
 554
 555         if (top <= at)
 556                 goto out;
 557
 558         ds->pebs_index = ds->pebs_buffer_base;
 559
 560         n = top - at;
 561
 562         /*
 563          * Should not happen, we program the threshold at 1 and do not
 564          * set a reset value.
 565          */
 566         WARN_ON_ONCE(n > MAX_PEBS_EVENTS);
 567
 568         for ( ; at < top; at++) {
 569                 for_each_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) {
 570                         if (!cpuc->events[bit]->attr.precise)
 571                                 continue;
 572
 573                         event = cpuc->events[bit];
 574                 }
 575
 576                 if (!event)
 577                         continue;
 578
 579                 if (!intel_pmu_save_and_restart(event))
 580                         continue;
 581
 582                 perf_sample_data_init(&data, 0);
 583                 data.period = event->hw.last_period;
 584
 585                 if (event->attr.sample_type & PERF_SAMPLE_RAW) {
 586                         raw.size = x86_pmu.pebs_record_size;
 587                         raw.data = at;
 588                         data.raw = &raw;
 589                 }
 590
 591                 /*
 592                  * See the comment in intel_pmu_drain_pebs_core()
 593                  */
 594                 regs = *iregs;
 595                 regs.ip = at->ip;
 596                 regs.bp = at->bp;
 597                 regs.sp = at->sp;
 598
 599                 if (intel_pmu_pebs_fixup_ip(&regs))
 600                         regs.flags |= PERF_EFLAGS_EXACT;
 601                 else
 602                         regs.flags &= ~PERF_EFLAGS_EXACT;
 603
 604                 if (perf_event_overflow(event, 1, &data, &regs))
 605                         x86_pmu_stop(event);
 606         }
 607 out:
 608         intel_pmu_pebs_enable_all();
 609 }
 610
 611 /*
 612  * BTS, PEBS probe and setup
 613  */
 614
 615 static void intel_ds_init(void)
 616 {
 617         /*
 618          * No support for 32bit formats
 619          */
 620         if (!boot_cpu_has(X86_FEATURE_DTES64))
 621                 return;
 622
 623         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
 624         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
 625         if (x86_pmu.pebs) {
 626                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
 627                 int format = x86_pmu.intel_cap.pebs_format;
 628
 629                 switch (format) {
 630                 case 0:
 631                         printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
 632                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
 633                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
 634                         x86_pmu.pebs_constraints = intel_core_pebs_events;
 635                         break;
 636
 637                 case 1:
 638                         printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
 639                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
 640                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
 641                         x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
 642                         break;
 643
 644                 default:
 645                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
 646                         x86_pmu.pebs = 0;
 647                         break;
 648                 }
 649         }
 650 }
 651
 652 #else /* CONFIG_CPU_SUP_INTEL */
 653
 654 static int reseve_ds_buffers(void)
 655 {
 656         return 0;
 657 }
 658
 659 static void release_ds_buffers(void)
 660 {
 661 }
 662
 663 #endif /* CONFIG_CPU_SUP_INTEL */