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Merge branch 'kvm-updates/2.6.36' of git://git.kernel.org/pub/scm/virt/kvm/kvm
[linux-rapidio-2.6.git] / sound / pci / maestro3.c
blob3c40d726b46eacf088335fa007d9ff6c0cf91bd5
1 /*
2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the hardware init stuffs are based on maestro3 driver for
7 * OSS/Free by Zach Brown. Many thanks to Zach!
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 *
24 * ChangeLog:
25 * Aug. 27, 2001
26 * - Fixed deadlock on capture
27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
28 *
29 */
30
31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32 #define DRIVER_NAME "Maestro3"
33
34 #include <asm/io.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/init.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/moduleparam.h>
43 #include <linux/firmware.h>
44 #include <linux/input.h>
45 #include <sound/core.h>
46 #include <sound/info.h>
47 #include <sound/control.h>
48 #include <sound/pcm.h>
49 #include <sound/mpu401.h>
50 #include <sound/ac97_codec.h>
51 #include <sound/initval.h>
52 #include <asm/byteorder.h>
53
54 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
55 MODULE_DESCRIPTION("ESS Maestro3 PCI");
56 MODULE_LICENSE("GPL");
57 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
58 "{ESS,ES1988},"
59 "{ESS,Allegro PCI},"
60 "{ESS,Allegro-1 PCI},"
61 "{ESS,Canyon3D-2/LE PCI}}");
62 MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
63 MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
64
65 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
66 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
67 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
68 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
69 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
70
71 module_param_array(index, int, NULL, 0444);
72 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
73 module_param_array(id, charp, NULL, 0444);
74 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
75 module_param_array(enable, bool, NULL, 0444);
76 MODULE_PARM_DESC(enable, "Enable this soundcard.");
77 module_param_array(external_amp, bool, NULL, 0444);
78 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
79 module_param_array(amp_gpio, int, NULL, 0444);
80 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
81
82 #define MAX_PLAYBACKS 2
83 #define MAX_CAPTURES 1
84 #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
85
86
87 /*
88 * maestro3 registers
89 */
90
91 /* Allegro PCI configuration registers */
92 #define PCI_LEGACY_AUDIO_CTRL 0x40
93 #define SOUND_BLASTER_ENABLE 0x00000001
94 #define FM_SYNTHESIS_ENABLE 0x00000002
95 #define GAME_PORT_ENABLE 0x00000004
96 #define MPU401_IO_ENABLE 0x00000008
97 #define MPU401_IRQ_ENABLE 0x00000010
98 #define ALIAS_10BIT_IO 0x00000020
99 #define SB_DMA_MASK 0x000000C0
100 #define SB_DMA_0 0x00000040
101 #define SB_DMA_1 0x00000040
102 #define SB_DMA_R 0x00000080
103 #define SB_DMA_3 0x000000C0
104 #define SB_IRQ_MASK 0x00000700
105 #define SB_IRQ_5 0x00000000
106 #define SB_IRQ_7 0x00000100
107 #define SB_IRQ_9 0x00000200
108 #define SB_IRQ_10 0x00000300
109 #define MIDI_IRQ_MASK 0x00003800
110 #define SERIAL_IRQ_ENABLE 0x00004000
111 #define DISABLE_LEGACY 0x00008000
112
113 #define PCI_ALLEGRO_CONFIG 0x50
114 #define SB_ADDR_240 0x00000004
115 #define MPU_ADDR_MASK 0x00000018
116 #define MPU_ADDR_330 0x00000000
117 #define MPU_ADDR_300 0x00000008
118 #define MPU_ADDR_320 0x00000010
119 #define MPU_ADDR_340 0x00000018
120 #define USE_PCI_TIMING 0x00000040
121 #define POSTED_WRITE_ENABLE 0x00000080
122 #define DMA_POLICY_MASK 0x00000700
123 #define DMA_DDMA 0x00000000
124 #define DMA_TDMA 0x00000100
125 #define DMA_PCPCI 0x00000200
126 #define DMA_WBDMA16 0x00000400
127 #define DMA_WBDMA4 0x00000500
128 #define DMA_WBDMA2 0x00000600
129 #define DMA_WBDMA1 0x00000700
130 #define DMA_SAFE_GUARD 0x00000800
131 #define HI_PERF_GP_ENABLE 0x00001000
132 #define PIC_SNOOP_MODE_0 0x00002000
133 #define PIC_SNOOP_MODE_1 0x00004000
134 #define SOUNDBLASTER_IRQ_MASK 0x00008000
135 #define RING_IN_ENABLE 0x00010000
136 #define SPDIF_TEST_MODE 0x00020000
137 #define CLK_MULT_MODE_SELECT_2 0x00040000
138 #define EEPROM_WRITE_ENABLE 0x00080000
139 #define CODEC_DIR_IN 0x00100000
140 #define HV_BUTTON_FROM_GD 0x00200000
141 #define REDUCED_DEBOUNCE 0x00400000
142 #define HV_CTRL_ENABLE 0x00800000
143 #define SPDIF_ENABLE 0x01000000
144 #define CLK_DIV_SELECT 0x06000000
145 #define CLK_DIV_BY_48 0x00000000
146 #define CLK_DIV_BY_49 0x02000000
147 #define CLK_DIV_BY_50 0x04000000
148 #define CLK_DIV_RESERVED 0x06000000
149 #define PM_CTRL_ENABLE 0x08000000
150 #define CLK_MULT_MODE_SELECT 0x30000000
151 #define CLK_MULT_MODE_SHIFT 28
152 #define CLK_MULT_MODE_0 0x00000000
153 #define CLK_MULT_MODE_1 0x10000000
154 #define CLK_MULT_MODE_2 0x20000000
155 #define CLK_MULT_MODE_3 0x30000000
156 #define INT_CLK_SELECT 0x40000000
157 #define INT_CLK_MULT_RESET 0x80000000
158
159 /* M3 */
160 #define INT_CLK_SRC_NOT_PCI 0x00100000
161 #define INT_CLK_MULT_ENABLE 0x80000000
162
163 #define PCI_ACPI_CONTROL 0x54
164 #define PCI_ACPI_D0 0x00000000
165 #define PCI_ACPI_D1 0xB4F70000
166 #define PCI_ACPI_D2 0xB4F7B4F7
167
168 #define PCI_USER_CONFIG 0x58
169 #define EXT_PCI_MASTER_ENABLE 0x00000001
170 #define SPDIF_OUT_SELECT 0x00000002
171 #define TEST_PIN_DIR_CTRL 0x00000004
172 #define AC97_CODEC_TEST 0x00000020
173 #define TRI_STATE_BUFFER 0x00000080
174 #define IN_CLK_12MHZ_SELECT 0x00000100
175 #define MULTI_FUNC_DISABLE 0x00000200
176 #define EXT_MASTER_PAIR_SEL 0x00000400
177 #define PCI_MASTER_SUPPORT 0x00000800
178 #define STOP_CLOCK_ENABLE 0x00001000
179 #define EAPD_DRIVE_ENABLE 0x00002000
180 #define REQ_TRI_STATE_ENABLE 0x00004000
181 #define REQ_LOW_ENABLE 0x00008000
182 #define MIDI_1_ENABLE 0x00010000
183 #define MIDI_2_ENABLE 0x00020000
184 #define SB_AUDIO_SYNC 0x00040000
185 #define HV_CTRL_TEST 0x00100000
186 #define SOUNDBLASTER_TEST 0x00400000
187
188 #define PCI_USER_CONFIG_C 0x5C
189
190 #define PCI_DDMA_CTRL 0x60
191 #define DDMA_ENABLE 0x00000001
192
193
194 /* Allegro registers */
195 #define HOST_INT_CTRL 0x18
196 #define SB_INT_ENABLE 0x0001
197 #define MPU401_INT_ENABLE 0x0002
198 #define ASSP_INT_ENABLE 0x0010
199 #define RING_INT_ENABLE 0x0020
200 #define HV_INT_ENABLE 0x0040
201 #define CLKRUN_GEN_ENABLE 0x0100
202 #define HV_CTRL_TO_PME 0x0400
203 #define SOFTWARE_RESET_ENABLE 0x8000
204
205 /*
206 * should be using the above defines, probably.
207 */
208 #define REGB_ENABLE_RESET 0x01
209 #define REGB_STOP_CLOCK 0x10
210
211 #define HOST_INT_STATUS 0x1A
212 #define SB_INT_PENDING 0x01
213 #define MPU401_INT_PENDING 0x02
214 #define ASSP_INT_PENDING 0x10
215 #define RING_INT_PENDING 0x20
216 #define HV_INT_PENDING 0x40
217
218 #define HARDWARE_VOL_CTRL 0x1B
219 #define SHADOW_MIX_REG_VOICE 0x1C
220 #define HW_VOL_COUNTER_VOICE 0x1D
221 #define SHADOW_MIX_REG_MASTER 0x1E
222 #define HW_VOL_COUNTER_MASTER 0x1F
223
224 #define CODEC_COMMAND 0x30
225 #define CODEC_READ_B 0x80
226
227 #define CODEC_STATUS 0x30
228 #define CODEC_BUSY_B 0x01
229
230 #define CODEC_DATA 0x32
231
232 #define RING_BUS_CTRL_A 0x36
233 #define RAC_PME_ENABLE 0x0100
234 #define RAC_SDFS_ENABLE 0x0200
235 #define LAC_PME_ENABLE 0x0400
236 #define LAC_SDFS_ENABLE 0x0800
237 #define SERIAL_AC_LINK_ENABLE 0x1000
238 #define IO_SRAM_ENABLE 0x2000
239 #define IIS_INPUT_ENABLE 0x8000
240
241 #define RING_BUS_CTRL_B 0x38
242 #define SECOND_CODEC_ID_MASK 0x0003
243 #define SPDIF_FUNC_ENABLE 0x0010
244 #define SECOND_AC_ENABLE 0x0020
245 #define SB_MODULE_INTF_ENABLE 0x0040
246 #define SSPE_ENABLE 0x0040
247 #define M3I_DOCK_ENABLE 0x0080
248
249 #define SDO_OUT_DEST_CTRL 0x3A
250 #define COMMAND_ADDR_OUT 0x0003
251 #define PCM_LR_OUT_LOCAL 0x0000
252 #define PCM_LR_OUT_REMOTE 0x0004
253 #define PCM_LR_OUT_MUTE 0x0008
254 #define PCM_LR_OUT_BOTH 0x000C
255 #define LINE1_DAC_OUT_LOCAL 0x0000
256 #define LINE1_DAC_OUT_REMOTE 0x0010
257 #define LINE1_DAC_OUT_MUTE 0x0020
258 #define LINE1_DAC_OUT_BOTH 0x0030
259 #define PCM_CLS_OUT_LOCAL 0x0000
260 #define PCM_CLS_OUT_REMOTE 0x0040
261 #define PCM_CLS_OUT_MUTE 0x0080
262 #define PCM_CLS_OUT_BOTH 0x00C0
263 #define PCM_RLF_OUT_LOCAL 0x0000
264 #define PCM_RLF_OUT_REMOTE 0x0100
265 #define PCM_RLF_OUT_MUTE 0x0200
266 #define PCM_RLF_OUT_BOTH 0x0300
267 #define LINE2_DAC_OUT_LOCAL 0x0000
268 #define LINE2_DAC_OUT_REMOTE 0x0400
269 #define LINE2_DAC_OUT_MUTE 0x0800
270 #define LINE2_DAC_OUT_BOTH 0x0C00
271 #define HANDSET_OUT_LOCAL 0x0000
272 #define HANDSET_OUT_REMOTE 0x1000
273 #define HANDSET_OUT_MUTE 0x2000
274 #define HANDSET_OUT_BOTH 0x3000
275 #define IO_CTRL_OUT_LOCAL 0x0000
276 #define IO_CTRL_OUT_REMOTE 0x4000
277 #define IO_CTRL_OUT_MUTE 0x8000
278 #define IO_CTRL_OUT_BOTH 0xC000
279
280 #define SDO_IN_DEST_CTRL 0x3C
281 #define STATUS_ADDR_IN 0x0003
282 #define PCM_LR_IN_LOCAL 0x0000
283 #define PCM_LR_IN_REMOTE 0x0004
284 #define PCM_LR_RESERVED 0x0008
285 #define PCM_LR_IN_BOTH 0x000C
286 #define LINE1_ADC_IN_LOCAL 0x0000
287 #define LINE1_ADC_IN_REMOTE 0x0010
288 #define LINE1_ADC_IN_MUTE 0x0020
289 #define MIC_ADC_IN_LOCAL 0x0000
290 #define MIC_ADC_IN_REMOTE 0x0040
291 #define MIC_ADC_IN_MUTE 0x0080
292 #define LINE2_DAC_IN_LOCAL 0x0000
293 #define LINE2_DAC_IN_REMOTE 0x0400
294 #define LINE2_DAC_IN_MUTE 0x0800
295 #define HANDSET_IN_LOCAL 0x0000
296 #define HANDSET_IN_REMOTE 0x1000
297 #define HANDSET_IN_MUTE 0x2000
298 #define IO_STATUS_IN_LOCAL 0x0000
299 #define IO_STATUS_IN_REMOTE 0x4000
300
301 #define SPDIF_IN_CTRL 0x3E
302 #define SPDIF_IN_ENABLE 0x0001
303
304 #define GPIO_DATA 0x60
305 #define GPIO_DATA_MASK 0x0FFF
306 #define GPIO_HV_STATUS 0x3000
307 #define GPIO_PME_STATUS 0x4000
308
309 #define GPIO_MASK 0x64
310 #define GPIO_DIRECTION 0x68
311 #define GPO_PRIMARY_AC97 0x0001
312 #define GPI_LINEOUT_SENSE 0x0004
313 #define GPO_SECONDARY_AC97 0x0008
314 #define GPI_VOL_DOWN 0x0010
315 #define GPI_VOL_UP 0x0020
316 #define GPI_IIS_CLK 0x0040
317 #define GPI_IIS_LRCLK 0x0080
318 #define GPI_IIS_DATA 0x0100
319 #define GPI_DOCKING_STATUS 0x0100
320 #define GPI_HEADPHONE_SENSE 0x0200
321 #define GPO_EXT_AMP_SHUTDOWN 0x1000
322
323 #define GPO_EXT_AMP_M3 1 /* default m3 amp */
324 #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
325
326 /* M3 */
327 #define GPO_M3_EXT_AMP_SHUTDN 0x0002
328
329 #define ASSP_INDEX_PORT 0x80
330 #define ASSP_MEMORY_PORT 0x82
331 #define ASSP_DATA_PORT 0x84
332
333 #define MPU401_DATA_PORT 0x98
334 #define MPU401_STATUS_PORT 0x99
335
336 #define CLK_MULT_DATA_PORT 0x9C
337
338 #define ASSP_CONTROL_A 0xA2
339 #define ASSP_0_WS_ENABLE 0x01
340 #define ASSP_CTRL_A_RESERVED1 0x02
341 #define ASSP_CTRL_A_RESERVED2 0x04
342 #define ASSP_CLK_49MHZ_SELECT 0x08
343 #define FAST_PLU_ENABLE 0x10
344 #define ASSP_CTRL_A_RESERVED3 0x20
345 #define DSP_CLK_36MHZ_SELECT 0x40
346
347 #define ASSP_CONTROL_B 0xA4
348 #define RESET_ASSP 0x00
349 #define RUN_ASSP 0x01
350 #define ENABLE_ASSP_CLOCK 0x00
351 #define STOP_ASSP_CLOCK 0x10
352 #define RESET_TOGGLE 0x40
353
354 #define ASSP_CONTROL_C 0xA6
355 #define ASSP_HOST_INT_ENABLE 0x01
356 #define FM_ADDR_REMAP_DISABLE 0x02
357 #define HOST_WRITE_PORT_ENABLE 0x08
358
359 #define ASSP_HOST_INT_STATUS 0xAC
360 #define DSP2HOST_REQ_PIORECORD 0x01
361 #define DSP2HOST_REQ_I2SRATE 0x02
362 #define DSP2HOST_REQ_TIMER 0x04
363
364 /* AC97 registers */
365 /* XXX fix this crap up */
366 /*#define AC97_RESET 0x00*/
367
368 #define AC97_VOL_MUTE_B 0x8000
369 #define AC97_VOL_M 0x1F
370 #define AC97_LEFT_VOL_S 8
371
372 #define AC97_MASTER_VOL 0x02
373 #define AC97_LINE_LEVEL_VOL 0x04
374 #define AC97_MASTER_MONO_VOL 0x06
375 #define AC97_PC_BEEP_VOL 0x0A
376 #define AC97_PC_BEEP_VOL_M 0x0F
377 #define AC97_SROUND_MASTER_VOL 0x38
378 #define AC97_PC_BEEP_VOL_S 1
379
380 /*#define AC97_PHONE_VOL 0x0C
381 #define AC97_MIC_VOL 0x0E*/
382 #define AC97_MIC_20DB_ENABLE 0x40
383
384 /*#define AC97_LINEIN_VOL 0x10
385 #define AC97_CD_VOL 0x12
386 #define AC97_VIDEO_VOL 0x14
387 #define AC97_AUX_VOL 0x16*/
388 #define AC97_PCM_OUT_VOL 0x18
389 /*#define AC97_RECORD_SELECT 0x1A*/
390 #define AC97_RECORD_MIC 0x00
391 #define AC97_RECORD_CD 0x01
392 #define AC97_RECORD_VIDEO 0x02
393 #define AC97_RECORD_AUX 0x03
394 #define AC97_RECORD_MONO_MUX 0x02
395 #define AC97_RECORD_DIGITAL 0x03
396 #define AC97_RECORD_LINE 0x04
397 #define AC97_RECORD_STEREO 0x05
398 #define AC97_RECORD_MONO 0x06
399 #define AC97_RECORD_PHONE 0x07
400
401 /*#define AC97_RECORD_GAIN 0x1C*/
402 #define AC97_RECORD_VOL_M 0x0F
403
404 /*#define AC97_GENERAL_PURPOSE 0x20*/
405 #define AC97_POWER_DOWN_CTRL 0x26
406 #define AC97_ADC_READY 0x0001
407 #define AC97_DAC_READY 0x0002
408 #define AC97_ANALOG_READY 0x0004
409 #define AC97_VREF_ON 0x0008
410 #define AC97_PR0 0x0100
411 #define AC97_PR1 0x0200
412 #define AC97_PR2 0x0400
413 #define AC97_PR3 0x0800
414 #define AC97_PR4 0x1000
415
416 #define AC97_RESERVED1 0x28
417
418 #define AC97_VENDOR_TEST 0x5A
419
420 #define AC97_CLOCK_DELAY 0x5C
421 #define AC97_LINEOUT_MUX_SEL 0x0001
422 #define AC97_MONO_MUX_SEL 0x0002
423 #define AC97_CLOCK_DELAY_SEL 0x1F
424 #define AC97_DAC_CDS_SHIFT 6
425 #define AC97_ADC_CDS_SHIFT 11
426
427 #define AC97_MULTI_CHANNEL_SEL 0x74
428
429 /*#define AC97_VENDOR_ID1 0x7C
430 #define AC97_VENDOR_ID2 0x7E*/
431
432 /*
433 * ASSP control regs
434 */
435 #define DSP_PORT_TIMER_COUNT 0x06
436
437 #define DSP_PORT_MEMORY_INDEX 0x80
438
439 #define DSP_PORT_MEMORY_TYPE 0x82
440 #define MEMTYPE_INTERNAL_CODE 0x0002
441 #define MEMTYPE_INTERNAL_DATA 0x0003
442 #define MEMTYPE_MASK 0x0003
443
444 #define DSP_PORT_MEMORY_DATA 0x84
445
446 #define DSP_PORT_CONTROL_REG_A 0xA2
447 #define DSP_PORT_CONTROL_REG_B 0xA4
448 #define DSP_PORT_CONTROL_REG_C 0xA6
449
450 #define REV_A_CODE_MEMORY_BEGIN 0x0000
451 #define REV_A_CODE_MEMORY_END 0x0FFF
452 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
453 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
454
455 #define REV_B_CODE_MEMORY_BEGIN 0x0000
456 #define REV_B_CODE_MEMORY_END 0x0BFF
457 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
458 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
459
460 #define REV_A_DATA_MEMORY_BEGIN 0x1000
461 #define REV_A_DATA_MEMORY_END 0x2FFF
462 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
463 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
464
465 #define REV_B_DATA_MEMORY_BEGIN 0x1000
466 #define REV_B_DATA_MEMORY_END 0x2BFF
467 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
468 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
469
470
471 #define NUM_UNITS_KERNEL_CODE 16
472 #define NUM_UNITS_KERNEL_DATA 2
473
474 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
475 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
476
477 /*
478 * Kernel data layout
479 */
480
481 #define DP_SHIFT_COUNT 7
482
483 #define KDATA_BASE_ADDR 0x1000
484 #define KDATA_BASE_ADDR2 0x1080
485
486 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
487 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
488 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
489 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
490 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
491 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
492 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
493 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
494 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
495
496 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
497 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
498
499 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
500 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
501 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
502 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
503 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
504 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
505 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
506 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
507 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
508 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
509
510 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
511 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
512
513 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
514 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
515
516 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
517 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
518
519 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
520 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
521 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
522
523 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
524 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
525 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
526 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
527 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
528
529 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
530 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
531 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
532
533 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
534 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
535 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
536
537 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
538 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
539 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
540 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
541 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
542 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
543 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
544 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
545 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
546 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
547
548 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
549 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
550 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
551
552 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
553 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
554
555 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
556 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
557 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
558
559 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
560 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
561 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
562 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
563 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
564 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
565
566 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
567 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
568 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
569 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
570 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
571 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
572
573 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
574 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
575 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
576 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
577 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
578 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
579
580 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
581 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
582 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
583 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
584
585 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
586 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
587
588 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
589 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
590
591 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
592 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
593 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
594 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
595 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
596
597 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
598 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
599
600 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
601 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
602 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
603
604 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
605 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
606
607 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
608
609 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
610 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
611 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
612 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
613 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
614 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
615 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
616 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
617 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
618 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
619 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
620 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
621
622 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
623 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
624 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
625 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
626
627 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
628 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
629
630 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
631 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
632 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
633 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
634
635 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
636 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
637 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
638 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
639 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
640
641 /*
642 * second 'segment' (?) reserved for mixer
643 * buffers..
644 */
645
646 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
647 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
648 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
649 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
650 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
651 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
652 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
653 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
654 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
655 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
656 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
657 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
658 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
659 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
660 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
661 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
662
663 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
664 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
665 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
666 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
667 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
668 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
669 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
670 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
671 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
672 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
673 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
674
675 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
676 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
677 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
678 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
679 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
680 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
681
682 #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
683 #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
684 #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
685 #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
686
687 /*
688 * client data area offsets
689 */
690 #define CDATA_INSTANCE_READY 0x00
691
692 #define CDATA_HOST_SRC_ADDRL 0x01
693 #define CDATA_HOST_SRC_ADDRH 0x02
694 #define CDATA_HOST_SRC_END_PLUS_1L 0x03
695 #define CDATA_HOST_SRC_END_PLUS_1H 0x04
696 #define CDATA_HOST_SRC_CURRENTL 0x05
697 #define CDATA_HOST_SRC_CURRENTH 0x06
698
699 #define CDATA_IN_BUF_CONNECT 0x07
700 #define CDATA_OUT_BUF_CONNECT 0x08
701
702 #define CDATA_IN_BUF_BEGIN 0x09
703 #define CDATA_IN_BUF_END_PLUS_1 0x0A
704 #define CDATA_IN_BUF_HEAD 0x0B
705 #define CDATA_IN_BUF_TAIL 0x0C
706 #define CDATA_OUT_BUF_BEGIN 0x0D
707 #define CDATA_OUT_BUF_END_PLUS_1 0x0E
708 #define CDATA_OUT_BUF_HEAD 0x0F
709 #define CDATA_OUT_BUF_TAIL 0x10
710
711 #define CDATA_DMA_CONTROL 0x11
712 #define CDATA_RESERVED 0x12
713
714 #define CDATA_FREQUENCY 0x13
715 #define CDATA_LEFT_VOLUME 0x14
716 #define CDATA_RIGHT_VOLUME 0x15
717 #define CDATA_LEFT_SUR_VOL 0x16
718 #define CDATA_RIGHT_SUR_VOL 0x17
719
720 #define CDATA_HEADER_LEN 0x18
721
722 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
723 #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
724 #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
725 #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
726 #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
727 #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
728 #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
729 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
730
731 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
732 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
733 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
734 #define MINISRC_BIQUAD_STAGE 2
735 #define MINISRC_COEF_LOC 0x175
736
737 #define DMACONTROL_BLOCK_MASK 0x000F
738 #define DMAC_BLOCK0_SELECTOR 0x0000
739 #define DMAC_BLOCK1_SELECTOR 0x0001
740 #define DMAC_BLOCK2_SELECTOR 0x0002
741 #define DMAC_BLOCK3_SELECTOR 0x0003
742 #define DMAC_BLOCK4_SELECTOR 0x0004
743 #define DMAC_BLOCK5_SELECTOR 0x0005
744 #define DMAC_BLOCK6_SELECTOR 0x0006
745 #define DMAC_BLOCK7_SELECTOR 0x0007
746 #define DMAC_BLOCK8_SELECTOR 0x0008
747 #define DMAC_BLOCK9_SELECTOR 0x0009
748 #define DMAC_BLOCKA_SELECTOR 0x000A
749 #define DMAC_BLOCKB_SELECTOR 0x000B
750 #define DMAC_BLOCKC_SELECTOR 0x000C
751 #define DMAC_BLOCKD_SELECTOR 0x000D
752 #define DMAC_BLOCKE_SELECTOR 0x000E
753 #define DMAC_BLOCKF_SELECTOR 0x000F
754 #define DMACONTROL_PAGE_MASK 0x00F0
755 #define DMAC_PAGE0_SELECTOR 0x0030
756 #define DMAC_PAGE1_SELECTOR 0x0020
757 #define DMAC_PAGE2_SELECTOR 0x0010
758 #define DMAC_PAGE3_SELECTOR 0x0000
759 #define DMACONTROL_AUTOREPEAT 0x1000
760 #define DMACONTROL_STOPPED 0x2000
761 #define DMACONTROL_DIRECTION 0x0100
762
763 /*
764 * an arbitrary volume we set the internal
765 * volume settings to so that the ac97 volume
766 * range is a little less insane. 0x7fff is
767 * max.
768 */
769 #define ARB_VOLUME ( 0x6800 )
770
771 /*
772 */
773
774 struct m3_list {
775 int curlen;
776 int mem_addr;
777 int max;
778 };
779
780 struct m3_dma {
781
782 int number;
783 struct snd_pcm_substream *substream;
784
785 struct assp_instance {
786 unsigned short code, data;
787 } inst;
788
789 int running;
790 int opened;
791
792 unsigned long buffer_addr;
793 int dma_size;
794 int period_size;
795 unsigned int hwptr;
796 int count;
797
798 int index[3];
799 struct m3_list *index_list[3];
800
801 int in_lists;
802
803 struct list_head list;
804
805 };
806
807 struct snd_m3 {
808
809 struct snd_card *card;
810
811 unsigned long iobase;
812
813 int irq;
814 unsigned int allegro_flag : 1;
815
816 struct snd_ac97 *ac97;
817
818 struct snd_pcm *pcm;
819
820 struct pci_dev *pci;
821
822 int dacs_active;
823 int timer_users;
824
825 struct m3_list msrc_list;
826 struct m3_list mixer_list;
827 struct m3_list adc1_list;
828 struct m3_list dma_list;
829
830 /* for storing reset state..*/
831 u8 reset_state;
832
833 int external_amp;
834 int amp_gpio; /* gpio pin # for external amp, -1 = default */
835 unsigned int hv_config; /* hardware-volume config bits */
836 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
837 (e.g. for IrDA on Dell Inspirons) */
838 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
839
840 /* midi */
841 struct snd_rawmidi *rmidi;
842
843 /* pcm streams */
844 int num_substreams;
845 struct m3_dma *substreams;
846
847 spinlock_t reg_lock;
848
849 #ifdef CONFIG_SND_MAESTRO3_INPUT
850 struct input_dev *input_dev;
851 char phys[64]; /* physical device path */
852 #else
853 spinlock_t ac97_lock;
854 struct snd_kcontrol *master_switch;
855 struct snd_kcontrol *master_volume;
856 struct tasklet_struct hwvol_tq;
857 #endif
858
859 unsigned int in_suspend;
860
861 #ifdef CONFIG_PM
862 u16 *suspend_mem;
863 #endif
864
865 const struct firmware *assp_kernel_image;
866 const struct firmware *assp_minisrc_image;
867 };
868
869 /*
870 * pci ids
871 */
872 static DEFINE_PCI_DEVICE_TABLE(snd_m3_ids) = {
873 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
874 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
875 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
876 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
877 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
878 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
879 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
880 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
881 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
882 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
883 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
884 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
885 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
886 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
887 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
888 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
889 {0,},
890 };
891
892 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
893
894 static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = {
895 SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
896 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
897 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
898 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
899 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
900 { } /* END */
901 };
902
903 static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = {
904 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
905 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
906 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
907 { } /* END */
908 };
909
910 /* hardware volume quirks */
911 static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = {
912 /* Allegro chips */
913 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
914 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
915 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
916 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
917 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
918 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
919 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
920 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
921 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
922 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
923 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
924 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
925 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
926 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
927 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
928 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
929 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
930 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
931 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
932 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
933 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
934 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
935 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
936 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
937 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
938 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
939 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
940 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
941 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
942 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
943 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
944 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
945 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
946 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
947 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
948 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
949 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
950 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
951 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
952 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
953 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
954 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
955 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
956 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
957 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
958 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
959 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
960 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
961 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
962 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
963 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
964 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
965 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
966 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
967 /* Maestro3 chips */
968 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
969 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
970 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
971 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
972 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
973 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
974 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
975 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
976 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
977 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
978 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
979 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
980 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
981 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
982 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
983 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
984 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
985 { } /* END */
986 };
987
988 /* HP Omnibook quirks */
989 static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = {
990 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
991 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
992 { } /* END */
993 };
994
995 /*
996 * lowlevel functions
997 */
998
999 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
1000 {
1001 outw(value, chip->iobase + reg);
1002 }
1003
1004 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
1005 {
1006 return inw(chip->iobase + reg);
1007 }
1008
1009 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1010 {
1011 outb(value, chip->iobase + reg);
1012 }
1013
1014 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1015 {
1016 return inb(chip->iobase + reg);
1017 }
1018
1019 /*
1020 * access 16bit words to the code or data regions of the dsp's memory.
1021 * index addresses 16bit words.
1022 */
1023 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1024 {
1025 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1026 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1027 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1028 }
1029
1030 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1031 {
1032 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1033 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1034 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1035 }
1036
1037 static void snd_m3_assp_halt(struct snd_m3 *chip)
1038 {
1039 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1040 msleep(10);
1041 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1042 }
1043
1044 static void snd_m3_assp_continue(struct snd_m3 *chip)
1045 {
1046 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1047 }
1048
1049
1050 /*
1051 * This makes me sad. the maestro3 has lists
1052 * internally that must be packed.. 0 terminates,
1053 * apparently, or maybe all unused entries have
1054 * to be 0, the lists have static lengths set
1055 * by the binary code images.
1056 */
1057
1058 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1059 {
1060 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1061 list->mem_addr + list->curlen,
1062 val);
1063 return list->curlen++;
1064 }
1065
1066 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1067 {
1068 u16 val;
1069 int lastindex = list->curlen - 1;
1070
1071 if (index != lastindex) {
1072 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1073 list->mem_addr + lastindex);
1074 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1075 list->mem_addr + index,
1076 val);
1077 }
1078
1079 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1080 list->mem_addr + lastindex,
1081 0);
1082
1083 list->curlen--;
1084 }
1085
1086 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1087 {
1088 chip->timer_users++;
1089 if (chip->timer_users != 1)
1090 return;
1091
1092 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1093 KDATA_TIMER_COUNT_RELOAD,
1094 240);
1095
1096 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1097 KDATA_TIMER_COUNT_CURRENT,
1098 240);
1099
1100 snd_m3_outw(chip,
1101 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1102 HOST_INT_CTRL);
1103 }
1104
1105 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1106 {
1107 chip->timer_users--;
1108 if (chip->timer_users > 0)
1109 return;
1110
1111 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1112 KDATA_TIMER_COUNT_RELOAD,
1113 0);
1114
1115 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1116 KDATA_TIMER_COUNT_CURRENT,
1117 0);
1118
1119 snd_m3_outw(chip,
1120 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1121 HOST_INT_CTRL);
1122 }
1123
1124 /*
1125 * start/stop
1126 */
1127
1128 /* spinlock held! */
1129 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1130 struct snd_pcm_substream *subs)
1131 {
1132 if (! s || ! subs)
1133 return -EINVAL;
1134
1135 snd_m3_inc_timer_users(chip);
1136 switch (subs->stream) {
1137 case SNDRV_PCM_STREAM_PLAYBACK:
1138 chip->dacs_active++;
1139 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1140 s->inst.data + CDATA_INSTANCE_READY, 1);
1141 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1142 KDATA_MIXER_TASK_NUMBER,
1143 chip->dacs_active);
1144 break;
1145 case SNDRV_PCM_STREAM_CAPTURE:
1146 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1147 KDATA_ADC1_REQUEST, 1);
1148 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1149 s->inst.data + CDATA_INSTANCE_READY, 1);
1150 break;
1151 }
1152 return 0;
1153 }
1154
1155 /* spinlock held! */
1156 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1157 struct snd_pcm_substream *subs)
1158 {
1159 if (! s || ! subs)
1160 return -EINVAL;
1161
1162 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1163 s->inst.data + CDATA_INSTANCE_READY, 0);
1164 snd_m3_dec_timer_users(chip);
1165 switch (subs->stream) {
1166 case SNDRV_PCM_STREAM_PLAYBACK:
1167 chip->dacs_active--;
1168 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1169 KDATA_MIXER_TASK_NUMBER,
1170 chip->dacs_active);
1171 break;
1172 case SNDRV_PCM_STREAM_CAPTURE:
1173 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1174 KDATA_ADC1_REQUEST, 0);
1175 break;
1176 }
1177 return 0;
1178 }
1179
1180 static int
1181 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1182 {
1183 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1184 struct m3_dma *s = subs->runtime->private_data;
1185 int err = -EINVAL;
1186
1187 if (snd_BUG_ON(!s))
1188 return -ENXIO;
1189
1190 spin_lock(&chip->reg_lock);
1191 switch (cmd) {
1192 case SNDRV_PCM_TRIGGER_START:
1193 case SNDRV_PCM_TRIGGER_RESUME:
1194 if (s->running)
1195 err = -EBUSY;
1196 else {
1197 s->running = 1;
1198 err = snd_m3_pcm_start(chip, s, subs);
1199 }
1200 break;
1201 case SNDRV_PCM_TRIGGER_STOP:
1202 case SNDRV_PCM_TRIGGER_SUSPEND:
1203 if (! s->running)
1204 err = 0; /* should return error? */
1205 else {
1206 s->running = 0;
1207 err = snd_m3_pcm_stop(chip, s, subs);
1208 }
1209 break;
1210 }
1211 spin_unlock(&chip->reg_lock);
1212 return err;
1213 }
1214
1215 /*
1216 * setup
1217 */
1218 static void
1219 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1220 {
1221 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1222 struct snd_pcm_runtime *runtime = subs->runtime;
1223
1224 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1225 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1226 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1227 } else {
1228 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1229 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1230 }
1231 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1232 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1233
1234 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1235 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1236 s->hwptr = 0;
1237 s->count = 0;
1238
1239 #define LO(x) ((x) & 0xffff)
1240 #define HI(x) LO((x) >> 16)
1241
1242 /* host dma buffer pointers */
1243 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1244 s->inst.data + CDATA_HOST_SRC_ADDRL,
1245 LO(s->buffer_addr));
1246
1247 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1248 s->inst.data + CDATA_HOST_SRC_ADDRH,
1249 HI(s->buffer_addr));
1250
1251 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1252 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1253 LO(s->buffer_addr + s->dma_size));
1254
1255 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1256 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1257 HI(s->buffer_addr + s->dma_size));
1258
1259 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1260 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1261 LO(s->buffer_addr));
1262
1263 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1264 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1265 HI(s->buffer_addr));
1266 #undef LO
1267 #undef HI
1268
1269 /* dsp buffers */
1270
1271 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1272 s->inst.data + CDATA_IN_BUF_BEGIN,
1273 dsp_in_buffer);
1274
1275 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1276 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1277 dsp_in_buffer + (dsp_in_size / 2));
1278
1279 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1280 s->inst.data + CDATA_IN_BUF_HEAD,
1281 dsp_in_buffer);
1282
1283 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1284 s->inst.data + CDATA_IN_BUF_TAIL,
1285 dsp_in_buffer);
1286
1287 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1288 s->inst.data + CDATA_OUT_BUF_BEGIN,
1289 dsp_out_buffer);
1290
1291 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1292 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1293 dsp_out_buffer + (dsp_out_size / 2));
1294
1295 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1296 s->inst.data + CDATA_OUT_BUF_HEAD,
1297 dsp_out_buffer);
1298
1299 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1300 s->inst.data + CDATA_OUT_BUF_TAIL,
1301 dsp_out_buffer);
1302 }
1303
1304 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1305 struct snd_pcm_runtime *runtime)
1306 {
1307 u32 freq;
1308
1309 /*
1310 * put us in the lists if we're not already there
1311 */
1312 if (! s->in_lists) {
1313 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1314 s->inst.data >> DP_SHIFT_COUNT);
1315 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1316 s->inst.data >> DP_SHIFT_COUNT);
1317 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1318 s->inst.data >> DP_SHIFT_COUNT);
1319 s->in_lists = 1;
1320 }
1321
1322 /* write to 'mono' word */
1323 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1324 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1325 runtime->channels == 2 ? 0 : 1);
1326 /* write to '8bit' word */
1327 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1328 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1329 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1330
1331 /* set up dac/adc rate */
1332 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1333 if (freq)
1334 freq--;
1335
1336 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1337 s->inst.data + CDATA_FREQUENCY,
1338 freq);
1339 }
1340
1341
1342 static const struct play_vals {
1343 u16 addr, val;
1344 } pv[] = {
1345 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1346 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1347 {SRC3_DIRECTION_OFFSET, 0} ,
1348 /* +1, +2 are stereo/16 bit */
1349 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1350 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1351 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1352 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1353 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1354 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1355 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1356 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1357 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1358 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1359 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1360 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1361 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1362 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1363 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1364 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1365 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1366 };
1367
1368
1369 /* the mode passed should be already shifted and masked */
1370 static void
1371 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1372 struct snd_pcm_substream *subs)
1373 {
1374 unsigned int i;
1375
1376 /*
1377 * some per client initializers
1378 */
1379
1380 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1381 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1382 s->inst.data + 40 + 8);
1383
1384 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1385 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1386 s->inst.code + MINISRC_COEF_LOC);
1387
1388 /* enable or disable low pass filter? */
1389 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1390 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1391 subs->runtime->rate > 45000 ? 0xff : 0);
1392
1393 /* tell it which way dma is going? */
1394 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1395 s->inst.data + CDATA_DMA_CONTROL,
1396 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1397
1398 /*
1399 * set an armload of static initializers
1400 */
1401 for (i = 0; i < ARRAY_SIZE(pv); i++)
1402 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1403 s->inst.data + pv[i].addr, pv[i].val);
1404 }
1405
1406 /*
1407 * Native record driver
1408 */
1409 static const struct rec_vals {
1410 u16 addr, val;
1411 } rv[] = {
1412 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1413 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1414 {SRC3_DIRECTION_OFFSET, 1} ,
1415 /* +1, +2 are stereo/16 bit */
1416 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1417 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1418 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1419 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1420 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1421 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1422 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1423 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1424 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1425 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1426 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1427 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1428 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1429 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1430 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1431 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1432 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1433 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1434 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1435 };
1436
1437 static void
1438 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1439 {
1440 unsigned int i;
1441
1442 /*
1443 * some per client initializers
1444 */
1445
1446 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1447 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1448 s->inst.data + 40 + 8);
1449
1450 /* tell it which way dma is going? */
1451 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1452 s->inst.data + CDATA_DMA_CONTROL,
1453 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1454 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1455
1456 /*
1457 * set an armload of static initializers
1458 */
1459 for (i = 0; i < ARRAY_SIZE(rv); i++)
1460 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1461 s->inst.data + rv[i].addr, rv[i].val);
1462 }
1463
1464 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1465 struct snd_pcm_hw_params *hw_params)
1466 {
1467 struct m3_dma *s = substream->runtime->private_data;
1468 int err;
1469
1470 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1471 return err;
1472 /* set buffer address */
1473 s->buffer_addr = substream->runtime->dma_addr;
1474 if (s->buffer_addr & 0x3) {
1475 snd_printk(KERN_ERR "oh my, not aligned\n");
1476 s->buffer_addr = s->buffer_addr & ~0x3;
1477 }
1478 return 0;
1479 }
1480
1481 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1482 {
1483 struct m3_dma *s;
1484
1485 if (substream->runtime->private_data == NULL)
1486 return 0;
1487 s = substream->runtime->private_data;
1488 snd_pcm_lib_free_pages(substream);
1489 s->buffer_addr = 0;
1490 return 0;
1491 }
1492
1493 static int
1494 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1495 {
1496 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1497 struct snd_pcm_runtime *runtime = subs->runtime;
1498 struct m3_dma *s = runtime->private_data;
1499
1500 if (snd_BUG_ON(!s))
1501 return -ENXIO;
1502
1503 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1504 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1505 return -EINVAL;
1506 if (runtime->rate > 48000 ||
1507 runtime->rate < 8000)
1508 return -EINVAL;
1509
1510 spin_lock_irq(&chip->reg_lock);
1511
1512 snd_m3_pcm_setup1(chip, s, subs);
1513
1514 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1515 snd_m3_playback_setup(chip, s, subs);
1516 else
1517 snd_m3_capture_setup(chip, s, subs);
1518
1519 snd_m3_pcm_setup2(chip, s, runtime);
1520
1521 spin_unlock_irq(&chip->reg_lock);
1522
1523 return 0;
1524 }
1525
1526 /*
1527 * get current pointer
1528 */
1529 static unsigned int
1530 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1531 {
1532 u16 hi = 0, lo = 0;
1533 int retry = 10;
1534 u32 addr;
1535
1536 /*
1537 * try and get a valid answer
1538 */
1539 while (retry--) {
1540 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1541 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1542
1543 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1544 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1545
1546 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1547 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1548 break;
1549 }
1550 addr = lo | ((u32)hi<<16);
1551 return (unsigned int)(addr - s->buffer_addr);
1552 }
1553
1554 static snd_pcm_uframes_t
1555 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1556 {
1557 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1558 unsigned int ptr;
1559 struct m3_dma *s = subs->runtime->private_data;
1560
1561 if (snd_BUG_ON(!s))
1562 return 0;
1563
1564 spin_lock(&chip->reg_lock);
1565 ptr = snd_m3_get_pointer(chip, s, subs);
1566 spin_unlock(&chip->reg_lock);
1567 return bytes_to_frames(subs->runtime, ptr);
1568 }
1569
1570
1571 /* update pointer */
1572 /* spinlock held! */
1573 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1574 {
1575 struct snd_pcm_substream *subs = s->substream;
1576 unsigned int hwptr;
1577 int diff;
1578
1579 if (! s->running)
1580 return;
1581
1582 hwptr = snd_m3_get_pointer(chip, s, subs);
1583
1584 /* try to avoid expensive modulo divisions */
1585 if (hwptr >= s->dma_size)
1586 hwptr %= s->dma_size;
1587
1588 diff = s->dma_size + hwptr - s->hwptr;
1589 if (diff >= s->dma_size)
1590 diff %= s->dma_size;
1591
1592 s->hwptr = hwptr;
1593 s->count += diff;
1594
1595 if (s->count >= (signed)s->period_size) {
1596
1597 if (s->count < 2 * (signed)s->period_size)
1598 s->count -= (signed)s->period_size;
1599 else
1600 s->count %= s->period_size;
1601
1602 spin_unlock(&chip->reg_lock);
1603 snd_pcm_period_elapsed(subs);
1604 spin_lock(&chip->reg_lock);
1605 }
1606 }
1607
1608 /* The m3's hardware volume works by incrementing / decrementing 2 counters
1609 (without wrap around) in response to volume button presses and then
1610 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1611 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1612 static void snd_m3_update_hw_volume(unsigned long private_data)
1613 {
1614 struct snd_m3 *chip = (struct snd_m3 *) private_data;
1615 int x, val;
1616 #ifndef CONFIG_SND_MAESTRO3_INPUT
1617 unsigned long flags;
1618 #endif
1619
1620 /* Figure out which volume control button was pushed,
1621 based on differences from the default register
1622 values. */
1623 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1624
1625 /* Reset the volume counters to 4. Tests on the allegro integrated
1626 into a Compaq N600C laptop, have revealed that:
1627 1) Writing any value will result in the 2 counters being reset to
1628 4 so writing 0x88 is not strictly necessary
1629 2) Writing to any of the 4 involved registers will reset all 4
1630 of them (and reading them always returns the same value for all
1631 of them)
1632 It could be that a maestro deviates from this, so leave the code
1633 as is. */
1634 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1635 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1636 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1637 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1638
1639 /* Ignore spurious HV interrupts during suspend / resume, this avoids
1640 mistaking them for a mute button press. */
1641 if (chip->in_suspend)
1642 return;
1643
1644 #ifndef CONFIG_SND_MAESTRO3_INPUT
1645 if (!chip->master_switch || !chip->master_volume)
1646 return;
1647
1648 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1649 spin_lock_irqsave(&chip->ac97_lock, flags);
1650
1651 val = chip->ac97->regs[AC97_MASTER_VOL];
1652 switch (x) {
1653 case 0x88:
1654 /* The counters have not changed, yet we've received a HV
1655 interrupt. According to tests run by various people this
1656 happens when pressing the mute button. */
1657 val ^= 0x8000;
1658 chip->ac97->regs[AC97_MASTER_VOL] = val;
1659 outw(val, chip->iobase + CODEC_DATA);
1660 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1661 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1662 &chip->master_switch->id);
1663 break;
1664 case 0xaa:
1665 /* counters increased by 1 -> volume up */
1666 if ((val & 0x7f) > 0)
1667 val--;
1668 if ((val & 0x7f00) > 0)
1669 val -= 0x0100;
1670 chip->ac97->regs[AC97_MASTER_VOL] = val;
1671 outw(val, chip->iobase + CODEC_DATA);
1672 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1673 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1674 &chip->master_volume->id);
1675 break;
1676 case 0x66:
1677 /* counters decreased by 1 -> volume down */
1678 if ((val & 0x7f) < 0x1f)
1679 val++;
1680 if ((val & 0x7f00) < 0x1f00)
1681 val += 0x0100;
1682 chip->ac97->regs[AC97_MASTER_VOL] = val;
1683 outw(val, chip->iobase + CODEC_DATA);
1684 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1685 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1686 &chip->master_volume->id);
1687 break;
1688 }
1689 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1690 #else
1691 if (!chip->input_dev)
1692 return;
1693
1694 val = 0;
1695 switch (x) {
1696 case 0x88:
1697 /* The counters have not changed, yet we've received a HV
1698 interrupt. According to tests run by various people this
1699 happens when pressing the mute button. */
1700 val = KEY_MUTE;
1701 break;
1702 case 0xaa:
1703 /* counters increased by 1 -> volume up */
1704 val = KEY_VOLUMEUP;
1705 break;
1706 case 0x66:
1707 /* counters decreased by 1 -> volume down */
1708 val = KEY_VOLUMEDOWN;
1709 break;
1710 }
1711
1712 if (val) {
1713 input_report_key(chip->input_dev, val, 1);
1714 input_sync(chip->input_dev);
1715 input_report_key(chip->input_dev, val, 0);
1716 input_sync(chip->input_dev);
1717 }
1718 #endif
1719 }
1720
1721 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1722 {
1723 struct snd_m3 *chip = dev_id;
1724 u8 status;
1725 int i;
1726
1727 status = inb(chip->iobase + HOST_INT_STATUS);
1728
1729 if (status == 0xff)
1730 return IRQ_NONE;
1731
1732 if (status & HV_INT_PENDING)
1733 #ifdef CONFIG_SND_MAESTRO3_INPUT
1734 snd_m3_update_hw_volume((unsigned long)chip);
1735 #else
1736 tasklet_schedule(&chip->hwvol_tq);
1737 #endif
1738
1739 /*
1740 * ack an assp int if its running
1741 * and has an int pending
1742 */
1743 if (status & ASSP_INT_PENDING) {
1744 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1745 if (!(ctl & STOP_ASSP_CLOCK)) {
1746 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1747 if (ctl & DSP2HOST_REQ_TIMER) {
1748 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1749 /* update adc/dac info if it was a timer int */
1750 spin_lock(&chip->reg_lock);
1751 for (i = 0; i < chip->num_substreams; i++) {
1752 struct m3_dma *s = &chip->substreams[i];
1753 if (s->running)
1754 snd_m3_update_ptr(chip, s);
1755 }
1756 spin_unlock(&chip->reg_lock);
1757 }
1758 }
1759 }
1760
1761 #if 0 /* TODO: not supported yet */
1762 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1763 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1764 #endif
1765
1766 /* ack ints */
1767 outb(status, chip->iobase + HOST_INT_STATUS);
1768
1769 return IRQ_HANDLED;
1770 }
1771
1772
1773 /*
1774 */
1775
1776 static struct snd_pcm_hardware snd_m3_playback =
1777 {
1778 .info = (SNDRV_PCM_INFO_MMAP |
1779 SNDRV_PCM_INFO_INTERLEAVED |
1780 SNDRV_PCM_INFO_MMAP_VALID |
1781 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1782 /*SNDRV_PCM_INFO_PAUSE |*/
1783 SNDRV_PCM_INFO_RESUME),
1784 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1785 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1786 .rate_min = 8000,
1787 .rate_max = 48000,
1788 .channels_min = 1,
1789 .channels_max = 2,
1790 .buffer_bytes_max = (512*1024),
1791 .period_bytes_min = 64,
1792 .period_bytes_max = (512*1024),
1793 .periods_min = 1,
1794 .periods_max = 1024,
1795 };
1796
1797 static struct snd_pcm_hardware snd_m3_capture =
1798 {
1799 .info = (SNDRV_PCM_INFO_MMAP |
1800 SNDRV_PCM_INFO_INTERLEAVED |
1801 SNDRV_PCM_INFO_MMAP_VALID |
1802 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1803 /*SNDRV_PCM_INFO_PAUSE |*/
1804 SNDRV_PCM_INFO_RESUME),
1805 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1806 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1807 .rate_min = 8000,
1808 .rate_max = 48000,
1809 .channels_min = 1,
1810 .channels_max = 2,
1811 .buffer_bytes_max = (512*1024),
1812 .period_bytes_min = 64,
1813 .period_bytes_max = (512*1024),
1814 .periods_min = 1,
1815 .periods_max = 1024,
1816 };
1817
1818
1819 /*
1820 */
1821
1822 static int
1823 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1824 {
1825 int i;
1826 struct m3_dma *s;
1827
1828 spin_lock_irq(&chip->reg_lock);
1829 for (i = 0; i < chip->num_substreams; i++) {
1830 s = &chip->substreams[i];
1831 if (! s->opened)
1832 goto __found;
1833 }
1834 spin_unlock_irq(&chip->reg_lock);
1835 return -ENOMEM;
1836 __found:
1837 s->opened = 1;
1838 s->running = 0;
1839 spin_unlock_irq(&chip->reg_lock);
1840
1841 subs->runtime->private_data = s;
1842 s->substream = subs;
1843
1844 /* set list owners */
1845 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1846 s->index_list[0] = &chip->mixer_list;
1847 } else
1848 s->index_list[0] = &chip->adc1_list;
1849 s->index_list[1] = &chip->msrc_list;
1850 s->index_list[2] = &chip->dma_list;
1851
1852 return 0;
1853 }
1854
1855 static void
1856 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1857 {
1858 struct m3_dma *s = subs->runtime->private_data;
1859
1860 if (s == NULL)
1861 return; /* not opened properly */
1862
1863 spin_lock_irq(&chip->reg_lock);
1864 if (s->substream && s->running)
1865 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1866 if (s->in_lists) {
1867 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1868 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1869 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1870 s->in_lists = 0;
1871 }
1872 s->running = 0;
1873 s->opened = 0;
1874 spin_unlock_irq(&chip->reg_lock);
1875 }
1876
1877 static int
1878 snd_m3_playback_open(struct snd_pcm_substream *subs)
1879 {
1880 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1881 struct snd_pcm_runtime *runtime = subs->runtime;
1882 int err;
1883
1884 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1885 return err;
1886
1887 runtime->hw = snd_m3_playback;
1888
1889 return 0;
1890 }
1891
1892 static int
1893 snd_m3_playback_close(struct snd_pcm_substream *subs)
1894 {
1895 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1896
1897 snd_m3_substream_close(chip, subs);
1898 return 0;
1899 }
1900
1901 static int
1902 snd_m3_capture_open(struct snd_pcm_substream *subs)
1903 {
1904 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1905 struct snd_pcm_runtime *runtime = subs->runtime;
1906 int err;
1907
1908 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1909 return err;
1910
1911 runtime->hw = snd_m3_capture;
1912
1913 return 0;
1914 }
1915
1916 static int
1917 snd_m3_capture_close(struct snd_pcm_substream *subs)
1918 {
1919 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1920
1921 snd_m3_substream_close(chip, subs);
1922 return 0;
1923 }
1924
1925 /*
1926 * create pcm instance
1927 */
1928
1929 static struct snd_pcm_ops snd_m3_playback_ops = {
1930 .open = snd_m3_playback_open,
1931 .close = snd_m3_playback_close,
1932 .ioctl = snd_pcm_lib_ioctl,
1933 .hw_params = snd_m3_pcm_hw_params,
1934 .hw_free = snd_m3_pcm_hw_free,
1935 .prepare = snd_m3_pcm_prepare,
1936 .trigger = snd_m3_pcm_trigger,
1937 .pointer = snd_m3_pcm_pointer,
1938 };
1939
1940 static struct snd_pcm_ops snd_m3_capture_ops = {
1941 .open = snd_m3_capture_open,
1942 .close = snd_m3_capture_close,
1943 .ioctl = snd_pcm_lib_ioctl,
1944 .hw_params = snd_m3_pcm_hw_params,
1945 .hw_free = snd_m3_pcm_hw_free,
1946 .prepare = snd_m3_pcm_prepare,
1947 .trigger = snd_m3_pcm_trigger,
1948 .pointer = snd_m3_pcm_pointer,
1949 };
1950
1951 static int __devinit
1952 snd_m3_pcm(struct snd_m3 * chip, int device)
1953 {
1954 struct snd_pcm *pcm;
1955 int err;
1956
1957 err = snd_pcm_new(chip->card, chip->card->driver, device,
1958 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1959 if (err < 0)
1960 return err;
1961
1962 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1963 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1964
1965 pcm->private_data = chip;
1966 pcm->info_flags = 0;
1967 strcpy(pcm->name, chip->card->driver);
1968 chip->pcm = pcm;
1969
1970 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1971 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1972
1973 return 0;
1974 }
1975
1976
1977 /*
1978 * ac97 interface
1979 */
1980
1981 /*
1982 * Wait for the ac97 serial bus to be free.
1983 * return nonzero if the bus is still busy.
1984 */
1985 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1986 {
1987 int i = 10000;
1988
1989 do {
1990 if (! (snd_m3_inb(chip, 0x30) & 1))
1991 return 0;
1992 cpu_relax();
1993 } while (i-- > 0);
1994
1995 snd_printk(KERN_ERR "ac97 serial bus busy\n");
1996 return 1;
1997 }
1998
1999 static unsigned short
2000 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
2001 {
2002 struct snd_m3 *chip = ac97->private_data;
2003 #ifndef CONFIG_SND_MAESTRO3_INPUT
2004 unsigned long flags;
2005 #endif
2006 unsigned short data = 0xffff;
2007
2008 if (snd_m3_ac97_wait(chip))
2009 goto fail;
2010 #ifndef CONFIG_SND_MAESTRO3_INPUT
2011 spin_lock_irqsave(&chip->ac97_lock, flags);
2012 #endif
2013 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
2014 if (snd_m3_ac97_wait(chip))
2015 goto fail_unlock;
2016 data = snd_m3_inw(chip, CODEC_DATA);
2017 fail_unlock:
2018 #ifndef CONFIG_SND_MAESTRO3_INPUT
2019 spin_unlock_irqrestore(&chip->ac97_lock, flags);
2020 #endif
2021 fail:
2022 return data;
2023 }
2024
2025 static void
2026 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
2027 {
2028 struct snd_m3 *chip = ac97->private_data;
2029 #ifndef CONFIG_SND_MAESTRO3_INPUT
2030 unsigned long flags;
2031 #endif
2032
2033 if (snd_m3_ac97_wait(chip))
2034 return;
2035 #ifndef CONFIG_SND_MAESTRO3_INPUT
2036 spin_lock_irqsave(&chip->ac97_lock, flags);
2037 #endif
2038 snd_m3_outw(chip, val, CODEC_DATA);
2039 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
2040 #ifndef CONFIG_SND_MAESTRO3_INPUT
2041 spin_unlock_irqrestore(&chip->ac97_lock, flags);
2042 #endif
2043 }
2044
2045
2046 static void snd_m3_remote_codec_config(int io, int isremote)
2047 {
2048 isremote = isremote ? 1 : 0;
2049
2050 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
2051 io + RING_BUS_CTRL_B);
2052 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
2053 io + SDO_OUT_DEST_CTRL);
2054 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
2055 io + SDO_IN_DEST_CTRL);
2056 }
2057
2058 /*
2059 * hack, returns non zero on err
2060 */
2061 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
2062 {
2063 u16 ret;
2064
2065 if (snd_m3_ac97_wait(chip))
2066 return 1;
2067
2068 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2069
2070 if (snd_m3_ac97_wait(chip))
2071 return 1;
2072
2073 ret = snd_m3_inw(chip, 0x32);
2074
2075 return (ret == 0) || (ret == 0xffff);
2076 }
2077
2078 static void snd_m3_ac97_reset(struct snd_m3 *chip)
2079 {
2080 u16 dir;
2081 int delay1 = 0, delay2 = 0, i;
2082 int io = chip->iobase;
2083
2084 if (chip->allegro_flag) {
2085 /*
2086 * the onboard codec on the allegro seems
2087 * to want to wait a very long time before
2088 * coming back to life
2089 */
2090 delay1 = 50;
2091 delay2 = 800;
2092 } else {
2093 /* maestro3 */
2094 delay1 = 20;
2095 delay2 = 500;
2096 }
2097
2098 for (i = 0; i < 5; i++) {
2099 dir = inw(io + GPIO_DIRECTION);
2100 if (!chip->irda_workaround)
2101 dir |= 0x10; /* assuming pci bus master? */
2102
2103 snd_m3_remote_codec_config(io, 0);
2104
2105 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2106 udelay(20);
2107
2108 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2109 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2110 outw(0, io + GPIO_DATA);
2111 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2112
2113 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2114
2115 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2116 udelay(5);
2117 /* ok, bring back the ac-link */
2118 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2119 outw(~0, io + GPIO_MASK);
2120
2121 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2122
2123 if (! snd_m3_try_read_vendor(chip))
2124 break;
2125
2126 delay1 += 10;
2127 delay2 += 100;
2128
2129 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2130 delay1, delay2);
2131 }
2132
2133 #if 0
2134 /* more gung-ho reset that doesn't
2135 * seem to work anywhere :)
2136 */
2137 tmp = inw(io + RING_BUS_CTRL_A);
2138 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2139 msleep(20);
2140 outw(tmp, io + RING_BUS_CTRL_A);
2141 msleep(50);
2142 #endif
2143 }
2144
2145 static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2146 {
2147 struct snd_ac97_bus *pbus;
2148 struct snd_ac97_template ac97;
2149 #ifndef CONFIG_SND_MAESTRO3_INPUT
2150 struct snd_ctl_elem_id elem_id;
2151 #endif
2152 int err;
2153 static struct snd_ac97_bus_ops ops = {
2154 .write = snd_m3_ac97_write,
2155 .read = snd_m3_ac97_read,
2156 };
2157
2158 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2159 return err;
2160
2161 memset(&ac97, 0, sizeof(ac97));
2162 ac97.private_data = chip;
2163 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2164 return err;
2165
2166 /* seems ac97 PCM needs initialization.. hack hack.. */
2167 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2168 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2169 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2170
2171 #ifndef CONFIG_SND_MAESTRO3_INPUT
2172 memset(&elem_id, 0, sizeof(elem_id));
2173 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2174 strcpy(elem_id.name, "Master Playback Switch");
2175 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2176 memset(&elem_id, 0, sizeof(elem_id));
2177 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2178 strcpy(elem_id.name, "Master Playback Volume");
2179 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2180 #endif
2181
2182 return 0;
2183 }
2184
2185
2186 /*
2187 * initialize ASSP
2188 */
2189
2190 #define MINISRC_LPF_LEN 10
2191 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2192 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2193 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2194 };
2195
2196 static void snd_m3_assp_init(struct snd_m3 *chip)
2197 {
2198 unsigned int i;
2199 const u16 *data;
2200
2201 /* zero kernel data */
2202 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2203 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2204 KDATA_BASE_ADDR + i, 0);
2205
2206 /* zero mixer data? */
2207 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2208 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2209 KDATA_BASE_ADDR2 + i, 0);
2210
2211 /* init dma pointer */
2212 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2213 KDATA_CURRENT_DMA,
2214 KDATA_DMA_XFER0);
2215
2216 /* write kernel into code memory.. */
2217 data = (const u16 *)chip->assp_kernel_image->data;
2218 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2219 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2220 REV_B_CODE_MEMORY_BEGIN + i,
2221 le16_to_cpu(data[i]));
2222 }
2223
2224 /*
2225 * We only have this one client and we know that 0x400
2226 * is free in our kernel's mem map, so lets just
2227 * drop it there. It seems that the minisrc doesn't
2228 * need vectors, so we won't bother with them..
2229 */
2230 data = (const u16 *)chip->assp_minisrc_image->data;
2231 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2232 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2233 0x400 + i, le16_to_cpu(data[i]));
2234 }
2235
2236 /*
2237 * write the coefficients for the low pass filter?
2238 */
2239 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2240 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2241 0x400 + MINISRC_COEF_LOC + i,
2242 minisrc_lpf[i]);
2243 }
2244
2245 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2246 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2247 0x8000);
2248
2249 /*
2250 * the minisrc is the only thing on
2251 * our task list..
2252 */
2253 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2254 KDATA_TASK0,
2255 0x400);
2256
2257 /*
2258 * init the mixer number..
2259 */
2260
2261 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2262 KDATA_MIXER_TASK_NUMBER,0);
2263
2264 /*
2265 * EXTREME KERNEL MASTER VOLUME
2266 */
2267 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2268 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2269 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2270 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2271
2272 chip->mixer_list.curlen = 0;
2273 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2274 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2275 chip->adc1_list.curlen = 0;
2276 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2277 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2278 chip->dma_list.curlen = 0;
2279 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2280 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2281 chip->msrc_list.curlen = 0;
2282 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2283 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2284 }
2285
2286
2287 static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2288 {
2289 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2290 MINISRC_IN_BUFFER_SIZE / 2 +
2291 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2292 int address, i;
2293
2294 /*
2295 * the revb memory map has 0x1100 through 0x1c00
2296 * free.
2297 */
2298
2299 /*
2300 * align instance address to 256 bytes so that its
2301 * shifted list address is aligned.
2302 * list address = (mem address >> 1) >> 7;
2303 */
2304 data_bytes = ALIGN(data_bytes, 256);
2305 address = 0x1100 + ((data_bytes/2) * index);
2306
2307 if ((address + (data_bytes/2)) >= 0x1c00) {
2308 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2309 data_bytes, index, address);
2310 return -ENOMEM;
2311 }
2312
2313 s->number = index;
2314 s->inst.code = 0x400;
2315 s->inst.data = address;
2316
2317 for (i = data_bytes / 2; i > 0; address++, i--) {
2318 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2319 address, 0);
2320 }
2321
2322 return 0;
2323 }
2324
2325
2326 /*
2327 * this works for the reference board, have to find
2328 * out about others
2329 *
2330 * this needs more magic for 4 speaker, but..
2331 */
2332 static void
2333 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2334 {
2335 int io = chip->iobase;
2336 u16 gpo, polarity;
2337
2338 if (! chip->external_amp)
2339 return;
2340
2341 polarity = enable ? 0 : 1;
2342 polarity = polarity << chip->amp_gpio;
2343 gpo = 1 << chip->amp_gpio;
2344
2345 outw(~gpo, io + GPIO_MASK);
2346
2347 outw(inw(io + GPIO_DIRECTION) | gpo,
2348 io + GPIO_DIRECTION);
2349
2350 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2351 io + GPIO_DATA);
2352
2353 outw(0xffff, io + GPIO_MASK);
2354 }
2355
2356 static void
2357 snd_m3_hv_init(struct snd_m3 *chip)
2358 {
2359 unsigned long io = chip->iobase;
2360 u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2361
2362 if (!chip->is_omnibook)
2363 return;
2364
2365 /*
2366 * Volume buttons on some HP OmniBook laptops
2367 * require some GPIO magic to work correctly.
2368 */
2369 outw(0xffff, io + GPIO_MASK);
2370 outw(0x0000, io + GPIO_DATA);
2371
2372 outw(~val, io + GPIO_MASK);
2373 outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2374 outw(val, io + GPIO_MASK);
2375
2376 outw(0xffff, io + GPIO_MASK);
2377 }
2378
2379 static int
2380 snd_m3_chip_init(struct snd_m3 *chip)
2381 {
2382 struct pci_dev *pcidev = chip->pci;
2383 unsigned long io = chip->iobase;
2384 u32 n;
2385 u16 w;
2386 u8 t; /* makes as much sense as 'n', no? */
2387
2388 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2389 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2390 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2391 DISABLE_LEGACY);
2392 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2393
2394 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2395 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2396 n |= chip->hv_config;
2397 /* For some reason we must always use reduced debounce. */
2398 n |= REDUCED_DEBOUNCE;
2399 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2400 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2401
2402 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2403 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2404 n &= ~INT_CLK_SELECT;
2405 if (!chip->allegro_flag) {
2406 n &= ~INT_CLK_MULT_ENABLE;
2407 n |= INT_CLK_SRC_NOT_PCI;
2408 }
2409 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2410 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2411
2412 if (chip->allegro_flag) {
2413 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2414 n |= IN_CLK_12MHZ_SELECT;
2415 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2416 }
2417
2418 t = inb(chip->iobase + ASSP_CONTROL_A);
2419 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2420 t |= ASSP_CLK_49MHZ_SELECT;
2421 t |= ASSP_0_WS_ENABLE;
2422 outb(t, chip->iobase + ASSP_CONTROL_A);
2423
2424 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2425 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2426
2427 outb(0x00, io + HARDWARE_VOL_CTRL);
2428 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2429 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2430 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2431 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2432
2433 return 0;
2434 }
2435
2436 static void
2437 snd_m3_enable_ints(struct snd_m3 *chip)
2438 {
2439 unsigned long io = chip->iobase;
2440 unsigned short val;
2441
2442 /* TODO: MPU401 not supported yet */
2443 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2444 if (chip->hv_config & HV_CTRL_ENABLE)
2445 val |= HV_INT_ENABLE;
2446 outb(val, chip->iobase + HOST_INT_STATUS);
2447 outw(val, io + HOST_INT_CTRL);
2448 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2449 io + ASSP_CONTROL_C);
2450 }
2451
2452
2453 /*
2454 */
2455
2456 static int snd_m3_free(struct snd_m3 *chip)
2457 {
2458 struct m3_dma *s;
2459 int i;
2460
2461 #ifdef CONFIG_SND_MAESTRO3_INPUT
2462 if (chip->input_dev)
2463 input_unregister_device(chip->input_dev);
2464 #endif
2465
2466 if (chip->substreams) {
2467 spin_lock_irq(&chip->reg_lock);
2468 for (i = 0; i < chip->num_substreams; i++) {
2469 s = &chip->substreams[i];
2470 /* check surviving pcms; this should not happen though.. */
2471 if (s->substream && s->running)
2472 snd_m3_pcm_stop(chip, s, s->substream);
2473 }
2474 spin_unlock_irq(&chip->reg_lock);
2475 kfree(chip->substreams);
2476 }
2477 if (chip->iobase) {
2478 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2479 }
2480
2481 #ifdef CONFIG_PM
2482 vfree(chip->suspend_mem);
2483 #endif
2484
2485 if (chip->irq >= 0)
2486 free_irq(chip->irq, chip);
2487
2488 if (chip->iobase)
2489 pci_release_regions(chip->pci);
2490
2491 release_firmware(chip->assp_kernel_image);
2492 release_firmware(chip->assp_minisrc_image);
2493
2494 pci_disable_device(chip->pci);
2495 kfree(chip);
2496 return 0;
2497 }
2498
2499
2500 /*
2501 * APM support
2502 */
2503 #ifdef CONFIG_PM
2504 static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2505 {
2506 struct snd_card *card = pci_get_drvdata(pci);
2507 struct snd_m3 *chip = card->private_data;
2508 int i, dsp_index;
2509
2510 if (chip->suspend_mem == NULL)
2511 return 0;
2512
2513 chip->in_suspend = 1;
2514 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2515 snd_pcm_suspend_all(chip->pcm);
2516 snd_ac97_suspend(chip->ac97);
2517
2518 msleep(10); /* give the assp a chance to idle.. */
2519
2520 snd_m3_assp_halt(chip);
2521
2522 /* save dsp image */
2523 dsp_index = 0;
2524 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2525 chip->suspend_mem[dsp_index++] =
2526 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2527 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2528 chip->suspend_mem[dsp_index++] =
2529 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2530
2531 pci_disable_device(pci);
2532 pci_save_state(pci);
2533 pci_set_power_state(pci, pci_choose_state(pci, state));
2534 return 0;
2535 }
2536
2537 static int m3_resume(struct pci_dev *pci)
2538 {
2539 struct snd_card *card = pci_get_drvdata(pci);
2540 struct snd_m3 *chip = card->private_data;
2541 int i, dsp_index;
2542
2543 if (chip->suspend_mem == NULL)
2544 return 0;
2545
2546 pci_set_power_state(pci, PCI_D0);
2547 pci_restore_state(pci);
2548 if (pci_enable_device(pci) < 0) {
2549 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2550 "disabling device\n");
2551 snd_card_disconnect(card);
2552 return -EIO;
2553 }
2554 pci_set_master(pci);
2555
2556 /* first lets just bring everything back. .*/
2557 snd_m3_outw(chip, 0, 0x54);
2558 snd_m3_outw(chip, 0, 0x56);
2559
2560 snd_m3_chip_init(chip);
2561 snd_m3_assp_halt(chip);
2562 snd_m3_ac97_reset(chip);
2563
2564 /* restore dsp image */
2565 dsp_index = 0;
2566 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2567 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2568 chip->suspend_mem[dsp_index++]);
2569 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2570 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2571 chip->suspend_mem[dsp_index++]);
2572
2573 /* tell the dma engine to restart itself */
2574 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2575 KDATA_DMA_ACTIVE, 0);
2576
2577 /* restore ac97 registers */
2578 snd_ac97_resume(chip->ac97);
2579
2580 snd_m3_assp_continue(chip);
2581 snd_m3_enable_ints(chip);
2582 snd_m3_amp_enable(chip, 1);
2583
2584 snd_m3_hv_init(chip);
2585
2586 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2587 chip->in_suspend = 0;
2588 return 0;
2589 }
2590 #endif /* CONFIG_PM */
2591
2592 #ifdef CONFIG_SND_MAESTRO3_INPUT
2593 static int __devinit snd_m3_input_register(struct snd_m3 *chip)
2594 {
2595 struct input_dev *input_dev;
2596 int err;
2597
2598 input_dev = input_allocate_device();
2599 if (!input_dev)
2600 return -ENOMEM;
2601
2602 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2603 pci_name(chip->pci));
2604
2605 input_dev->name = chip->card->driver;
2606 input_dev->phys = chip->phys;
2607 input_dev->id.bustype = BUS_PCI;
2608 input_dev->id.vendor = chip->pci->vendor;
2609 input_dev->id.product = chip->pci->device;
2610 input_dev->dev.parent = &chip->pci->dev;
2611
2612 __set_bit(EV_KEY, input_dev->evbit);
2613 __set_bit(KEY_MUTE, input_dev->keybit);
2614 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2615 __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2616
2617 err = input_register_device(input_dev);
2618 if (err) {
2619 input_free_device(input_dev);
2620 return err;
2621 }
2622
2623 chip->input_dev = input_dev;
2624 return 0;
2625 }
2626 #endif /* CONFIG_INPUT */
2627
2628 /*
2629 */
2630
2631 static int snd_m3_dev_free(struct snd_device *device)
2632 {
2633 struct snd_m3 *chip = device->device_data;
2634 return snd_m3_free(chip);
2635 }
2636
2637 static int __devinit
2638 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2639 int enable_amp,
2640 int amp_gpio,
2641 struct snd_m3 **chip_ret)
2642 {
2643 struct snd_m3 *chip;
2644 int i, err;
2645 const struct snd_pci_quirk *quirk;
2646 static struct snd_device_ops ops = {
2647 .dev_free = snd_m3_dev_free,
2648 };
2649
2650 *chip_ret = NULL;
2651
2652 if (pci_enable_device(pci))
2653 return -EIO;
2654
2655 /* check, if we can restrict PCI DMA transfers to 28 bits */
2656 if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
2657 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
2658 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2659 pci_disable_device(pci);
2660 return -ENXIO;
2661 }
2662
2663 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2664 if (chip == NULL) {
2665 pci_disable_device(pci);
2666 return -ENOMEM;
2667 }
2668
2669 spin_lock_init(&chip->reg_lock);
2670 #ifndef CONFIG_SND_MAESTRO3_INPUT
2671 spin_lock_init(&chip->ac97_lock);
2672 #endif
2673
2674 switch (pci->device) {
2675 case PCI_DEVICE_ID_ESS_ALLEGRO:
2676 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2677 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2678 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2679 chip->allegro_flag = 1;
2680 break;
2681 }
2682
2683 chip->card = card;
2684 chip->pci = pci;
2685 chip->irq = -1;
2686
2687 chip->external_amp = enable_amp;
2688 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2689 chip->amp_gpio = amp_gpio;
2690 else {
2691 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2692 if (quirk) {
2693 snd_printdd(KERN_INFO "maestro3: set amp-gpio "
2694 "for '%s'\n", quirk->name);
2695 chip->amp_gpio = quirk->value;
2696 } else if (chip->allegro_flag)
2697 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2698 else /* presumably this is for all 'maestro3's.. */
2699 chip->amp_gpio = GPO_EXT_AMP_M3;
2700 }
2701
2702 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2703 if (quirk) {
2704 snd_printdd(KERN_INFO "maestro3: enabled irda workaround "
2705 "for '%s'\n", quirk->name);
2706 chip->irda_workaround = 1;
2707 }
2708 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2709 if (quirk)
2710 chip->hv_config = quirk->value;
2711 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2712 chip->is_omnibook = 1;
2713
2714 chip->num_substreams = NR_DSPS;
2715 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2716 GFP_KERNEL);
2717 if (chip->substreams == NULL) {
2718 kfree(chip);
2719 pci_disable_device(pci);
2720 return -ENOMEM;
2721 }
2722
2723 err = request_firmware(&chip->assp_kernel_image,
2724 "ess/maestro3_assp_kernel.fw", &pci->dev);
2725 if (err < 0) {
2726 snd_m3_free(chip);
2727 return err;
2728 }
2729
2730 err = request_firmware(&chip->assp_minisrc_image,
2731 "ess/maestro3_assp_minisrc.fw", &pci->dev);
2732 if (err < 0) {
2733 snd_m3_free(chip);
2734 return err;
2735 }
2736
2737 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2738 snd_m3_free(chip);
2739 return err;
2740 }
2741 chip->iobase = pci_resource_start(pci, 0);
2742
2743 /* just to be sure */
2744 pci_set_master(pci);
2745
2746 snd_m3_chip_init(chip);
2747 snd_m3_assp_halt(chip);
2748
2749 snd_m3_ac97_reset(chip);
2750
2751 snd_m3_amp_enable(chip, 1);
2752
2753 snd_m3_hv_init(chip);
2754
2755 #ifndef CONFIG_SND_MAESTRO3_INPUT
2756 tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2757 #endif
2758
2759 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2760 card->driver, chip)) {
2761 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2762 snd_m3_free(chip);
2763 return -ENOMEM;
2764 }
2765 chip->irq = pci->irq;
2766
2767 #ifdef CONFIG_PM
2768 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2769 if (chip->suspend_mem == NULL)
2770 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2771 #endif
2772
2773 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2774 snd_m3_free(chip);
2775 return err;
2776 }
2777
2778 if ((err = snd_m3_mixer(chip)) < 0)
2779 return err;
2780
2781 for (i = 0; i < chip->num_substreams; i++) {
2782 struct m3_dma *s = &chip->substreams[i];
2783 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2784 return err;
2785 }
2786
2787 if ((err = snd_m3_pcm(chip, 0)) < 0)
2788 return err;
2789
2790 #ifdef CONFIG_SND_MAESTRO3_INPUT
2791 if (chip->hv_config & HV_CTRL_ENABLE) {
2792 err = snd_m3_input_register(chip);
2793 if (err)
2794 snd_printk(KERN_WARNING "Input device registration "
2795 "failed with error %i", err);
2796 }
2797 #endif
2798
2799 snd_m3_enable_ints(chip);
2800 snd_m3_assp_continue(chip);
2801
2802 snd_card_set_dev(card, &pci->dev);
2803
2804 *chip_ret = chip;
2805
2806 return 0;
2807 }
2808
2809 /*
2810 */
2811 static int __devinit
2812 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2813 {
2814 static int dev;
2815 struct snd_card *card;
2816 struct snd_m3 *chip;
2817 int err;
2818
2819 /* don't pick up modems */
2820 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2821 return -ENODEV;
2822
2823 if (dev >= SNDRV_CARDS)
2824 return -ENODEV;
2825 if (!enable[dev]) {
2826 dev++;
2827 return -ENOENT;
2828 }
2829
2830 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2831 if (err < 0)
2832 return err;
2833
2834 switch (pci->device) {
2835 case PCI_DEVICE_ID_ESS_ALLEGRO:
2836 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2837 strcpy(card->driver, "Allegro");
2838 break;
2839 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2840 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2841 strcpy(card->driver, "Canyon3D-2");
2842 break;
2843 default:
2844 strcpy(card->driver, "Maestro3");
2845 break;
2846 }
2847
2848 if ((err = snd_m3_create(card, pci,
2849 external_amp[dev],
2850 amp_gpio[dev],
2851 &chip)) < 0) {
2852 snd_card_free(card);
2853 return err;
2854 }
2855 card->private_data = chip;
2856
2857 sprintf(card->shortname, "ESS %s PCI", card->driver);
2858 sprintf(card->longname, "%s at 0x%lx, irq %d",
2859 card->shortname, chip->iobase, chip->irq);
2860
2861 if ((err = snd_card_register(card)) < 0) {
2862 snd_card_free(card);
2863 return err;
2864 }
2865
2866 #if 0 /* TODO: not supported yet */
2867 /* TODO enable MIDI IRQ and I/O */
2868 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2869 chip->iobase + MPU401_DATA_PORT,
2870 MPU401_INFO_INTEGRATED,
2871 chip->irq, 0, &chip->rmidi);
2872 if (err < 0)
2873 printk(KERN_WARNING "maestro3: no MIDI support.\n");
2874 #endif
2875
2876 pci_set_drvdata(pci, card);
2877 dev++;
2878 return 0;
2879 }
2880
2881 static void __devexit snd_m3_remove(struct pci_dev *pci)
2882 {
2883 snd_card_free(pci_get_drvdata(pci));
2884 pci_set_drvdata(pci, NULL);
2885 }
2886
2887 static struct pci_driver driver = {
2888 .name = "Maestro3",
2889 .id_table = snd_m3_ids,
2890 .probe = snd_m3_probe,
2891 .remove = __devexit_p(snd_m3_remove),
2892 #ifdef CONFIG_PM
2893 .suspend = m3_suspend,
2894 .resume = m3_resume,
2895 #endif
2896 };
2897
2898 static int __init alsa_card_m3_init(void)
2899 {
2900 return pci_register_driver(&driver);
2901 }
2902
2903 static void __exit alsa_card_m3_exit(void)
2904 {
2905 pci_unregister_driver(&driver);
2906 }
2907
2908 module_init(alsa_card_m3_init)
2909 module_exit(alsa_card_m3_exit)
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