drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /* statistics can be kept for for tuning/monitoring */
  25 struct ehci_stats {
  26         /* irq usage */
  27         unsigned long           normal;
  28         unsigned long           error;
  29         unsigned long           reclaim;
  30         unsigned long           lost_iaa;
  31
  32         /* termination of urbs from core */
  33         unsigned long           complete;
  34         unsigned long           unlink;
  35 };
  36
  37 /* ehci_hcd->lock guards shared data against other CPUs:
  38  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  39  *   usb_host_endpoint: hcpriv
  40  *   ehci_qh:   qh_next, qtd_list
  41  *   ehci_qtd:  qtd_list
  42  *
  43  * Also, hold this lock when talking to HC registers or
  44  * when updating hw_* fields in shared qh/qtd/... structures.
  45  */
  46
  47 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  48
  49 struct ehci_hcd {                       /* one per controller */
  50         /* glue to PCI and HCD framework */
  51         struct ehci_caps __iomem *caps;
  52         struct ehci_regs __iomem *regs;
  53         struct ehci_dbg_port __iomem *debug;
  54
  55         __u32                   hcs_params;     /* cached register copy */
  56         spinlock_t              lock;
  57
  58         /* async schedule support */
  59         struct ehci_qh          *async;
  60         struct ehci_qh          *reclaim;
  61         unsigned                reclaim_ready : 1;
  62         unsigned                scanning : 1;
  63
  64         /* periodic schedule support */
  65 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  66         unsigned                periodic_size;
  67         __le32                  *periodic;      /* hw periodic table */
  68         dma_addr_t              periodic_dma;
  69         unsigned                i_thresh;       /* uframes HC might cache */
  70
  71         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  72         int                     next_uframe;    /* scan periodic, start here */
  73         unsigned                periodic_sched; /* periodic activity count */
  74
  75         /* per root hub port */
  76         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
  77
  78         /* per-HC memory pools (could be per-bus, but ...) */
  79         struct dma_pool         *qh_pool;       /* qh per active urb */
  80         struct dma_pool         *qtd_pool;      /* one or more per qh */
  81         struct dma_pool         *itd_pool;      /* itd per iso urb */
  82         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
  83
  84         struct timer_list       watchdog;
  85         struct notifier_block   reboot_notifier;
  86         unsigned long           actions;
  87         unsigned                stamp;
  88         unsigned long           next_statechange;
  89         u32                     command;
  90
  91         unsigned                is_tdi_rh_tt:1; /* TDI roothub with TT */
  92         unsigned                no_selective_suspend:1;
  93         u8                      sbrn;           /* packed release number */
  94
  95         /* irq statistics */
  96 #ifdef EHCI_STATS
  97         struct ehci_stats       stats;
  98 #       define COUNT(x) do { (x)++; } while (0)
  99 #else
 100 #       define COUNT(x) do {} while (0)
 101 #endif
 102 };
 103
 104 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 105 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 106 {
 107         return (struct ehci_hcd *) (hcd->hcd_priv);
 108 }
 109 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 110 {
 111         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 112 }
 113
 114
 115 enum ehci_timer_action {
 116         TIMER_IO_WATCHDOG,
 117         TIMER_IAA_WATCHDOG,
 118         TIMER_ASYNC_SHRINK,
 119         TIMER_ASYNC_OFF,
 120 };
 121
 122 static inline void
 123 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 124 {
 125         clear_bit (action, &ehci->actions);
 126 }
 127
 128 static inline void
 129 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
 130 {
 131         if (!test_and_set_bit (action, &ehci->actions)) {
 132                 unsigned long t;
 133
 134                 switch (action) {
 135                 case TIMER_IAA_WATCHDOG:
 136                         t = EHCI_IAA_JIFFIES;
 137                         break;
 138                 case TIMER_IO_WATCHDOG:
 139                         t = EHCI_IO_JIFFIES;
 140                         break;
 141                 case TIMER_ASYNC_OFF:
 142                         t = EHCI_ASYNC_JIFFIES;
 143                         break;
 144                 // case TIMER_ASYNC_SHRINK:
 145                 default:
 146                         t = EHCI_SHRINK_JIFFIES;
 147                         break;
 148                 }
 149                 t += jiffies;
 150                 // all timings except IAA watchdog can be overridden.
 151                 // async queue SHRINK often precedes IAA.  while it's ready
 152                 // to go OFF neither can matter, and afterwards the IO
 153                 // watchdog stops unless there's still periodic traffic.
 154                 if (action != TIMER_IAA_WATCHDOG
 155                                 && t > ehci->watchdog.expires
 156                                 && timer_pending (&ehci->watchdog))
 157                         return;
 158                 mod_timer (&ehci->watchdog, t);
 159         }
 160 }
 161
 162 /*-------------------------------------------------------------------------*/
 163
 164 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 165
 166 /* Section 2.2 Host Controller Capability Registers */
 167 struct ehci_caps {
 168         /* these fields are specified as 8 and 16 bit registers,
 169          * but some hosts can't perform 8 or 16 bit PCI accesses.
 170          */
 171         u32             hc_capbase;
 172 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
 173 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
 174         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 175 #define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
 176 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
 177 #define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
 178 #define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
 179 #define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
 180 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
 181 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
 182
 183         u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
 184 #define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
 185 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
 186 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
 187 #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
 188 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 189 #define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
 190         u8              portroute [8];   /* nibbles for routing - offset 0xC */
 191 } __attribute__ ((packed));
 192
 193
 194 /* Section 2.3 Host Controller Operational Registers */
 195 struct ehci_regs {
 196
 197         /* USBCMD: offset 0x00 */
 198         u32             command;
 199 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 200 #define CMD_PARK        (1<<11)         /* enable "park" on async qh */
 201 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
 202 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
 203 #define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
 204 #define CMD_ASE         (1<<5)          /* async schedule enable */
 205 #define CMD_PSE         (1<<4)          /* periodic schedule enable */
 206 /* 3:2 is periodic frame list size */
 207 #define CMD_RESET       (1<<1)          /* reset HC not bus */
 208 #define CMD_RUN         (1<<0)          /* start/stop HC */
 209
 210         /* USBSTS: offset 0x04 */
 211         u32             status;
 212 #define STS_ASS         (1<<15)         /* Async Schedule Status */
 213 #define STS_PSS         (1<<14)         /* Periodic Schedule Status */
 214 #define STS_RECL        (1<<13)         /* Reclamation */
 215 #define STS_HALT        (1<<12)         /* Not running (any reason) */
 216 /* some bits reserved */
 217         /* these STS_* flags are also intr_enable bits (USBINTR) */
 218 #define STS_IAA         (1<<5)          /* Interrupted on async advance */
 219 #define STS_FATAL       (1<<4)          /* such as some PCI access errors */
 220 #define STS_FLR         (1<<3)          /* frame list rolled over */
 221 #define STS_PCD         (1<<2)          /* port change detect */
 222 #define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
 223 #define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
 224
 225         /* USBINTR: offset 0x08 */
 226         u32             intr_enable;
 227
 228         /* FRINDEX: offset 0x0C */
 229         u32             frame_index;    /* current microframe number */
 230         /* CTRLDSSEGMENT: offset 0x10 */
 231         u32             segment;        /* address bits 63:32 if needed */
 232         /* PERIODICLISTBASE: offset 0x14 */
 233         u32             frame_list;     /* points to periodic list */
 234         /* ASYNCLISTADDR: offset 0x18 */
 235         u32             async_next;     /* address of next async queue head */
 236
 237         u32             reserved [9];
 238
 239         /* CONFIGFLAG: offset 0x40 */
 240         u32             configured_flag;
 241 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
 242
 243         /* PORTSC: offset 0x44 */
 244         u32             port_status [0];        /* up to N_PORTS */
 245 /* 31:23 reserved */
 246 #define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
 247 #define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
 248 #define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
 249 /* 19:16 for port testing */
 250 #define PORT_LED_OFF    (0<<14)
 251 #define PORT_LED_AMBER  (1<<14)
 252 #define PORT_LED_GREEN  (2<<14)
 253 #define PORT_LED_MASK   (3<<14)
 254 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
 255 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
 256 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
 257 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
 258 /* 9 reserved */
 259 #define PORT_RESET      (1<<8)          /* reset port */
 260 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 261 #define PORT_RESUME     (1<<6)          /* resume it */
 262 #define PORT_OCC        (1<<5)          /* over current change */
 263 #define PORT_OC         (1<<4)          /* over current active */
 264 #define PORT_PEC        (1<<3)          /* port enable change */
 265 #define PORT_PE         (1<<2)          /* port enable */
 266 #define PORT_CSC        (1<<1)          /* connect status change */
 267 #define PORT_CONNECT    (1<<0)          /* device connected */
 268 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
 269 } __attribute__ ((packed));
 270
 271 /* Appendix C, Debug port ... intended for use with special "debug devices"
 272  * that can help if there's no serial console.  (nonstandard enumeration.)
 273  */
 274 struct ehci_dbg_port {
 275         u32     control;
 276 #define DBGP_OWNER      (1<<30)
 277 #define DBGP_ENABLED    (1<<28)
 278 #define DBGP_DONE       (1<<16)
 279 #define DBGP_INUSE      (1<<10)
 280 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
 281 #       define DBGP_ERR_BAD     1
 282 #       define DBGP_ERR_SIGNAL  2
 283 #define DBGP_ERROR      (1<<6)
 284 #define DBGP_GO         (1<<5)
 285 #define DBGP_OUT        (1<<4)
 286 #define DBGP_LEN(x)     (((x)>>0)&0x0f)
 287         u32     pids;
 288 #define DBGP_PID_GET(x)         (((x)>>16)&0xff)
 289 #define DBGP_PID_SET(data,tok)  (((data)<<8)|(tok))
 290         u32     data03;
 291         u32     data47;
 292         u32     address;
 293 #define DBGP_EPADDR(dev,ep)     (((dev)<<8)|(ep))
 294 } __attribute__ ((packed));
 295
 296 /*-------------------------------------------------------------------------*/
 297
 298 #define QTD_NEXT(dma)   cpu_to_le32((u32)dma)
 299
 300 /*
 301  * EHCI Specification 0.95 Section 3.5
 302  * QTD: describe data transfer components (buffer, direction, ...)
 303  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 304  *
 305  * These are associated only with "QH" (Queue Head) structures,
 306  * used with control, bulk, and interrupt transfers.
 307  */
 308 struct ehci_qtd {
 309         /* first part defined by EHCI spec */
 310         __le32                  hw_next;          /* see EHCI 3.5.1 */
 311         __le32                  hw_alt_next;      /* see EHCI 3.5.2 */
 312         __le32                  hw_token;         /* see EHCI 3.5.3 */
 313 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 314 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 315 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 316 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 317 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 318 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 319 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 320 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 321 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 322 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 323 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 324 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 325 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 326         __le32                  hw_buf [5];        /* see EHCI 3.5.4 */
 327         __le32                  hw_buf_hi [5];        /* Appendix B */
 328
 329         /* the rest is HCD-private */
 330         dma_addr_t              qtd_dma;                /* qtd address */
 331         struct list_head        qtd_list;               /* sw qtd list */
 332         struct urb              *urb;                   /* qtd's urb */
 333         size_t                  length;                 /* length of buffer */
 334 } __attribute__ ((aligned (32)));
 335
 336 /* mask NakCnt+T in qh->hw_alt_next */
 337 #define QTD_MASK __constant_cpu_to_le32 (~0x1f)
 338
 339 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 340
 341 /*-------------------------------------------------------------------------*/
 342
 343 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 344 #define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1))
 345
 346 /* values for that type tag */
 347 #define Q_TYPE_ITD      __constant_cpu_to_le32 (0 << 1)
 348 #define Q_TYPE_QH       __constant_cpu_to_le32 (1 << 1)
 349 #define Q_TYPE_SITD     __constant_cpu_to_le32 (2 << 1)
 350 #define Q_TYPE_FSTN     __constant_cpu_to_le32 (3 << 1)
 351
 352 /* next async queue entry, or pointer to interrupt/periodic QH */
 353 #define QH_NEXT(dma)    (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
 354
 355 /* for periodic/async schedules and qtd lists, mark end of list */
 356 #define EHCI_LIST_END   __constant_cpu_to_le32(1) /* "null pointer" to hw */
 357
 358 /*
 359  * Entries in periodic shadow table are pointers to one of four kinds
 360  * of data structure.  That's dictated by the hardware; a type tag is
 361  * encoded in the low bits of the hardware's periodic schedule.  Use
 362  * Q_NEXT_TYPE to get the tag.
 363  *
 364  * For entries in the async schedule, the type tag always says "qh".
 365  */
 366 union ehci_shadow {
 367         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 368         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 369         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 370         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 371         __le32                  *hw_next;       /* (all types) */
 372         void                    *ptr;
 373 };
 374
 375 /*-------------------------------------------------------------------------*/
 376
 377 /*
 378  * EHCI Specification 0.95 Section 3.6
 379  * QH: describes control/bulk/interrupt endpoints
 380  * See Fig 3-7 "Queue Head Structure Layout".
 381  *
 382  * These appear in both the async and (for interrupt) periodic schedules.
 383  */
 384
 385 struct ehci_qh {
 386         /* first part defined by EHCI spec */
 387         __le32                  hw_next;         /* see EHCI 3.6.1 */
 388         __le32                  hw_info1;        /* see EHCI 3.6.2 */
 389 #define QH_HEAD         0x00008000
 390         __le32                  hw_info2;        /* see EHCI 3.6.2 */
 391 #define QH_SMASK        0x000000ff
 392 #define QH_CMASK        0x0000ff00
 393 #define QH_HUBADDR      0x007f0000
 394 #define QH_HUBPORT      0x3f800000
 395 #define QH_MULT         0xc0000000
 396         __le32                  hw_current;      /* qtd list - see EHCI 3.6.4 */
 397
 398         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 399         __le32                  hw_qtd_next;
 400         __le32                  hw_alt_next;
 401         __le32                  hw_token;
 402         __le32                  hw_buf [5];
 403         __le32                  hw_buf_hi [5];
 404
 405         /* the rest is HCD-private */
 406         dma_addr_t              qh_dma;         /* address of qh */
 407         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 408         struct list_head        qtd_list;       /* sw qtd list */
 409         struct ehci_qtd         *dummy;
 410         struct ehci_qh          *reclaim;       /* next to reclaim */
 411
 412         struct ehci_hcd         *ehci;
 413         struct kref             kref;
 414         unsigned                stamp;
 415
 416         u8                      qh_state;
 417 #define QH_STATE_LINKED         1               /* HC sees this */
 418 #define QH_STATE_UNLINK         2               /* HC may still see this */
 419 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 420 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 421 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 422
 423         /* periodic schedule info */
 424         u8                      usecs;          /* intr bandwidth */
 425         u8                      gap_uf;         /* uframes split/csplit gap */
 426         u8                      c_usecs;        /* ... split completion bw */
 427         u16                     tt_usecs;       /* tt downstream bandwidth */
 428         unsigned short          period;         /* polling interval */
 429         unsigned short          start;          /* where polling starts */
 430 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 431         struct usb_device       *dev;           /* access to TT */
 432 } __attribute__ ((aligned (32)));
 433
 434 /*-------------------------------------------------------------------------*/
 435
 436 /* description of one iso transaction (up to 3 KB data if highspeed) */
 437 struct ehci_iso_packet {
 438         /* These will be copied to iTD when scheduling */
 439         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 440         __le32                  transaction;    /* itd->hw_transaction[i] |= */
 441         u8                      cross;          /* buf crosses pages */
 442         /* for full speed OUT splits */
 443         u32                     buf1;
 444 };
 445
 446 /* temporary schedule data for packets from iso urbs (both speeds)
 447  * each packet is one logical usb transaction to the device (not TT),
 448  * beginning at stream->next_uframe
 449  */
 450 struct ehci_iso_sched {
 451         struct list_head        td_list;
 452         unsigned                span;
 453         struct ehci_iso_packet  packet [0];
 454 };
 455
 456 /*
 457  * ehci_iso_stream - groups all (s)itds for this endpoint.
 458  * acts like a qh would, if EHCI had them for ISO.
 459  */
 460 struct ehci_iso_stream {
 461         /* first two fields match QH, but info1 == 0 */
 462         __le32                  hw_next;
 463         __le32                  hw_info1;
 464
 465         u32                     refcount;
 466         u8                      bEndpointAddress;
 467         u8                      highspeed;
 468         u16                     depth;          /* depth in uframes */
 469         struct list_head        td_list;        /* queued itds/sitds */
 470         struct list_head        free_list;      /* list of unused itds/sitds */
 471         struct usb_device       *udev;
 472         struct usb_host_endpoint *ep;
 473
 474         /* output of (re)scheduling */
 475         unsigned long           start;          /* jiffies */
 476         unsigned long           rescheduled;
 477         int                     next_uframe;
 478         __le32                  splits;
 479
 480         /* the rest is derived from the endpoint descriptor,
 481          * trusting urb->interval == f(epdesc->bInterval) and
 482          * including the extra info for hw_bufp[0..2]
 483          */
 484         u8                      interval;
 485         u8                      usecs, c_usecs;
 486         u16                     tt_usecs;
 487         u16                     maxp;
 488         u16                     raw_mask;
 489         unsigned                bandwidth;
 490
 491         /* This is used to initialize iTD's hw_bufp fields */
 492         __le32                  buf0;
 493         __le32                  buf1;
 494         __le32                  buf2;
 495
 496         /* this is used to initialize sITD's tt info */
 497         __le32                  address;
 498 };
 499
 500 /*-------------------------------------------------------------------------*/
 501
 502 /*
 503  * EHCI Specification 0.95 Section 3.3
 504  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 505  *
 506  * Schedule records for high speed iso xfers
 507  */
 508 struct ehci_itd {
 509         /* first part defined by EHCI spec */
 510         __le32                  hw_next;           /* see EHCI 3.3.1 */
 511         __le32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 512 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 513 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 514 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 515 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 516 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 517 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 518
 519 #define ITD_ACTIVE      __constant_cpu_to_le32(EHCI_ISOC_ACTIVE)
 520
 521         __le32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 522         __le32                  hw_bufp_hi [7]; /* Appendix B */
 523
 524         /* the rest is HCD-private */
 525         dma_addr_t              itd_dma;        /* for this itd */
 526         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 527
 528         struct urb              *urb;
 529         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 530         struct list_head        itd_list;       /* list of stream's itds */
 531
 532         /* any/all hw_transactions here may be used by that urb */
 533         unsigned                frame;          /* where scheduled */
 534         unsigned                pg;
 535         unsigned                index[8];       /* in urb->iso_frame_desc */
 536         u8                      usecs[8];
 537 } __attribute__ ((aligned (32)));
 538
 539 /*-------------------------------------------------------------------------*/
 540
 541 /*
 542  * EHCI Specification 0.95 Section 3.4
 543  * siTD, aka split-transaction isochronous Transfer Descriptor
 544  *       ... describe full speed iso xfers through TT in hubs
 545  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 546  */
 547 struct ehci_sitd {
 548         /* first part defined by EHCI spec */
 549         __le32                  hw_next;
 550 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 551         __le32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 552         __le32                  hw_uframe;              /* EHCI table 3-10 */
 553         __le32                  hw_results;             /* EHCI table 3-11 */
 554 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 555 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 556 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 557 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 558 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 559 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 560 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 561 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 562 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 563 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 564
 565 #define SITD_ACTIVE     __constant_cpu_to_le32(SITD_STS_ACTIVE)
 566
 567         __le32                  hw_buf [2];             /* EHCI table 3-12 */
 568         __le32                  hw_backpointer;         /* EHCI table 3-13 */
 569         __le32                  hw_buf_hi [2];          /* Appendix B */
 570
 571         /* the rest is HCD-private */
 572         dma_addr_t              sitd_dma;
 573         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 574
 575         struct urb              *urb;
 576         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 577         struct list_head        sitd_list;      /* list of stream's sitds */
 578         unsigned                frame;
 579         unsigned                index;
 580 } __attribute__ ((aligned (32)));
 581
 582 /*-------------------------------------------------------------------------*/
 583
 584 /*
 585  * EHCI Specification 0.96 Section 3.7
 586  * Periodic Frame Span Traversal Node (FSTN)
 587  *
 588  * Manages split interrupt transactions (using TT) that span frame boundaries
 589  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 590  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 591  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 592  */
 593 struct ehci_fstn {
 594         __le32                  hw_next;        /* any periodic q entry */
 595         __le32                  hw_prev;        /* qh or EHCI_LIST_END */
 596
 597         /* the rest is HCD-private */
 598         dma_addr_t              fstn_dma;
 599         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 600 } __attribute__ ((aligned (32)));
 601
 602 /*-------------------------------------------------------------------------*/
 603
 604 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 605
 606 /*
 607  * Some EHCI controllers have a Transaction Translator built into the
 608  * root hub. This is a non-standard feature.  Each controller will need
 609  * to add code to the following inline functions, and call them as
 610  * needed (mostly in root hub code).
 611  */
 612
 613 #define ehci_is_TDI(e)                  ((e)->is_tdi_rh_tt)
 614
 615 /* Returns the speed of a device attached to a port on the root hub. */
 616 static inline unsigned int
 617 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 618 {
 619         if (ehci_is_TDI(ehci)) {
 620                 switch ((portsc>>26)&3) {
 621                 case 0:
 622                         return 0;
 623                 case 1:
 624                         return (1<<USB_PORT_FEAT_LOWSPEED);
 625                 case 2:
 626                 default:
 627                         return (1<<USB_PORT_FEAT_HIGHSPEED);
 628                 }
 629         }
 630         return (1<<USB_PORT_FEAT_HIGHSPEED);
 631 }
 632
 633 #else
 634
 635 #define ehci_is_TDI(e)                  (0)
 636
 637 #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
 638 #endif
 639
 640 /*-------------------------------------------------------------------------*/
 641
 642 #ifndef DEBUG
 643 #define STUB_DEBUG_FILES
 644 #endif  /* DEBUG */
 645
 646 /*-------------------------------------------------------------------------*/
 647
 648 #endif /* __LINUX_EHCI_HCD_H */