drivers/video/geode/lxfb_ops.c

   1 /* Geode LX framebuffer driver
   2  *
   3  * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/fb.h>
  14 #include <linux/uaccess.h>
  15 #include <linux/delay.h>
  16 #include <asm/geode.h>
  17
  18 #include "lxfb.h"
  19
  20 /* TODO
  21  * Support panel scaling
  22  * Add acceleration
  23  * Add support for interlacing (TV out)
  24  * Support compression
  25  */
  26
  27 /* This is the complete list of PLL frequencies that we can set -
  28  * we will choose the closest match to the incoming clock.
  29  * freq is the frequency of the dotclock * 1000 (for example,
  30  * 24823 = 24.983 Mhz).
  31  * pllval is the corresponding PLL value
  32 */
  33
  34 static const struct {
  35   unsigned int pllval;
  36   unsigned int freq;
  37 } pll_table[] = {
  38   { 0x000131AC,   6231 },
  39   { 0x0001215D,   6294 },
  40   { 0x00011087,   6750 },
  41   { 0x0001216C,   7081 },
  42   { 0x0001218D,   7140 },
  43   { 0x000110C9,   7800 },
  44   { 0x00013147,   7875 },
  45   { 0x000110A7,   8258 },
  46   { 0x00012159,   8778 },
  47   { 0x00014249,   8875 },
  48   { 0x00010057,   9000 },
  49   { 0x0001219A,   9472 },
  50   { 0x00012158,   9792 },
  51   { 0x00010045,  10000 },
  52   { 0x00010089,  10791 },
  53   { 0x000110E7,  11225 },
  54   { 0x00012136,  11430 },
  55   { 0x00013207,  12375 },
  56   { 0x00012187,  12500 },
  57   { 0x00014286,  14063 },
  58   { 0x000110E5,  15016 },
  59   { 0x00014214,  16250 },
  60   { 0x00011105,  17045 },
  61   { 0x000131E4,  18563 },
  62   { 0x00013183,  18750 },
  63   { 0x00014284,  19688 },
  64   { 0x00011104,  20400 },
  65   { 0x00016363,  23625 },
  66   { 0x00015303,  24380 },
  67   { 0x000031AC,  24923 },
  68   { 0x0000215D,  25175 },
  69   { 0x00001087,  27000 },
  70   { 0x0000216C,  28322 },
  71   { 0x0000218D,  28560 },
  72   { 0x00010041,  29913 },
  73   { 0x000010C9,  31200 },
  74   { 0x00003147,  31500 },
  75   { 0x000141A1,  32400 },
  76   { 0x000010A7,  33032 },
  77   { 0x00012182,  33375 },
  78   { 0x000141B1,  33750 },
  79   { 0x00002159,  35112 },
  80   { 0x00004249,  35500 },
  81   { 0x00000057,  36000 },
  82   { 0x000141E1,  37125 },
  83   { 0x0000219A,  37889 },
  84   { 0x00002158,  39168 },
  85   { 0x00000045,  40000 },
  86   { 0x000131A1,  40500 },
  87   { 0x00010061,  42301 },
  88   { 0x00000089,  43163 },
  89   { 0x00012151,  43875 },
  90   { 0x000010E7,  44900 },
  91   { 0x00002136,  45720 },
  92   { 0x000152E1,  47250 },
  93   { 0x00010071,  48000 },
  94   { 0x00003207,  49500 },
  95   { 0x00002187,  50000 },
  96   { 0x00014291,  50625 },
  97   { 0x00011101,  51188 },
  98   { 0x00017481,  54563 },
  99   { 0x00004286,  56250 },
 100   { 0x00014170,  57375 },
 101   { 0x00016210,  58500 },
 102   { 0x000010E5,  60065 },
 103   { 0x00013140,  62796 },
 104   { 0x00004214,  65000 },
 105   { 0x00016250,  65250 },
 106   { 0x00001105,  68179 },
 107   { 0x000141C0,  69600 },
 108   { 0x00015220,  70160 },
 109   { 0x00010050,  72000 },
 110   { 0x000031E4,  74250 },
 111   { 0x00003183,  75000 },
 112   { 0x00004284,  78750 },
 113   { 0x00012130,  80052 },
 114   { 0x00001104,  81600 },
 115   { 0x00006363,  94500 },
 116   { 0x00005303,  97520 },
 117   { 0x00002183, 100187 },
 118   { 0x00002122, 101420 },
 119   { 0x00001081, 108000 },
 120   { 0x00006201, 113310 },
 121   { 0x00000041, 119650 },
 122   { 0x000041A1, 129600 },
 123   { 0x00002182, 133500 },
 124   { 0x000041B1, 135000 },
 125   { 0x00000051, 144000 },
 126   { 0x000041E1, 148500 },
 127   { 0x000062D1, 157500 },
 128   { 0x000031A1, 162000 },
 129   { 0x00000061, 169203 },
 130   { 0x00004231, 172800 },
 131   { 0x00002151, 175500 },
 132   { 0x000052E1, 189000 },
 133   { 0x00000071, 192000 },
 134   { 0x00003201, 198000 },
 135   { 0x00004291, 202500 },
 136   { 0x00001101, 204750 },
 137   { 0x00007481, 218250 },
 138   { 0x00004170, 229500 },
 139   { 0x00006210, 234000 },
 140   { 0x00003140, 251182 },
 141   { 0x00006250, 261000 },
 142   { 0x000041C0, 278400 },
 143   { 0x00005220, 280640 },
 144   { 0x00000050, 288000 },
 145   { 0x000041E0, 297000 },
 146   { 0x00002130, 320207 }
 147 };
 148
 149
 150 static void lx_set_dotpll(u32 pllval)
 151 {
 152         u32 dotpll_lo, dotpll_hi;
 153         int i;
 154
 155         rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 156
 157         if ((dotpll_lo & GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
 158                 return;
 159
 160         dotpll_hi = pllval;
 161         dotpll_lo &= ~(GLCP_DOTPLL_BYPASS | GLCP_DOTPLL_HALFPIX);
 162         dotpll_lo |= GLCP_DOTPLL_RESET;
 163
 164         wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 165
 166         /* Wait 100us for the PLL to lock */
 167
 168         udelay(100);
 169
 170         /* Now, loop for the lock bit */
 171
 172         for (i = 0; i < 1000; i++) {
 173                 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 174                 if (dotpll_lo & GLCP_DOTPLL_LOCK)
 175                         break;
 176         }
 177
 178         /* Clear the reset bit */
 179
 180         dotpll_lo &= ~GLCP_DOTPLL_RESET;
 181         wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 182 }
 183
 184 /* Set the clock based on the frequency specified by the current mode */
 185
 186 static void lx_set_clock(struct fb_info *info)
 187 {
 188         unsigned int diff, min, best = 0;
 189         unsigned int freq, i;
 190
 191         freq = (unsigned int) (1000000000 / info->var.pixclock);
 192
 193         min = abs(pll_table[0].freq - freq);
 194
 195         for (i = 0; i < ARRAY_SIZE(pll_table); i++) {
 196                 diff = abs(pll_table[i].freq - freq);
 197                 if (diff < min) {
 198                         min = diff;
 199                         best = i;
 200                 }
 201         }
 202
 203         lx_set_dotpll(pll_table[best].pllval & 0x00017FFF);
 204 }
 205
 206 static void lx_graphics_disable(struct fb_info *info)
 207 {
 208         struct lxfb_par *par = info->par;
 209         unsigned int val, gcfg;
 210
 211         /* Note:  This assumes that the video is in a quitet state */
 212
 213         write_vp(par, VP_A1T, 0);
 214         write_vp(par, VP_A2T, 0);
 215         write_vp(par, VP_A3T, 0);
 216
 217         /* Turn off the VGA and video enable */
 218         val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE |
 219                         DC_GENERAL_CFG_VIDE);
 220
 221         write_dc(par, DC_GENERAL_CFG, val);
 222
 223         val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN;
 224         write_vp(par, VP_VCFG, val);
 225
 226         write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK |
 227                         DC_IRQ_STATUS | DC_IRQ_VIP_VSYNC_IRQ_STATUS);
 228
 229         val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN;
 230         write_dc(par, DC_GENLK_CTL, val);
 231
 232         val = read_dc(par, DC_CLR_KEY);
 233         write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN);
 234
 235         /* We don't actually blank the panel, due to the long latency
 236            involved with bringing it back */
 237
 238         val = read_vp(par, VP_MISC) | VP_MISC_DACPWRDN;
 239         write_vp(par, VP_MISC, val);
 240
 241         /* Turn off the display */
 242
 243         val = read_vp(par, VP_DCFG);
 244         write_vp(par, VP_DCFG, val & ~(VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
 245                         VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN));
 246
 247         gcfg = read_dc(par, DC_GENERAL_CFG);
 248         gcfg &= ~(DC_GENERAL_CFG_CMPE | DC_GENERAL_CFG_DECE);
 249         write_dc(par, DC_GENERAL_CFG, gcfg);
 250
 251         /* Turn off the TGEN */
 252         val = read_dc(par, DC_DISPLAY_CFG);
 253         val &= ~DC_DISPLAY_CFG_TGEN;
 254         write_dc(par, DC_DISPLAY_CFG, val);
 255
 256         /* Wait 1000 usecs to ensure that the TGEN is clear */
 257         udelay(1000);
 258
 259         /* Turn off the FIFO loader */
 260
 261         gcfg &= ~DC_GENERAL_CFG_DFLE;
 262         write_dc(par, DC_GENERAL_CFG, gcfg);
 263
 264         /* Lastly, wait for the GP to go idle */
 265
 266         do {
 267                 val = read_gp(par, GP_BLT_STATUS);
 268         } while ((val & GP_BLT_STATUS_PB) || !(val & GP_BLT_STATUS_CE));
 269 }
 270
 271 static void lx_graphics_enable(struct fb_info *info)
 272 {
 273         struct lxfb_par *par = info->par;
 274         u32 temp, config;
 275
 276         /* Set the video request register */
 277         write_vp(par, VP_VRR, 0);
 278
 279         /* Set up the polarities */
 280
 281         config = read_vp(par, VP_DCFG);
 282
 283         config &= ~(VP_DCFG_CRT_SYNC_SKW | VP_DCFG_PWR_SEQ_DELAY |
 284                         VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL);
 285
 286         config |= (VP_DCFG_CRT_SYNC_SKW_DEFAULT | VP_DCFG_PWR_SEQ_DELAY_DEFAULT
 287                         | VP_DCFG_GV_GAM);
 288
 289         if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 290                 config |= VP_DCFG_CRT_HSYNC_POL;
 291
 292         if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 293                 config |= VP_DCFG_CRT_VSYNC_POL;
 294
 295         if (par->output & OUTPUT_PANEL) {
 296                 u32 msrlo, msrhi;
 297
 298                 write_fp(par, FP_PT1, 0);
 299                 write_fp(par, FP_PT2, FP_PT2_SCRC);
 300                 write_fp(par, FP_DFC, FP_DFC_BC);
 301
 302                 msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW;
 303                 msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH;
 304
 305                 wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
 306         }
 307
 308         if (par->output & OUTPUT_CRT) {
 309                 config |= VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
 310                                 VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN;
 311         }
 312
 313         write_vp(par, VP_DCFG, config);
 314
 315         /* Turn the CRT dacs back on */
 316
 317         if (par->output & OUTPUT_CRT) {
 318                 temp = read_vp(par, VP_MISC);
 319                 temp &= ~(VP_MISC_DACPWRDN | VP_MISC_APWRDN);
 320                 write_vp(par, VP_MISC, temp);
 321         }
 322
 323         /* Turn the panel on (if it isn't already) */
 324
 325         if (par->output & OUTPUT_PANEL) {
 326                 temp = read_fp(par, FP_PM);
 327
 328                 if (!(temp & 0x09))
 329                         write_fp(par, FP_PM, temp | FP_PM_P);
 330         }
 331 }
 332
 333 unsigned int lx_framebuffer_size(void)
 334 {
 335         unsigned int val;
 336
 337         /* The frame buffer size is reported by a VSM in VSA II */
 338         /* Virtual Register Class    = 0x02                     */
 339         /* VG_MEM_SIZE (1MB units)   = 0x00                     */
 340
 341         outw(0xFC53, 0xAC1C);
 342         outw(0x0200, 0xAC1C);
 343
 344         val = (unsigned int)(inw(0xAC1E)) & 0xFE;
 345         return (val << 20);
 346 }
 347
 348 void lx_set_mode(struct fb_info *info)
 349 {
 350         struct lxfb_par *par = info->par;
 351         u64 msrval;
 352
 353         unsigned int max, dv, val, size;
 354
 355         unsigned int gcfg, dcfg;
 356         int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
 357         int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
 358
 359         /* Unlock the DC registers */
 360         write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
 361
 362         lx_graphics_disable(info);
 363
 364         lx_set_clock(info);
 365
 366         /* Set output mode */
 367
 368         rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
 369         msrval &= ~DF_CONFIG_OUTPUT_MASK;
 370
 371         if (par->output & OUTPUT_PANEL) {
 372                 msrval |= DF_OUTPUT_PANEL;
 373
 374                 if (par->output & OUTPUT_CRT)
 375                         msrval |= DF_SIMULTANEOUS_CRT_AND_FP;
 376                 else
 377                         msrval &= ~DF_SIMULTANEOUS_CRT_AND_FP;
 378         } else {
 379                 msrval |= DF_OUTPUT_CRT;
 380         }
 381
 382         wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
 383
 384         /* Clear the various buffers */
 385         /* FIXME:  Adjust for panning here */
 386
 387         write_dc(par, DC_FB_ST_OFFSET, 0);
 388         write_dc(par, DC_CB_ST_OFFSET, 0);
 389         write_dc(par, DC_CURS_ST_OFFSET, 0);
 390
 391         /* FIXME: Add support for interlacing */
 392         /* FIXME: Add support for scaling */
 393
 394         val = read_dc(par, DC_GENLK_CTL);
 395         val &= ~(DC_GENLK_CTL_ALPHA_FLICK_EN | DC_GENLK_CTL_FLICK_EN |
 396                         DC_GENLK_CTL_FLICK_SEL_MASK);
 397
 398         /* Default scaling params */
 399
 400         write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000);
 401         write_dc(par, DC_IRQ_FILT_CTL, 0);
 402         write_dc(par, DC_GENLK_CTL, val);
 403
 404         /* FIXME:  Support compression */
 405
 406         if (info->fix.line_length > 4096)
 407                 dv = DC_DV_CTL_DV_LINE_SIZE_8K;
 408         else if (info->fix.line_length > 2048)
 409                 dv = DC_DV_CTL_DV_LINE_SIZE_4K;
 410         else if (info->fix.line_length > 1024)
 411                 dv = DC_DV_CTL_DV_LINE_SIZE_2K;
 412         else
 413                 dv = DC_DV_CTL_DV_LINE_SIZE_1K;
 414
 415         max = info->fix.line_length * info->var.yres;
 416         max = (max + 0x3FF) & 0xFFFFFC00;
 417
 418         write_dc(par, DC_DV_TOP, max | DC_DV_TOP_DV_TOP_EN);
 419
 420         val = read_dc(par, DC_DV_CTL) & ~DC_DV_CTL_DV_LINE_SIZE;
 421         write_dc(par, DC_DV_CTL, val | dv);
 422
 423         size = info->var.xres * (info->var.bits_per_pixel >> 3);
 424
 425         write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
 426         write_dc(par, DC_LINE_SIZE, (size + 7) >> 3);
 427
 428         /* Set default watermark values */
 429
 430         rdmsrl(MSR_LX_SPARE_MSR, msrval);
 431
 432         msrval &= ~(DC_SPARE_DISABLE_CFIFO_HGO | DC_SPARE_VFIFO_ARB_SELECT |
 433                     DC_SPARE_LOAD_WM_LPEN_MASK | DC_SPARE_WM_LPEN_OVRD |
 434                     DC_SPARE_DISABLE_INIT_VID_PRI | DC_SPARE_DISABLE_VFIFO_WM);
 435         msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI;
 436         wrmsrl(MSR_LX_SPARE_MSR, msrval);
 437
 438         gcfg = DC_GENERAL_CFG_DFLE;   /* Display fifo enable */
 439         gcfg |= (0x6 << DC_GENERAL_CFG_DFHPSL_SHIFT) | /* default priority */
 440                         (0xb << DC_GENERAL_CFG_DFHPEL_SHIFT);
 441         gcfg |= DC_GENERAL_CFG_FDTY;  /* Set the frame dirty mode */
 442
 443         dcfg  = DC_DISPLAY_CFG_VDEN;  /* Enable video data */
 444         dcfg |= DC_DISPLAY_CFG_GDEN;  /* Enable graphics */
 445         dcfg |= DC_DISPLAY_CFG_TGEN;  /* Turn on the timing generator */
 446         dcfg |= DC_DISPLAY_CFG_TRUP;  /* Update timings immediately */
 447         dcfg |= DC_DISPLAY_CFG_PALB;  /* Palette bypass in > 8 bpp modes */
 448         dcfg |= DC_DISPLAY_CFG_VISL;
 449         dcfg |= DC_DISPLAY_CFG_DCEN;  /* Always center the display */
 450
 451         /* Set the current BPP mode */
 452
 453         switch (info->var.bits_per_pixel) {
 454         case 8:
 455                 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
 456                 break;
 457
 458         case 16:
 459                 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
 460                 break;
 461
 462         case 32:
 463         case 24:
 464                 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
 465                 break;
 466         }
 467
 468         /* Now - set up the timings */
 469
 470         hactive = info->var.xres;
 471         hblankstart = hactive;
 472         hsyncstart = hblankstart + info->var.right_margin;
 473         hsyncend =  hsyncstart + info->var.hsync_len;
 474         hblankend = hsyncend + info->var.left_margin;
 475         htotal = hblankend;
 476
 477         vactive = info->var.yres;
 478         vblankstart = vactive;
 479         vsyncstart = vblankstart + info->var.lower_margin;
 480         vsyncend =  vsyncstart + info->var.vsync_len;
 481         vblankend = vsyncend + info->var.upper_margin;
 482         vtotal = vblankend;
 483
 484         write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) | ((htotal - 1) << 16));
 485         write_dc(par, DC_H_BLANK_TIMING,
 486                         (hblankstart - 1) | ((hblankend - 1) << 16));
 487         write_dc(par, DC_H_SYNC_TIMING,
 488                         (hsyncstart - 1) | ((hsyncend - 1) << 16));
 489
 490         write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) | ((vtotal - 1) << 16));
 491         write_dc(par, DC_V_BLANK_TIMING,
 492                         (vblankstart - 1) | ((vblankend - 1) << 16));
 493         write_dc(par, DC_V_SYNC_TIMING,
 494                         (vsyncstart - 1) | ((vsyncend - 1) << 16));
 495
 496         write_dc(par, DC_FB_ACTIVE,
 497                         (info->var.xres - 1) << 16 | (info->var.yres - 1));
 498
 499         /* And re-enable the graphics output */
 500         lx_graphics_enable(info);
 501
 502         /* Write the two main configuration registers */
 503         write_dc(par, DC_DISPLAY_CFG, dcfg);
 504         write_dc(par, DC_ARB_CFG, 0);
 505         write_dc(par, DC_GENERAL_CFG, gcfg);
 506
 507         /* Lock the DC registers */
 508         write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
 509 }
 510
 511 void lx_set_palette_reg(struct fb_info *info, unsigned regno,
 512                         unsigned red, unsigned green, unsigned blue)
 513 {
 514         struct lxfb_par *par = info->par;
 515         int val;
 516
 517         /* Hardware palette is in RGB 8-8-8 format. */
 518
 519         val  = (red   << 8) & 0xff0000;
 520         val |= (green)      & 0x00ff00;
 521         val |= (blue  >> 8) & 0x0000ff;
 522
 523         write_dc(par, DC_PAL_ADDRESS, regno);
 524         write_dc(par, DC_PAL_DATA, val);
 525 }
 526
 527 int lx_blank_display(struct fb_info *info, int blank_mode)
 528 {
 529         struct lxfb_par *par = info->par;
 530         u32 dcfg, fp_pm;
 531         int blank, hsync, vsync;
 532
 533         /* CRT power saving modes. */
 534         switch (blank_mode) {
 535         case FB_BLANK_UNBLANK:
 536                 blank = 0; hsync = 1; vsync = 1;
 537                 break;
 538         case FB_BLANK_NORMAL:
 539                 blank = 1; hsync = 1; vsync = 1;
 540                 break;
 541         case FB_BLANK_VSYNC_SUSPEND:
 542                 blank = 1; hsync = 1; vsync = 0;
 543                 break;
 544         case FB_BLANK_HSYNC_SUSPEND:
 545                 blank = 1; hsync = 0; vsync = 1;
 546                 break;
 547         case FB_BLANK_POWERDOWN:
 548                 blank = 1; hsync = 0; vsync = 0;
 549                 break;
 550         default:
 551                 return -EINVAL;
 552         }
 553
 554         dcfg = read_vp(par, VP_DCFG);
 555         dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN);
 556         if (!blank)
 557                 dcfg |= VP_DCFG_DAC_BL_EN;
 558         if (hsync)
 559                 dcfg |= VP_DCFG_HSYNC_EN;
 560         if (vsync)
 561                 dcfg |= VP_DCFG_VSYNC_EN;
 562         write_vp(par, VP_DCFG, dcfg);
 563
 564         /* Power on/off flat panel */
 565
 566         if (par->output & OUTPUT_PANEL) {
 567                 fp_pm = read_fp(par, FP_PM);
 568                 if (blank_mode == FB_BLANK_POWERDOWN)
 569                         fp_pm &= ~FP_PM_P;
 570                 else
 571                         fp_pm |= FP_PM_P;
 572                 write_fp(par, FP_PM, fp_pm);
 573         }
 574
 575         return 0;
 576 }