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radeonfb: Disable new color expand acceleration unless explicitely enabled
[linux-2.6/zen-sources.git] / drivers / video / aty / radeon_base.c
blobd5b27f9d374d0f23f72dd18c67be2e2e8d22c579
1 /*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53 #define RADEON_VERSION "0.2.0"
54
55 #include "radeonfb.h"
56
57 #include <linux/module.h>
58 #include <linux/moduleparam.h>
59 #include <linux/kernel.h>
60 #include <linux/errno.h>
61 #include <linux/string.h>
62 #include <linux/ctype.h>
63 #include <linux/mm.h>
64 #include <linux/slab.h>
65 #include <linux/delay.h>
66 #include <linux/time.h>
67 #include <linux/fb.h>
68 #include <linux/ioport.h>
69 #include <linux/init.h>
70 #include <linux/pci.h>
71 #include <linux/vmalloc.h>
72 #include <linux/device.h>
73
74 #include <asm/io.h>
75 #include <linux/uaccess.h>
76
77 #ifdef CONFIG_PPC_OF
78
79 #include <asm/pci-bridge.h>
80 #include "../macmodes.h"
81
82 #ifdef CONFIG_BOOTX_TEXT
83 #include <asm/btext.h>
84 #endif
85
86 #endif /* CONFIG_PPC_OF */
87
88 #ifdef CONFIG_MTRR
89 #include <asm/mtrr.h>
90 #endif
91
92 #include <video/radeon.h>
93 #include <linux/radeonfb.h>
94
95 #include "../edid.h" // MOVE THAT TO include/video
96 #include "ati_ids.h"
97
98 #define MAX_MAPPED_VRAM (2048*2048*4)
99 #define MIN_MAPPED_VRAM (1024*768*1)
100
101 #define CHIP_DEF(id, family, flags) \
102 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
103
104 static struct pci_device_id radeonfb_pci_table[] = {
105 /* Radeon Xpress 200m */
106 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
107 CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
108 /* Mobility M6 */
109 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
110 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
111 /* Radeon VE/7000 */
112 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
113 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
114 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
115 /* Radeon IGP320M (U1) */
116 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
117 /* Radeon IGP320 (A3) */
118 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
119 /* IGP330M/340M/350M (U2) */
120 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
121 /* IGP330/340/350 (A4) */
122 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
123 /* Mobility 7000 IGP */
124 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
125 /* 7000 IGP (A4+) */
126 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
127 /* 8500 AIW */
128 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
129 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
130 /* 8700/8800 */
131 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
132 /* 8500 */
133 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
134 /* 9100 */
135 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
136 /* Mobility M7 */
137 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
138 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139 /* 7500 */
140 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
141 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
142 /* Mobility M9 */
143 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
144 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
146 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
147 /* 9000/Pro */
148 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
149 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
150
151 CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
152 /* Mobility 9100 IGP (U3) */
153 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
154 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
155 /* 9100 IGP (A5) */
156 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
157 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
158 /* Mobility 9200 (M9+) */
159 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
160 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
161 /* 9200 */
162 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
165 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
166 /* 9500 */
167 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
168 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
169 /* 9600TX / FireGL Z1 */
170 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
171 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
172 /* 9700/9500/Pro/FireGL X1 */
173 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
174 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
175 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
176 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
177 /* Mobility M10/M11 */
178 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
182 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
183 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
184 /* 9600/FireGL T2 */
185 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
191 /* 9800/Pro/FileGL X2 */
192 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
199 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
200 /* Newer stuff */
201 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
203 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
205 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
211 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
212 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
219 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
224 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
225 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
226 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
227 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
228 /* Original Radeon/7200 */
229 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
230 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
231 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
232 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
233 { 0, }
234 };
235 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
236
237
238 typedef struct {
239 u16 reg;
240 u32 val;
241 } reg_val;
242
243
244 /* these common regs are cleared before mode setting so they do not
245 * interfere with anything
246 */
247 static reg_val common_regs[] = {
248 { OVR_CLR, 0 },
249 { OVR_WID_LEFT_RIGHT, 0 },
250 { OVR_WID_TOP_BOTTOM, 0 },
251 { OV0_SCALE_CNTL, 0 },
252 { SUBPIC_CNTL, 0 },
253 { VIPH_CONTROL, 0 },
254 { I2C_CNTL_1, 0 },
255 { GEN_INT_CNTL, 0 },
256 { CAP0_TRIG_CNTL, 0 },
257 { CAP1_TRIG_CNTL, 0 },
258 };
259
260 /*
261 * globals
262 */
263
264 static char *mode_option;
265 static char *monitor_layout;
266 static int noaccel = 0;
267 static int default_dynclk = -2;
268 static int nomodeset = 0;
269 static int ignore_edid = 0;
270 static int mirror = 0;
271 static int panel_yres = 0;
272 static int force_dfp = 0;
273 static int force_measure_pll = 0;
274 #ifdef CONFIG_MTRR
275 static int nomtrr = 0;
276 #endif
277 static int force_sleep;
278 static int ignore_devlist;
279 #ifdef CONFIG_PMAC_BACKLIGHT
280 static int backlight = 1;
281 #else
282 static int backlight = 0;
283 #endif
284
285 int accel_cexp = 0;
286
287 /*
288 * prototypes
289 */
290
291 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
292 {
293 if (!rinfo->bios_seg)
294 return;
295 pci_unmap_rom(dev, rinfo->bios_seg);
296 }
297
298 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
299 {
300 void __iomem *rom;
301 u16 dptr;
302 u8 rom_type;
303 size_t rom_size;
304
305 /* If this is a primary card, there is a shadow copy of the
306 * ROM somewhere in the first meg. We will just ignore the copy
307 * and use the ROM directly.
308 */
309
310 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
311 unsigned int temp;
312 temp = INREG(MPP_TB_CONFIG);
313 temp &= 0x00ffffffu;
314 temp |= 0x04 << 24;
315 OUTREG(MPP_TB_CONFIG, temp);
316 temp = INREG(MPP_TB_CONFIG);
317
318 rom = pci_map_rom(dev, &rom_size);
319 if (!rom) {
320 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
321 pci_name(rinfo->pdev));
322 return -ENOMEM;
323 }
324
325 rinfo->bios_seg = rom;
326
327 /* Very simple test to make sure it appeared */
328 if (BIOS_IN16(0) != 0xaa55) {
329 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
330 "should be 0xaa55\n",
331 pci_name(rinfo->pdev), BIOS_IN16(0));
332 goto failed;
333 }
334 /* Look for the PCI data to check the ROM type */
335 dptr = BIOS_IN16(0x18);
336
337 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
338 * for now, until I've verified this works everywhere. The goal here is more
339 * to phase out Open Firmware images.
340 *
341 * Currently, we only look at the first PCI data, we could iteratre and deal with
342 * them all, and we should use fb_bios_start relative to start of image and not
343 * relative start of ROM, but so far, I never found a dual-image ATI card
344 *
345 * typedef struct {
346 * u32 signature; + 0x00
347 * u16 vendor; + 0x04
348 * u16 device; + 0x06
349 * u16 reserved_1; + 0x08
350 * u16 dlen; + 0x0a
351 * u8 drevision; + 0x0c
352 * u8 class_hi; + 0x0d
353 * u16 class_lo; + 0x0e
354 * u16 ilen; + 0x10
355 * u16 irevision; + 0x12
356 * u8 type; + 0x14
357 * u8 indicator; + 0x15
358 * u16 reserved_2; + 0x16
359 * } pci_data_t;
360 */
361 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
362 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
363 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
364 goto anyway;
365 }
366 rom_type = BIOS_IN8(dptr + 0x14);
367 switch(rom_type) {
368 case 0:
369 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
370 break;
371 case 1:
372 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
373 goto failed;
374 case 2:
375 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
376 goto failed;
377 default:
378 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
379 goto failed;
380 }
381 anyway:
382 /* Locate the flat panel infos, do some sanity checking !!! */
383 rinfo->fp_bios_start = BIOS_IN16(0x48);
384 return 0;
385
386 failed:
387 rinfo->bios_seg = NULL;
388 radeon_unmap_ROM(rinfo, dev);
389 return -ENXIO;
390 }
391
392 #ifdef CONFIG_X86
393 static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
394 {
395 /* I simplified this code as we used to miss the signatures in
396 * a lot of case. It's now closer to XFree, we just don't check
397 * for signatures at all... Something better will have to be done
398 * if we end up having conflicts
399 */
400 u32 segstart;
401 void __iomem *rom_base = NULL;
402
403 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
404 rom_base = ioremap(segstart, 0x10000);
405 if (rom_base == NULL)
406 return -ENOMEM;
407 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
408 break;
409 iounmap(rom_base);
410 rom_base = NULL;
411 }
412 if (rom_base == NULL)
413 return -ENXIO;
414
415 /* Locate the flat panel infos, do some sanity checking !!! */
416 rinfo->bios_seg = rom_base;
417 rinfo->fp_bios_start = BIOS_IN16(0x48);
418
419 return 0;
420 }
421 #endif
422
423 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
424 /*
425 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
426 * tree. Hopefully, ATI OF driver is kind enough to fill these
427 */
428 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
429 {
430 struct device_node *dp = rinfo->of_node;
431 const u32 *val;
432
433 if (dp == NULL)
434 return -ENODEV;
435 val = of_get_property(dp, "ATY,RefCLK", NULL);
436 if (!val || !*val) {
437 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
438 return -EINVAL;
439 }
440
441 rinfo->pll.ref_clk = (*val) / 10;
442
443 val = of_get_property(dp, "ATY,SCLK", NULL);
444 if (val && *val)
445 rinfo->pll.sclk = (*val) / 10;
446
447 val = of_get_property(dp, "ATY,MCLK", NULL);
448 if (val && *val)
449 rinfo->pll.mclk = (*val) / 10;
450
451 return 0;
452 }
453 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
454
455 /*
456 * Read PLL infos from chip registers
457 */
458 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
459 {
460 unsigned char ppll_div_sel;
461 unsigned Ns, Nm, M;
462 unsigned sclk, mclk, tmp, ref_div;
463 int hTotal, vTotal, num, denom, m, n;
464 unsigned long long hz, vclk;
465 long xtal;
466 struct timeval start_tv, stop_tv;
467 long total_secs, total_usecs;
468 int i;
469
470 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
471 * here, so... --BenH
472 */
473
474 /* Flush PCI buffers ? */
475 tmp = INREG16(DEVICE_ID);
476
477 local_irq_disable();
478
479 for(i=0; i<1000000; i++)
480 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
481 break;
482
483 do_gettimeofday(&start_tv);
484
485 for(i=0; i<1000000; i++)
486 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
487 break;
488
489 for(i=0; i<1000000; i++)
490 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
491 break;
492
493 do_gettimeofday(&stop_tv);
494
495 local_irq_enable();
496
497 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
498 if (total_secs > 10)
499 return -1;
500 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
501 total_usecs += total_secs * 1000000;
502 if (total_usecs < 0)
503 total_usecs = -total_usecs;
504 hz = 1000000/total_usecs;
505
506 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
507 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
508 vclk = (long long)hTotal * (long long)vTotal * hz;
509
510 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
511 case 0:
512 default:
513 num = 1;
514 denom = 1;
515 break;
516 case 1:
517 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
518 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
519 num = 2*n;
520 denom = 2*m;
521 break;
522 case 2:
523 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
524 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
525 num = 2*n;
526 denom = 2*m;
527 break;
528 }
529
530 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
531 radeon_pll_errata_after_index(rinfo);
532
533 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
534 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
535
536 num *= n;
537 denom *= m;
538
539 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
540 case 1:
541 denom *= 2;
542 break;
543 case 2:
544 denom *= 4;
545 break;
546 case 3:
547 denom *= 8;
548 break;
549 case 4:
550 denom *= 3;
551 break;
552 case 6:
553 denom *= 6;
554 break;
555 case 7:
556 denom *= 12;
557 break;
558 }
559
560 vclk *= denom;
561 do_div(vclk, 1000 * num);
562 xtal = vclk;
563
564 if ((xtal > 26900) && (xtal < 27100))
565 xtal = 2700;
566 else if ((xtal > 14200) && (xtal < 14400))
567 xtal = 1432;
568 else if ((xtal > 29400) && (xtal < 29600))
569 xtal = 2950;
570 else {
571 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
572 return -1;
573 }
574
575 tmp = INPLL(M_SPLL_REF_FB_DIV);
576 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
577
578 Ns = (tmp & 0xff0000) >> 16;
579 Nm = (tmp & 0xff00) >> 8;
580 M = (tmp & 0xff);
581 sclk = round_div((2 * Ns * xtal), (2 * M));
582 mclk = round_div((2 * Nm * xtal), (2 * M));
583
584 /* we're done, hopefully these are sane values */
585 rinfo->pll.ref_clk = xtal;
586 rinfo->pll.ref_div = ref_div;
587 rinfo->pll.sclk = sclk;
588 rinfo->pll.mclk = mclk;
589
590 return 0;
591 }
592
593 /*
594 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
595 */
596 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
597 {
598 /*
599 * In the case nothing works, these are defaults; they are mostly
600 * incomplete, however. It does provide ppll_max and _min values
601 * even for most other methods, however.
602 */
603 switch (rinfo->chipset) {
604 case PCI_DEVICE_ID_ATI_RADEON_QW:
605 case PCI_DEVICE_ID_ATI_RADEON_QX:
606 rinfo->pll.ppll_max = 35000;
607 rinfo->pll.ppll_min = 12000;
608 rinfo->pll.mclk = 23000;
609 rinfo->pll.sclk = 23000;
610 rinfo->pll.ref_clk = 2700;
611 break;
612 case PCI_DEVICE_ID_ATI_RADEON_QL:
613 case PCI_DEVICE_ID_ATI_RADEON_QN:
614 case PCI_DEVICE_ID_ATI_RADEON_QO:
615 case PCI_DEVICE_ID_ATI_RADEON_Ql:
616 case PCI_DEVICE_ID_ATI_RADEON_BB:
617 rinfo->pll.ppll_max = 35000;
618 rinfo->pll.ppll_min = 12000;
619 rinfo->pll.mclk = 27500;
620 rinfo->pll.sclk = 27500;
621 rinfo->pll.ref_clk = 2700;
622 break;
623 case PCI_DEVICE_ID_ATI_RADEON_Id:
624 case PCI_DEVICE_ID_ATI_RADEON_Ie:
625 case PCI_DEVICE_ID_ATI_RADEON_If:
626 case PCI_DEVICE_ID_ATI_RADEON_Ig:
627 rinfo->pll.ppll_max = 35000;
628 rinfo->pll.ppll_min = 12000;
629 rinfo->pll.mclk = 25000;
630 rinfo->pll.sclk = 25000;
631 rinfo->pll.ref_clk = 2700;
632 break;
633 case PCI_DEVICE_ID_ATI_RADEON_ND:
634 case PCI_DEVICE_ID_ATI_RADEON_NE:
635 case PCI_DEVICE_ID_ATI_RADEON_NF:
636 case PCI_DEVICE_ID_ATI_RADEON_NG:
637 rinfo->pll.ppll_max = 40000;
638 rinfo->pll.ppll_min = 20000;
639 rinfo->pll.mclk = 27000;
640 rinfo->pll.sclk = 27000;
641 rinfo->pll.ref_clk = 2700;
642 break;
643 case PCI_DEVICE_ID_ATI_RADEON_QD:
644 case PCI_DEVICE_ID_ATI_RADEON_QE:
645 case PCI_DEVICE_ID_ATI_RADEON_QF:
646 case PCI_DEVICE_ID_ATI_RADEON_QG:
647 default:
648 rinfo->pll.ppll_max = 35000;
649 rinfo->pll.ppll_min = 12000;
650 rinfo->pll.mclk = 16600;
651 rinfo->pll.sclk = 16600;
652 rinfo->pll.ref_clk = 2700;
653 break;
654 }
655 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
656
657
658 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
659 /*
660 * Retrieve PLL infos from Open Firmware first
661 */
662 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
663 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
664 goto found;
665 }
666 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
667
668 /*
669 * Check out if we have an X86 which gave us some PLL informations
670 * and if yes, retrieve them
671 */
672 if (!force_measure_pll && rinfo->bios_seg) {
673 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
674
675 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
676 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
677 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
678 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
679 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
680 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
681
682 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
683 goto found;
684 }
685
686 /*
687 * We didn't get PLL parameters from either OF or BIOS, we try to
688 * probe them
689 */
690 if (radeon_probe_pll_params(rinfo) == 0) {
691 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
692 goto found;
693 }
694
695 /*
696 * Fall back to already-set defaults...
697 */
698 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
699
700 found:
701 /*
702 * Some methods fail to retrieve SCLK and MCLK values, we apply default
703 * settings in this case (200Mhz). If that really happne often, we could
704 * fetch from registers instead...
705 */
706 if (rinfo->pll.mclk == 0)
707 rinfo->pll.mclk = 20000;
708 if (rinfo->pll.sclk == 0)
709 rinfo->pll.sclk = 20000;
710
711 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
712 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
713 rinfo->pll.ref_div,
714 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
715 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
716 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
717 }
718
719 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
720 {
721 struct radeonfb_info *rinfo = info->par;
722 struct fb_var_screeninfo v;
723 int nom, den;
724 unsigned int pitch;
725
726 if (radeon_match_mode(rinfo, &v, var))
727 return -EINVAL;
728
729 switch (v.bits_per_pixel) {
730 case 0 ... 8:
731 v.bits_per_pixel = 8;
732 break;
733 case 9 ... 16:
734 v.bits_per_pixel = 16;
735 break;
736 case 17 ... 24:
737 #if 0 /* Doesn't seem to work */
738 v.bits_per_pixel = 24;
739 break;
740 #endif
741 return -EINVAL;
742 case 25 ... 32:
743 v.bits_per_pixel = 32;
744 break;
745 default:
746 return -EINVAL;
747 }
748
749 switch (var_to_depth(&v)) {
750 case 8:
751 nom = den = 1;
752 v.red.offset = v.green.offset = v.blue.offset = 0;
753 v.red.length = v.green.length = v.blue.length = 8;
754 v.transp.offset = v.transp.length = 0;
755 break;
756 case 15:
757 nom = 2;
758 den = 1;
759 v.red.offset = 10;
760 v.green.offset = 5;
761 v.blue.offset = 0;
762 v.red.length = v.green.length = v.blue.length = 5;
763 v.transp.offset = v.transp.length = 0;
764 break;
765 case 16:
766 nom = 2;
767 den = 1;
768 v.red.offset = 11;
769 v.green.offset = 5;
770 v.blue.offset = 0;
771 v.red.length = 5;
772 v.green.length = 6;
773 v.blue.length = 5;
774 v.transp.offset = v.transp.length = 0;
775 break;
776 case 24:
777 nom = 4;
778 den = 1;
779 v.red.offset = 16;
780 v.green.offset = 8;
781 v.blue.offset = 0;
782 v.red.length = v.blue.length = v.green.length = 8;
783 v.transp.offset = v.transp.length = 0;
784 break;
785 case 32:
786 nom = 4;
787 den = 1;
788 v.red.offset = 16;
789 v.green.offset = 8;
790 v.blue.offset = 0;
791 v.red.length = v.blue.length = v.green.length = 8;
792 v.transp.offset = 24;
793 v.transp.length = 8;
794 break;
795 default:
796 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
797 var->xres, var->yres, var->bits_per_pixel);
798 return -EINVAL;
799 }
800
801 if (v.yres_virtual < v.yres)
802 v.yres_virtual = v.yres;
803 if (v.xres_virtual < v.xres)
804 v.xres_virtual = v.xres;
805
806
807 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
808 * with some panels, though I don't quite like this solution
809 */
810 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
811 v.xres_virtual = v.xres_virtual & ~7ul;
812 } else {
813 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
814 & ~(0x3f)) >> 6;
815 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
816 }
817
818 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
819 return -EINVAL;
820
821 if (v.xres_virtual < v.xres)
822 v.xres = v.xres_virtual;
823
824 if (v.xoffset < 0)
825 v.xoffset = 0;
826 if (v.yoffset < 0)
827 v.yoffset = 0;
828
829 if (v.xoffset > v.xres_virtual - v.xres)
830 v.xoffset = v.xres_virtual - v.xres - 1;
831
832 if (v.yoffset > v.yres_virtual - v.yres)
833 v.yoffset = v.yres_virtual - v.yres - 1;
834
835 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
836 v.transp.offset = v.transp.length =
837 v.transp.msb_right = 0;
838
839 memcpy(var, &v, sizeof(v));
840
841 return 0;
842 }
843
844
845 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
846 struct fb_info *info)
847 {
848 struct radeonfb_info *rinfo = info->par;
849
850 if ((var->xoffset + var->xres > var->xres_virtual)
851 || (var->yoffset + var->yres > var->yres_virtual))
852 return -EINVAL;
853
854 if (rinfo->asleep)
855 return 0;
856
857 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
858 * var->bits_per_pixel / 8) & ~7);
859 return 0;
860 }
861
862
863 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
864 unsigned long arg)
865 {
866 struct radeonfb_info *rinfo = info->par;
867 unsigned int tmp;
868 u32 value = 0;
869 int rc;
870
871 switch (cmd) {
872 /*
873 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
874 * and do something better using 2nd CRTC instead of just hackish
875 * routing to second output
876 */
877 case FBIO_RADEON_SET_MIRROR:
878 if (!rinfo->is_mobility)
879 return -EINVAL;
880
881 rc = get_user(value, (__u32 __user *)arg);
882
883 if (rc)
884 return rc;
885
886 if (value & 0x01) {
887 tmp = INREG(LVDS_GEN_CNTL);
888
889 tmp |= (LVDS_ON | LVDS_BLON);
890 } else {
891 tmp = INREG(LVDS_GEN_CNTL);
892
893 tmp &= ~(LVDS_ON | LVDS_BLON);
894 }
895
896 OUTREG(LVDS_GEN_CNTL, tmp);
897
898 if (value & 0x02) {
899 tmp = INREG(CRTC_EXT_CNTL);
900 tmp |= CRTC_CRT_ON;
901
902 mirror = 1;
903 } else {
904 tmp = INREG(CRTC_EXT_CNTL);
905 tmp &= ~CRTC_CRT_ON;
906
907 mirror = 0;
908 }
909
910 OUTREG(CRTC_EXT_CNTL, tmp);
911
912 return 0;
913 case FBIO_RADEON_GET_MIRROR:
914 if (!rinfo->is_mobility)
915 return -EINVAL;
916
917 tmp = INREG(LVDS_GEN_CNTL);
918 if ((LVDS_ON | LVDS_BLON) & tmp)
919 value |= 0x01;
920
921 tmp = INREG(CRTC_EXT_CNTL);
922 if (CRTC_CRT_ON & tmp)
923 value |= 0x02;
924
925 return put_user(value, (__u32 __user *)arg);
926 default:
927 return -EINVAL;
928 }
929
930 return -EINVAL;
931 }
932
933
934 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
935 {
936 u32 val;
937 u32 tmp_pix_clks;
938 int unblank = 0;
939
940 if (rinfo->lock_blank)
941 return 0;
942
943 radeon_engine_idle(rinfo);
944
945 val = INREG(CRTC_EXT_CNTL);
946 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
947 CRTC_VSYNC_DIS);
948 switch (blank) {
949 case FB_BLANK_VSYNC_SUSPEND:
950 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
951 break;
952 case FB_BLANK_HSYNC_SUSPEND:
953 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
954 break;
955 case FB_BLANK_POWERDOWN:
956 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
957 CRTC_HSYNC_DIS);
958 break;
959 case FB_BLANK_NORMAL:
960 val |= CRTC_DISPLAY_DIS;
961 break;
962 case FB_BLANK_UNBLANK:
963 default:
964 unblank = 1;
965 }
966 OUTREG(CRTC_EXT_CNTL, val);
967
968
969 switch (rinfo->mon1_type) {
970 case MT_DFP:
971 if (unblank)
972 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
973 ~(FP_FPON | FP_TMDS_EN));
974 else {
975 if (mode_switch || blank == FB_BLANK_NORMAL)
976 break;
977 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
978 }
979 break;
980 case MT_LCD:
981 del_timer_sync(&rinfo->lvds_timer);
982 val = INREG(LVDS_GEN_CNTL);
983 if (unblank) {
984 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
985 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
986 & (LVDS_DIGON | LVDS_BL_MOD_EN));
987 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
988 OUTREG(LVDS_GEN_CNTL, target_val);
989 else if ((val ^ target_val) != 0) {
990 OUTREG(LVDS_GEN_CNTL, target_val
991 & ~(LVDS_ON | LVDS_BL_MOD_EN));
992 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
993 rinfo->init_state.lvds_gen_cntl |=
994 target_val & LVDS_STATE_MASK;
995 if (mode_switch) {
996 radeon_msleep(rinfo->panel_info.pwr_delay);
997 OUTREG(LVDS_GEN_CNTL, target_val);
998 }
999 else {
1000 rinfo->pending_lvds_gen_cntl = target_val;
1001 mod_timer(&rinfo->lvds_timer,
1002 jiffies +
1003 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1004 }
1005 }
1006 } else {
1007 val |= LVDS_DISPLAY_DIS;
1008 OUTREG(LVDS_GEN_CNTL, val);
1009
1010 /* We don't do a full switch-off on a simple mode switch */
1011 if (mode_switch || blank == FB_BLANK_NORMAL)
1012 break;
1013
1014 /* Asic bug, when turning off LVDS_ON, we have to make sure
1015 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1016 */
1017 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1018 if (rinfo->is_mobility || rinfo->is_IGP)
1019 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1020 val &= ~(LVDS_BL_MOD_EN);
1021 OUTREG(LVDS_GEN_CNTL, val);
1022 udelay(100);
1023 val &= ~(LVDS_ON | LVDS_EN);
1024 OUTREG(LVDS_GEN_CNTL, val);
1025 val &= ~LVDS_DIGON;
1026 rinfo->pending_lvds_gen_cntl = val;
1027 mod_timer(&rinfo->lvds_timer,
1028 jiffies +
1029 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1030 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1031 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1032 if (rinfo->is_mobility || rinfo->is_IGP)
1033 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1034 }
1035 break;
1036 case MT_CRT:
1037 // todo: powerdown DAC
1038 default:
1039 break;
1040 }
1041
1042 return 0;
1043 }
1044
1045 static int radeonfb_blank (int blank, struct fb_info *info)
1046 {
1047 struct radeonfb_info *rinfo = info->par;
1048
1049 if (rinfo->asleep)
1050 return 0;
1051
1052 return radeon_screen_blank(rinfo, blank, 0);
1053 }
1054
1055 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1056 unsigned blue, unsigned transp,
1057 struct radeonfb_info *rinfo)
1058 {
1059 u32 pindex;
1060 unsigned int i;
1061
1062
1063 if (regno > 255)
1064 return -EINVAL;
1065
1066 red >>= 8;
1067 green >>= 8;
1068 blue >>= 8;
1069 rinfo->palette[regno].red = red;
1070 rinfo->palette[regno].green = green;
1071 rinfo->palette[regno].blue = blue;
1072
1073 /* default */
1074 pindex = regno;
1075
1076 if (!rinfo->asleep) {
1077 if (rinfo->bpp == 16) {
1078 pindex = regno * 8;
1079
1080 if (rinfo->depth == 16 && regno > 63)
1081 return -EINVAL;
1082 if (rinfo->depth == 15 && regno > 31)
1083 return -EINVAL;
1084
1085 /* For 565, the green component is mixed one order
1086 * below
1087 */
1088 if (rinfo->depth == 16) {
1089 OUTREG(PALETTE_INDEX, pindex>>1);
1090 OUTREG(PALETTE_DATA,
1091 (rinfo->palette[regno>>1].red << 16) |
1092 (green << 8) |
1093 (rinfo->palette[regno>>1].blue));
1094 green = rinfo->palette[regno<<1].green;
1095 }
1096 }
1097
1098 if (rinfo->depth != 16 || regno < 32) {
1099 OUTREG(PALETTE_INDEX, pindex);
1100 OUTREG(PALETTE_DATA, (red << 16) |
1101 (green << 8) | blue);
1102 }
1103 }
1104 if (regno < 16) {
1105 u32 *pal = rinfo->info->pseudo_palette;
1106 switch (rinfo->depth) {
1107 case 15:
1108 pal[regno] = (regno << 10) | (regno << 5) | regno;
1109 break;
1110 case 16:
1111 pal[regno] = (regno << 11) | (regno << 5) | regno;
1112 break;
1113 case 24:
1114 pal[regno] = (regno << 16) | (regno << 8) | regno;
1115 break;
1116 case 32:
1117 i = (regno << 8) | regno;
1118 pal[regno] = (i << 16) | i;
1119 break;
1120 }
1121 }
1122 return 0;
1123 }
1124
1125 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1126 unsigned blue, unsigned transp,
1127 struct fb_info *info)
1128 {
1129 struct radeonfb_info *rinfo = info->par;
1130 u32 dac_cntl2, vclk_cntl = 0;
1131 int rc;
1132
1133 if (!rinfo->asleep) {
1134 if (rinfo->is_mobility) {
1135 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1136 OUTPLL(VCLK_ECP_CNTL,
1137 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1138 }
1139
1140 /* Make sure we are on first palette */
1141 if (rinfo->has_CRTC2) {
1142 dac_cntl2 = INREG(DAC_CNTL2);
1143 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1144 OUTREG(DAC_CNTL2, dac_cntl2);
1145 }
1146 }
1147
1148 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1149
1150 if (!rinfo->asleep && rinfo->is_mobility)
1151 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1152
1153 return rc;
1154 }
1155
1156 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1157 {
1158 struct radeonfb_info *rinfo = info->par;
1159 u16 *red, *green, *blue, *transp;
1160 u32 dac_cntl2, vclk_cntl = 0;
1161 int i, start, rc = 0;
1162
1163 if (!rinfo->asleep) {
1164 if (rinfo->is_mobility) {
1165 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1166 OUTPLL(VCLK_ECP_CNTL,
1167 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1168 }
1169
1170 /* Make sure we are on first palette */
1171 if (rinfo->has_CRTC2) {
1172 dac_cntl2 = INREG(DAC_CNTL2);
1173 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1174 OUTREG(DAC_CNTL2, dac_cntl2);
1175 }
1176 }
1177
1178 red = cmap->red;
1179 green = cmap->green;
1180 blue = cmap->blue;
1181 transp = cmap->transp;
1182 start = cmap->start;
1183
1184 for (i = 0; i < cmap->len; i++) {
1185 u_int hred, hgreen, hblue, htransp = 0xffff;
1186
1187 hred = *red++;
1188 hgreen = *green++;
1189 hblue = *blue++;
1190 if (transp)
1191 htransp = *transp++;
1192 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1193 rinfo);
1194 if (rc)
1195 break;
1196 }
1197
1198 if (!rinfo->asleep && rinfo->is_mobility)
1199 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1200
1201 return rc;
1202 }
1203
1204 static void radeon_save_state (struct radeonfb_info *rinfo,
1205 struct radeon_regs *save)
1206 {
1207 /* CRTC regs */
1208 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1209 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1210 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1211 save->dac_cntl = INREG(DAC_CNTL);
1212 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1213 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1214 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1215 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1216 save->crtc_pitch = INREG(CRTC_PITCH);
1217 save->surface_cntl = INREG(SURFACE_CNTL);
1218
1219 /* FP regs */
1220 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1221 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1222 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1223 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1224 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1225 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1226 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1227 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1228 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1229 save->tmds_crc = INREG(TMDS_CRC);
1230 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1231 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1232
1233 /* PLL regs */
1234 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1235 radeon_pll_errata_after_index(rinfo);
1236 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1237 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1238 }
1239
1240
1241 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1242 {
1243 int i;
1244
1245 /* Workaround from XFree */
1246 if (rinfo->is_mobility) {
1247 /* A temporal workaround for the occational blanking on certain laptop
1248 * panels. This appears to related to the PLL divider registers
1249 * (fail to lock?). It occurs even when all dividers are the same
1250 * with their old settings. In this case we really don't need to
1251 * fiddle with PLL registers. By doing this we can avoid the blanking
1252 * problem with some panels.
1253 */
1254 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1255 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1256 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1257 /* We still have to force a switch to selected PPLL div thanks to
1258 * an XFree86 driver bug which will switch it away in some cases
1259 * even when using UseFDev */
1260 OUTREGP(CLOCK_CNTL_INDEX,
1261 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1262 ~PPLL_DIV_SEL_MASK);
1263 radeon_pll_errata_after_index(rinfo);
1264 radeon_pll_errata_after_data(rinfo);
1265 return;
1266 }
1267 }
1268
1269 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1270 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1271
1272 /* Reset PPLL & enable atomic update */
1273 OUTPLLP(PPLL_CNTL,
1274 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1275 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1276
1277 /* Switch to selected PPLL divider */
1278 OUTREGP(CLOCK_CNTL_INDEX,
1279 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1280 ~PPLL_DIV_SEL_MASK);
1281 radeon_pll_errata_after_index(rinfo);
1282 radeon_pll_errata_after_data(rinfo);
1283
1284 /* Set PPLL ref. div */
1285 if (IS_R300_VARIANT(rinfo) ||
1286 rinfo->family == CHIP_FAMILY_RS300 ||
1287 rinfo->family == CHIP_FAMILY_RS400 ||
1288 rinfo->family == CHIP_FAMILY_RS480) {
1289 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1290 /* When restoring console mode, use saved PPLL_REF_DIV
1291 * setting.
1292 */
1293 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1294 } else {
1295 /* R300 uses ref_div_acc field as real ref divider */
1296 OUTPLLP(PPLL_REF_DIV,
1297 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1298 ~R300_PPLL_REF_DIV_ACC_MASK);
1299 }
1300 } else
1301 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1302
1303 /* Set PPLL divider 3 & post divider*/
1304 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1305 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1306
1307 /* Write update */
1308 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1309 ;
1310 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1311
1312 /* Wait read update complete */
1313 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1314 the cause yet, but this workaround will mask the problem for now.
1315 Other chips usually will pass at the very first test, so the
1316 workaround shouldn't have any effect on them. */
1317 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1318 ;
1319
1320 OUTPLL(HTOTAL_CNTL, 0);
1321
1322 /* Clear reset & atomic update */
1323 OUTPLLP(PPLL_CNTL, 0,
1324 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1325
1326 /* We may want some locking ... oh well */
1327 radeon_msleep(5);
1328
1329 /* Switch back VCLK source to PPLL */
1330 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1331 }
1332
1333 /*
1334 * Timer function for delayed LVDS panel power up/down
1335 */
1336 static void radeon_lvds_timer_func(unsigned long data)
1337 {
1338 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1339
1340 radeon_engine_idle(rinfo);
1341
1342 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1343 }
1344
1345 /*
1346 * Apply a video mode. This will apply the whole register set, including
1347 * the PLL registers, to the card
1348 */
1349 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1350 int regs_only)
1351 {
1352 int i;
1353 int primary_mon = PRIMARY_MONITOR(rinfo);
1354
1355 if (nomodeset)
1356 return;
1357
1358 radeon_engine_idle(rinfo);
1359
1360 if (!regs_only)
1361 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1362
1363 for (i=0; i<10; i++)
1364 OUTREG(common_regs[i].reg, common_regs[i].val);
1365
1366 /* Apply surface registers */
1367 for (i=0; i<8; i++) {
1368 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1369 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1370 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1371 }
1372
1373 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1374 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1375 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1376 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1377 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1378 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1379 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1380 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1381 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1382 OUTREG(CRTC_OFFSET, 0);
1383 OUTREG(CRTC_OFFSET_CNTL, 0);
1384 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1385 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1386
1387 radeon_write_pll_regs(rinfo, mode);
1388
1389 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1390 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1391 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1392 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1393 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1394 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1395 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1396 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1397 OUTREG(TMDS_CRC, mode->tmds_crc);
1398 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1399 }
1400
1401 if (!regs_only)
1402 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1403
1404 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1405
1406 return;
1407 }
1408
1409 /*
1410 * Calculate the PLL values for a given mode
1411 */
1412 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1413 unsigned long freq)
1414 {
1415 const struct {
1416 int divider;
1417 int bitvalue;
1418 } *post_div,
1419 post_divs[] = {
1420 { 1, 0 },
1421 { 2, 1 },
1422 { 4, 2 },
1423 { 8, 3 },
1424 { 3, 4 },
1425 { 16, 5 },
1426 { 6, 6 },
1427 { 12, 7 },
1428 { 0, 0 },
1429 };
1430 int fb_div, pll_output_freq = 0;
1431 int uses_dvo = 0;
1432
1433 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1434 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1435 * recent than an r(v)100...
1436 */
1437 #if 1
1438 /* XXX I had reports of flicker happening with the cinema display
1439 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1440 * this case. This could just be a bandwidth calculation issue, I
1441 * haven't implemented the bandwidth code yet, but in the meantime,
1442 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1443 * I haven't seen a case were were absolutely needed an odd PLL
1444 * divider. I'll find a better fix once I have more infos on the
1445 * real cause of the problem.
1446 */
1447 while (rinfo->has_CRTC2) {
1448 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1449 u32 disp_output_cntl;
1450 int source;
1451
1452 /* FP2 path not enabled */
1453 if ((fp2_gen_cntl & FP2_ON) == 0)
1454 break;
1455 /* Not all chip revs have the same format for this register,
1456 * extract the source selection
1457 */
1458 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) {
1459 source = (fp2_gen_cntl >> 10) & 0x3;
1460 /* sourced from transform unit, check for transform unit
1461 * own source
1462 */
1463 if (source == 3) {
1464 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1465 source = (disp_output_cntl >> 12) & 0x3;
1466 }
1467 } else
1468 source = (fp2_gen_cntl >> 13) & 0x1;
1469 /* sourced from CRTC2 -> exit */
1470 if (source == 1)
1471 break;
1472
1473 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1474 uses_dvo = 1;
1475 break;
1476 }
1477 #else
1478 uses_dvo = 1;
1479 #endif
1480 if (freq > rinfo->pll.ppll_max)
1481 freq = rinfo->pll.ppll_max;
1482 if (freq*12 < rinfo->pll.ppll_min)
1483 freq = rinfo->pll.ppll_min / 12;
1484 pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n",
1485 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1486
1487 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1488 pll_output_freq = post_div->divider * freq;
1489 /* If we output to the DVO port (external TMDS), we don't allow an
1490 * odd PLL divider as those aren't supported on this path
1491 */
1492 if (uses_dvo && (post_div->divider & 1))
1493 continue;
1494 if (pll_output_freq >= rinfo->pll.ppll_min &&
1495 pll_output_freq <= rinfo->pll.ppll_max)
1496 break;
1497 }
1498
1499 /* If we fall through the bottom, try the "default value"
1500 given by the terminal post_div->bitvalue */
1501 if ( !post_div->divider ) {
1502 post_div = &post_divs[post_div->bitvalue];
1503 pll_output_freq = post_div->divider * freq;
1504 }
1505 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1506 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1507 pll_output_freq);
1508
1509 /* If we fall through the bottom, try the "default value"
1510 given by the terminal post_div->bitvalue */
1511 if ( !post_div->divider ) {
1512 post_div = &post_divs[post_div->bitvalue];
1513 pll_output_freq = post_div->divider * freq;
1514 }
1515 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1516 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1517 pll_output_freq);
1518
1519 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1520 rinfo->pll.ref_clk);
1521 regs->ppll_ref_div = rinfo->pll.ref_div;
1522 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1523
1524 pr_debug("post div = 0x%x\n", post_div->bitvalue);
1525 pr_debug("fb_div = 0x%x\n", fb_div);
1526 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1527 }
1528
1529 static int radeonfb_set_par(struct fb_info *info)
1530 {
1531 struct radeonfb_info *rinfo = info->par;
1532 struct fb_var_screeninfo *mode = &info->var;
1533 struct radeon_regs *newmode;
1534 int hTotal, vTotal, hSyncStart, hSyncEnd,
1535 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1536 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1537 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1538 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1539 int i, freq;
1540 int format = 0;
1541 int nopllcalc = 0;
1542 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1543 int primary_mon = PRIMARY_MONITOR(rinfo);
1544 int depth = var_to_depth(mode);
1545 int use_rmx = 0;
1546
1547 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1548 if (!newmode)
1549 return -ENOMEM;
1550
1551 /* We always want engine to be idle on a mode switch, even
1552 * if we won't actually change the mode
1553 */
1554 radeon_engine_idle(rinfo);
1555
1556 hSyncStart = mode->xres + mode->right_margin;
1557 hSyncEnd = hSyncStart + mode->hsync_len;
1558 hTotal = hSyncEnd + mode->left_margin;
1559
1560 vSyncStart = mode->yres + mode->lower_margin;
1561 vSyncEnd = vSyncStart + mode->vsync_len;
1562 vTotal = vSyncEnd + mode->upper_margin;
1563 pixClock = mode->pixclock;
1564
1565 sync = mode->sync;
1566 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1567 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1568
1569 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1570 if (rinfo->panel_info.xres < mode->xres)
1571 mode->xres = rinfo->panel_info.xres;
1572 if (rinfo->panel_info.yres < mode->yres)
1573 mode->yres = rinfo->panel_info.yres;
1574
1575 hTotal = mode->xres + rinfo->panel_info.hblank;
1576 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1577 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1578
1579 vTotal = mode->yres + rinfo->panel_info.vblank;
1580 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1581 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1582
1583 h_sync_pol = !rinfo->panel_info.hAct_high;
1584 v_sync_pol = !rinfo->panel_info.vAct_high;
1585
1586 pixClock = 100000000 / rinfo->panel_info.clock;
1587
1588 if (rinfo->panel_info.use_bios_dividers) {
1589 nopllcalc = 1;
1590 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1591 (rinfo->panel_info.post_divider << 16);
1592 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1593 }
1594 }
1595 dotClock = 1000000000 / pixClock;
1596 freq = dotClock / 10; /* x100 */
1597
1598 pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n",
1599 hSyncStart, hSyncEnd, hTotal);
1600 pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n",
1601 vSyncStart, vSyncEnd, vTotal);
1602
1603 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1604 vsync_wid = vSyncEnd - vSyncStart;
1605 if (hsync_wid == 0)
1606 hsync_wid = 1;
1607 else if (hsync_wid > 0x3f) /* max */
1608 hsync_wid = 0x3f;
1609
1610 if (vsync_wid == 0)
1611 vsync_wid = 1;
1612 else if (vsync_wid > 0x1f) /* max */
1613 vsync_wid = 0x1f;
1614
1615 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1616 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1617
1618 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1619
1620 format = radeon_get_dstbpp(depth);
1621 bytpp = mode->bits_per_pixel >> 3;
1622
1623 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1624 hsync_fudge = hsync_fudge_fp[format-1];
1625 else
1626 hsync_fudge = hsync_adj_tab[format-1];
1627
1628 hsync_start = hSyncStart - 8 + hsync_fudge;
1629
1630 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1631 (format << 8);
1632
1633 /* Clear auto-center etc... */
1634 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1635 newmode->crtc_more_cntl &= 0xfffffff0;
1636
1637 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1638 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1639 if (mirror)
1640 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1641
1642 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1643 CRTC_INTERLACE_EN);
1644 } else {
1645 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1646 CRTC_CRT_ON;
1647 }
1648
1649 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1650 DAC_8BIT_EN;
1651
1652 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1653 (((mode->xres / 8) - 1) << 16));
1654
1655 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1656 (hsync_wid << 16) | (h_sync_pol << 23));
1657
1658 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1659 ((mode->yres - 1) << 16);
1660
1661 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1662 (vsync_wid << 16) | (v_sync_pol << 23));
1663
1664 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1665 /* We first calculate the engine pitch */
1666 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1667 & ~(0x3f)) >> 6;
1668
1669 /* Then, re-multiply it to get the CRTC pitch */
1670 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1671 } else
1672 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1673
1674 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1675
1676 /*
1677 * It looks like recent chips have a problem with SURFACE_CNTL,
1678 * setting SURF_TRANSLATION_DIS completely disables the
1679 * swapper as well, so we leave it unset now.
1680 */
1681 newmode->surface_cntl = 0;
1682
1683 #if defined(__BIG_ENDIAN)
1684
1685 /* Setup swapping on both apertures, though we currently
1686 * only use aperture 0, enabling swapper on aperture 1
1687 * won't harm
1688 */
1689 switch (mode->bits_per_pixel) {
1690 case 16:
1691 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1692 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1693 break;
1694 case 24:
1695 case 32:
1696 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1697 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1698 break;
1699 }
1700 #endif
1701
1702 /* Clear surface registers */
1703 for (i=0; i<8; i++) {
1704 newmode->surf_lower_bound[i] = 0;
1705 newmode->surf_upper_bound[i] = 0x1f;
1706 newmode->surf_info[i] = 0;
1707 }
1708
1709 pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1710 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1711 pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1712 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1713
1714 rinfo->bpp = mode->bits_per_pixel;
1715 rinfo->depth = depth;
1716
1717 pr_debug("pixclock = %lu\n", (unsigned long)pixClock);
1718 pr_debug("freq = %lu\n", (unsigned long)freq);
1719
1720 /* We use PPLL_DIV_3 */
1721 newmode->clk_cntl_index = 0x300;
1722
1723 /* Calculate PPLL value if necessary */
1724 if (!nopllcalc)
1725 radeon_calc_pll_regs(rinfo, newmode, freq);
1726
1727 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1728
1729 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1730 unsigned int hRatio, vRatio;
1731
1732 if (mode->xres > rinfo->panel_info.xres)
1733 mode->xres = rinfo->panel_info.xres;
1734 if (mode->yres > rinfo->panel_info.yres)
1735 mode->yres = rinfo->panel_info.yres;
1736
1737 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1738 << HORZ_PANEL_SHIFT);
1739 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1740 << VERT_PANEL_SHIFT);
1741
1742 if (mode->xres != rinfo->panel_info.xres) {
1743 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1744 rinfo->panel_info.xres);
1745 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1746 (newmode->fp_horz_stretch &
1747 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1748 HORZ_AUTO_RATIO_INC)));
1749 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1750 HORZ_STRETCH_ENABLE);
1751 use_rmx = 1;
1752 }
1753 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1754
1755 if (mode->yres != rinfo->panel_info.yres) {
1756 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1757 rinfo->panel_info.yres);
1758 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1759 (newmode->fp_vert_stretch &
1760 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1761 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1762 VERT_STRETCH_ENABLE);
1763 use_rmx = 1;
1764 }
1765 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1766
1767 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1768 ~(FP_SEL_CRTC2 |
1769 FP_RMX_HVSYNC_CONTROL_EN |
1770 FP_DFP_SYNC_SEL |
1771 FP_CRT_SYNC_SEL |
1772 FP_CRTC_LOCK_8DOT |
1773 FP_USE_SHADOW_EN |
1774 FP_CRTC_USE_SHADOW_VEND |
1775 FP_CRT_SYNC_ALT));
1776
1777 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1778 FP_CRTC_DONT_SHADOW_HEND |
1779 FP_PANEL_FORMAT);
1780
1781 if (IS_R300_VARIANT(rinfo) ||
1782 (rinfo->family == CHIP_FAMILY_R200)) {
1783 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1784 if (use_rmx)
1785 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1786 else
1787 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1788 } else
1789 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1790
1791 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1792 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1793 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1794 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1795
1796 if (primary_mon == MT_LCD) {
1797 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1798 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1799 } else {
1800 /* DFP */
1801 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1802 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1803 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1804 if (IS_R300_VARIANT(rinfo) ||
1805 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1806 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1807 else
1808 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1809 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1810 }
1811
1812 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1813 (((mode->xres / 8) - 1) << 16));
1814 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1815 ((mode->yres - 1) << 16);
1816 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1817 (hsync_wid << 16) | (h_sync_pol << 23));
1818 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1819 (vsync_wid << 16) | (v_sync_pol << 23));
1820 }
1821
1822 /* do it! */
1823 if (!rinfo->asleep) {
1824 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1825 radeon_write_mode (rinfo, newmode, 0);
1826 /* (re)initialize the engine */
1827 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1828 radeonfb_engine_init (rinfo);
1829 }
1830 /* Update fix */
1831 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1832 info->fix.line_length = rinfo->pitch*64;
1833 else
1834 info->fix.line_length = mode->xres_virtual
1835 * ((mode->bits_per_pixel + 1) / 8);
1836 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1837 : FB_VISUAL_DIRECTCOLOR;
1838
1839 #ifdef CONFIG_BOOTX_TEXT
1840 /* Update debug text engine */
1841 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1842 rinfo->depth, info->fix.line_length);
1843 #endif
1844
1845 kfree(newmode);
1846 return 0;
1847 }
1848
1849 static struct fb_ops radeonfb_ops = {
1850 .owner = THIS_MODULE,
1851 .fb_check_var = radeonfb_check_var,
1852 .fb_set_par = radeonfb_set_par,
1853 .fb_setcolreg = radeonfb_setcolreg,
1854 .fb_setcmap = radeonfb_setcmap,
1855 .fb_pan_display = radeonfb_pan_display,
1856 .fb_blank = radeonfb_blank,
1857 .fb_ioctl = radeonfb_ioctl,
1858 .fb_sync = radeonfb_sync,
1859 .fb_fillrect = radeonfb_fillrect,
1860 .fb_copyarea = radeonfb_copyarea,
1861 .fb_imageblit = radeonfb_imageblit,
1862 };
1863
1864
1865 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1866 {
1867 struct fb_info *info = rinfo->info;
1868
1869 info->par = rinfo;
1870 info->pseudo_palette = rinfo->pseudo_palette;
1871 info->flags = FBINFO_DEFAULT
1872 | FBINFO_HWACCEL_IMAGEBLIT
1873 | FBINFO_HWACCEL_COPYAREA
1874 | FBINFO_HWACCEL_FILLRECT
1875 | FBINFO_HWACCEL_XPAN
1876 | FBINFO_HWACCEL_YPAN;
1877 info->fbops = &radeonfb_ops;
1878 info->screen_base = rinfo->fb_base;
1879 info->screen_size = rinfo->mapped_vram;
1880
1881 /* Fill fix common fields */
1882 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1883 info->fix.smem_start = rinfo->fb_base_phys;
1884 info->fix.smem_len = rinfo->video_ram;
1885 info->fix.type = FB_TYPE_PACKED_PIXELS;
1886 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1887 info->fix.xpanstep = 8;
1888 info->fix.ypanstep = 1;
1889 info->fix.ywrapstep = 0;
1890 info->fix.type_aux = 0;
1891 info->fix.mmio_start = rinfo->mmio_base_phys;
1892 info->fix.mmio_len = RADEON_REGSIZE;
1893 info->fix.accel = FB_ACCEL_ATI_RADEON;
1894
1895 /* Allocate colormap */
1896 fb_alloc_cmap(&info->cmap, 256, 0);
1897
1898 /* Setup pixmap used for acceleration */
1899 #define PIXMAP_SIZE (2048 * 4)
1900
1901 info->pixmap.addr = kmalloc(PIXMAP_SIZE, GFP_KERNEL);
1902 if (!info->pixmap.addr) {
1903 printk(KERN_ERR "radeonfb: Failed to allocate pixmap !\n");
1904 noaccel = 1;
1905 goto bail;
1906 }
1907 info->pixmap.size = PIXMAP_SIZE;
1908 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1909 info->pixmap.scan_align = 4;
1910 info->pixmap.buf_align = 4;
1911 info->pixmap.access_align = 32;
1912
1913 bail:
1914 if (noaccel)
1915 info->flags |= FBINFO_HWACCEL_DISABLED;
1916
1917 return 0;
1918 }
1919
1920 /*
1921 * This reconfigure the card's internal memory map. In theory, we'd like
1922 * to setup the card's memory at the same address as it's PCI bus address,
1923 * and the AGP aperture right after that so that system RAM on 32 bits
1924 * machines at least, is directly accessible. However, doing so would
1925 * conflict with the current XFree drivers...
1926 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1927 * on the proper way to set this up and duplicate this here. In the meantime,
1928 * I put the card's memory at 0 in card space and AGP at some random high
1929 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1930 */
1931 #ifdef CONFIG_PPC_OF
1932 #undef SET_MC_FB_FROM_APERTURE
1933 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1934 {
1935 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1936 u32 save_crtc_ext_cntl;
1937 u32 aper_base, aper_size;
1938 u32 agp_base;
1939
1940 /* First, we disable display to avoid interfering */
1941 if (rinfo->has_CRTC2) {
1942 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1943 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1944 }
1945 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1946 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1947
1948 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1949 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1950 mdelay(100);
1951
1952 aper_base = INREG(CONFIG_APER_0_BASE);
1953 aper_size = INREG(CONFIG_APER_SIZE);
1954
1955 #ifdef SET_MC_FB_FROM_APERTURE
1956 /* Set framebuffer to be at the same address as set in PCI BAR */
1957 OUTREG(MC_FB_LOCATION,
1958 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1959 rinfo->fb_local_base = aper_base;
1960 #else
1961 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1962 rinfo->fb_local_base = 0;
1963 #endif
1964 agp_base = aper_base + aper_size;
1965 if (agp_base & 0xf0000000)
1966 agp_base = (aper_base | 0x0fffffff) + 1;
1967
1968 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1969 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1970 * always the case on PPCs afaik.
1971 */
1972 #ifdef SET_MC_FB_FROM_APERTURE
1973 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1974 #else
1975 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1976 #endif
1977
1978 /* Fixup the display base addresses & engine offsets while we
1979 * are at it as well
1980 */
1981 #ifdef SET_MC_FB_FROM_APERTURE
1982 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1983 if (rinfo->has_CRTC2)
1984 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1985 OUTREG(OV0_BASE_ADDR, aper_base);
1986 #else
1987 OUTREG(DISPLAY_BASE_ADDR, 0);
1988 if (rinfo->has_CRTC2)
1989 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1990 OUTREG(OV0_BASE_ADDR, 0);
1991 #endif
1992 mdelay(100);
1993
1994 /* Restore display settings */
1995 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1996 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1997 if (rinfo->has_CRTC2)
1998 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1999
2000 pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
2001 aper_base,
2002 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
2003 0xffff0000 | (agp_base >> 16));
2004 }
2005 #endif /* CONFIG_PPC_OF */
2006
2007
2008 static void radeon_identify_vram(struct radeonfb_info *rinfo)
2009 {
2010 u32 tmp;
2011
2012 /* framebuffer size */
2013 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2014 (rinfo->family == CHIP_FAMILY_RS200) ||
2015 (rinfo->family == CHIP_FAMILY_RS300) ||
2016 (rinfo->family == CHIP_FAMILY_RC410) ||
2017 (rinfo->family == CHIP_FAMILY_RS400) ||
2018 (rinfo->family == CHIP_FAMILY_RS480) ) {
2019 u32 tom = INREG(NB_TOM);
2020 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2021
2022 OUTREG(MC_FB_LOCATION, tom);
2023 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2024 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2025 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2026
2027 /* This is supposed to fix the crtc2 noise problem. */
2028 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2029
2030 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2031 (rinfo->family == CHIP_FAMILY_RS200)) {
2032 /* This is to workaround the asic bug for RMX, some versions
2033 of BIOS dosen't have this register initialized correctly.
2034 */
2035 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2036 ~CRTC_H_CUTOFF_ACTIVE_EN);
2037 }
2038 } else {
2039 tmp = INREG(CONFIG_MEMSIZE);
2040 }
2041
2042 /* mem size is bits [28:0], mask off the rest */
2043 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2044
2045 /*
2046 * Hack to get around some busted production M6's
2047 * reporting no ram
2048 */
2049 if (rinfo->video_ram == 0) {
2050 switch (rinfo->pdev->device) {
2051 case PCI_CHIP_RADEON_LY:
2052 case PCI_CHIP_RADEON_LZ:
2053 rinfo->video_ram = 8192 * 1024;
2054 break;
2055 default:
2056 break;
2057 }
2058 }
2059
2060
2061 /*
2062 * Now try to identify VRAM type
2063 */
2064 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2065 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2066 rinfo->vram_ddr = 1;
2067 else
2068 rinfo->vram_ddr = 0;
2069
2070 tmp = INREG(MEM_CNTL);
2071 if (IS_R300_VARIANT(rinfo)) {
2072 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2073 switch (tmp) {
2074 case 0: rinfo->vram_width = 64; break;
2075 case 1: rinfo->vram_width = 128; break;
2076 case 2: rinfo->vram_width = 256; break;
2077 default: rinfo->vram_width = 128; break;
2078 }
2079 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2080 (rinfo->family == CHIP_FAMILY_RS100) ||
2081 (rinfo->family == CHIP_FAMILY_RS200)){
2082 if (tmp & RV100_MEM_HALF_MODE)
2083 rinfo->vram_width = 32;
2084 else
2085 rinfo->vram_width = 64;
2086 } else {
2087 if (tmp & MEM_NUM_CHANNELS_MASK)
2088 rinfo->vram_width = 128;
2089 else
2090 rinfo->vram_width = 64;
2091 }
2092
2093 /* This may not be correct, as some cards can have half of channel disabled
2094 * ToDo: identify these cases
2095 */
2096
2097 pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2098 pci_name(rinfo->pdev),
2099 rinfo->video_ram / 1024,
2100 rinfo->vram_ddr ? "DDR" : "SDRAM",
2101 rinfo->vram_width);
2102 }
2103
2104 /*
2105 * Sysfs
2106 */
2107
2108 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2109 {
2110 return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH);
2111 }
2112
2113
2114 static ssize_t radeon_show_edid1(struct kobject *kobj,
2115 struct bin_attribute *bin_attr,
2116 char *buf, loff_t off, size_t count)
2117 {
2118 struct device *dev = container_of(kobj, struct device, kobj);
2119 struct pci_dev *pdev = to_pci_dev(dev);
2120 struct fb_info *info = pci_get_drvdata(pdev);
2121 struct radeonfb_info *rinfo = info->par;
2122
2123 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2124 }
2125
2126
2127 static ssize_t radeon_show_edid2(struct kobject *kobj,
2128 struct bin_attribute *bin_attr,
2129 char *buf, loff_t off, size_t count)
2130 {
2131 struct device *dev = container_of(kobj, struct device, kobj);
2132 struct pci_dev *pdev = to_pci_dev(dev);
2133 struct fb_info *info = pci_get_drvdata(pdev);
2134 struct radeonfb_info *rinfo = info->par;
2135
2136 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2137 }
2138
2139 static struct bin_attribute edid1_attr = {
2140 .attr = {
2141 .name = "edid1",
2142 .mode = 0444,
2143 },
2144 .size = EDID_LENGTH,
2145 .read = radeon_show_edid1,
2146 };
2147
2148 static struct bin_attribute edid2_attr = {
2149 .attr = {
2150 .name = "edid2",
2151 .mode = 0444,
2152 },
2153 .size = EDID_LENGTH,
2154 .read = radeon_show_edid2,
2155 };
2156
2157
2158 static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
2159 const struct pci_device_id *ent)
2160 {
2161 struct fb_info *info;
2162 struct radeonfb_info *rinfo;
2163 int ret;
2164 unsigned char c1, c2;
2165 int err = 0;
2166
2167 pr_debug("radeonfb_pci_register BEGIN\n");
2168
2169 /* Enable device in PCI config */
2170 ret = pci_enable_device(pdev);
2171 if (ret < 0) {
2172 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2173 pci_name(pdev));
2174 goto err_out;
2175 }
2176
2177 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2178 if (!info) {
2179 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2180 pci_name(pdev));
2181 ret = -ENOMEM;
2182 goto err_disable;
2183 }
2184 rinfo = info->par;
2185 rinfo->info = info;
2186 rinfo->pdev = pdev;
2187
2188 spin_lock_init(&rinfo->reg_lock);
2189 init_timer(&rinfo->lvds_timer);
2190 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2191 rinfo->lvds_timer.data = (unsigned long)rinfo;
2192
2193 c1 = ent->device >> 8;
2194 c2 = ent->device & 0xff;
2195 if (isprint(c1) && isprint(c2))
2196 snprintf(rinfo->name, sizeof(rinfo->name),
2197 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2);
2198 else
2199 snprintf(rinfo->name, sizeof(rinfo->name),
2200 "ATI Radeon %x", ent->device & 0xffff);
2201
2202 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2203 rinfo->chipset = pdev->device;
2204 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2205 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2206 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2207
2208 /* Set base addrs */
2209 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2210 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2211
2212 /* request the mem regions */
2213 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2214 if (ret < 0) {
2215 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2216 pci_name(rinfo->pdev));
2217 goto err_release_fb;
2218 }
2219
2220 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2221 if (ret < 0) {
2222 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2223 pci_name(rinfo->pdev));
2224 goto err_release_pci0;
2225 }
2226
2227 /* map the regions */
2228 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2229 if (!rinfo->mmio_base) {
2230 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2231 pci_name(rinfo->pdev));
2232 ret = -EIO;
2233 goto err_release_pci2;
2234 }
2235
2236 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2237
2238 /*
2239 * Check for errata
2240 */
2241 rinfo->errata = 0;
2242 if (rinfo->family == CHIP_FAMILY_R300 &&
2243 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2244 == CFG_ATI_REV_A11)
2245 rinfo->errata |= CHIP_ERRATA_R300_CG;
2246
2247 if (rinfo->family == CHIP_FAMILY_RV200 ||
2248 rinfo->family == CHIP_FAMILY_RS200)
2249 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2250
2251 if (rinfo->family == CHIP_FAMILY_RV100 ||
2252 rinfo->family == CHIP_FAMILY_RS100 ||
2253 rinfo->family == CHIP_FAMILY_RS200)
2254 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2255
2256 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
2257 /* On PPC, we obtain the OF device-node pointer to the firmware
2258 * data for this chip
2259 */
2260 rinfo->of_node = pci_device_to_OF_node(pdev);
2261 if (rinfo->of_node == NULL)
2262 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2263 pci_name(rinfo->pdev));
2264
2265 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
2266 #ifdef CONFIG_PPC_OF
2267 /* On PPC, the firmware sets up a memory mapping that tends
2268 * to cause lockups when enabling the engine. We reconfigure
2269 * the card internal memory mappings properly
2270 */
2271 fixup_memory_mappings(rinfo);
2272 #endif /* CONFIG_PPC_OF */
2273
2274 /* Get VRAM size and type */
2275 radeon_identify_vram(rinfo);
2276
2277 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2278
2279 do {
2280 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2281 rinfo->mapped_vram);
2282 } while (rinfo->fb_base == NULL &&
2283 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
2284
2285 if (rinfo->fb_base == NULL) {
2286 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2287 pci_name(rinfo->pdev));
2288 ret = -EIO;
2289 goto err_unmap_rom;
2290 }
2291
2292 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2293 rinfo->mapped_vram/1024);
2294
2295 /*
2296 * Map the BIOS ROM if any and retrieve PLL parameters from
2297 * the BIOS. We skip that on mobility chips as the real panel
2298 * values we need aren't in the ROM but in the BIOS image in
2299 * memory. This is definitely not the best meacnism though,
2300 * we really need the arch code to tell us which is the "primary"
2301 * video adapter to use the memory image (or better, the arch
2302 * should provide us a copy of the BIOS image to shield us from
2303 * archs who would store that elsewhere and/or could initialize
2304 * more than one adapter during boot).
2305 */
2306 if (!rinfo->is_mobility)
2307 radeon_map_ROM(rinfo, pdev);
2308
2309 /*
2310 * On x86, the primary display on laptop may have it's BIOS
2311 * ROM elsewhere, try to locate it at the legacy memory hole.
2312 * We probably need to make sure this is the primary display,
2313 * but that is difficult without some arch support.
2314 */
2315 #ifdef CONFIG_X86
2316 if (rinfo->bios_seg == NULL)
2317 radeon_find_mem_vbios(rinfo);
2318 #endif
2319
2320 /* If both above failed, try the BIOS ROM again for mobility
2321 * chips
2322 */
2323 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2324 radeon_map_ROM(rinfo, pdev);
2325
2326 /* Get informations about the board's PLL */
2327 radeon_get_pllinfo(rinfo);
2328
2329 #ifdef CONFIG_FB_RADEON_I2C
2330 /* Register I2C bus */
2331 radeon_create_i2c_busses(rinfo);
2332 #endif
2333
2334 /* set all the vital stuff */
2335 radeon_set_fbinfo (rinfo);
2336
2337 /* Probe screen types */
2338 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2339
2340 /* Build mode list, check out panel native model */
2341 radeon_check_modes(rinfo, mode_option);
2342
2343 /* Register some sysfs stuff (should be done better) */
2344 if (rinfo->mon1_EDID)
2345 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2346 &edid1_attr);
2347 if (rinfo->mon2_EDID)
2348 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2349 &edid2_attr);
2350 if (err)
2351 pr_warning("%s() Creating sysfs files failed, continuing\n",
2352 __func__);
2353
2354 /* save current mode regs before we switch into the new one
2355 * so we can restore this upon __exit
2356 */
2357 radeon_save_state (rinfo, &rinfo->init_state);
2358 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2359
2360 /* Setup Power Management capabilities */
2361 if (default_dynclk < -1) {
2362 /* -2 is special: means ON on mobility chips and do not
2363 * change on others
2364 */
2365 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2366 } else
2367 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2368
2369 pci_set_drvdata(pdev, info);
2370
2371 /* Register with fbdev layer */
2372 ret = register_framebuffer(info);
2373 if (ret < 0) {
2374 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2375 pci_name(rinfo->pdev));
2376 goto err_unmap_fb;
2377 }
2378
2379 #ifdef CONFIG_MTRR
2380 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2381 rinfo->video_ram,
2382 MTRR_TYPE_WRCOMB, 1);
2383 #endif
2384
2385 if (backlight)
2386 radeonfb_bl_init(rinfo);
2387
2388 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2389
2390 if (rinfo->bios_seg)
2391 radeon_unmap_ROM(rinfo, pdev);
2392 pr_debug("radeonfb_pci_register END\n");
2393
2394 return 0;
2395 err_unmap_fb:
2396 iounmap(rinfo->fb_base);
2397 err_unmap_rom:
2398 kfree(rinfo->mon1_EDID);
2399 kfree(rinfo->mon2_EDID);
2400 if (rinfo->mon1_modedb)
2401 fb_destroy_modedb(rinfo->mon1_modedb);
2402 fb_dealloc_cmap(&info->cmap);
2403 #ifdef CONFIG_FB_RADEON_I2C
2404 radeon_delete_i2c_busses(rinfo);
2405 #endif
2406 if (rinfo->bios_seg)
2407 radeon_unmap_ROM(rinfo, pdev);
2408 iounmap(rinfo->mmio_base);
2409 err_release_pci2:
2410 pci_release_region(pdev, 2);
2411 err_release_pci0:
2412 pci_release_region(pdev, 0);
2413 err_release_fb:
2414 framebuffer_release(info);
2415 err_disable:
2416 err_out:
2417 return ret;
2418 }
2419
2420
2421
2422 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2423 {
2424 struct fb_info *info = pci_get_drvdata(pdev);
2425 struct radeonfb_info *rinfo = info->par;
2426
2427 if (!rinfo)
2428 return;
2429
2430 radeonfb_pm_exit(rinfo);
2431
2432 if (rinfo->mon1_EDID)
2433 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2434 if (rinfo->mon2_EDID)
2435 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2436
2437 #if 0
2438 /* restore original state
2439 *
2440 * Doesn't quite work yet, I suspect if we come from a legacy
2441 * VGA mode (or worse, text mode), we need to do some VGA black
2442 * magic here that I know nothing about. --BenH
2443 */
2444 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2445 #endif
2446
2447 del_timer_sync(&rinfo->lvds_timer);
2448
2449 #ifdef CONFIG_MTRR
2450 if (rinfo->mtrr_hdl >= 0)
2451 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2452 #endif
2453
2454 unregister_framebuffer(info);
2455
2456 radeonfb_bl_exit(rinfo);
2457
2458 iounmap(rinfo->mmio_base);
2459 iounmap(rinfo->fb_base);
2460
2461 pci_release_region(pdev, 2);
2462 pci_release_region(pdev, 0);
2463
2464 kfree(rinfo->mon1_EDID);
2465 kfree(rinfo->mon2_EDID);
2466 if (rinfo->mon1_modedb)
2467 fb_destroy_modedb(rinfo->mon1_modedb);
2468 #ifdef CONFIG_FB_RADEON_I2C
2469 radeon_delete_i2c_busses(rinfo);
2470 #endif
2471 fb_dealloc_cmap(&info->cmap);
2472 framebuffer_release(info);
2473 }
2474
2475
2476 static struct pci_driver radeonfb_driver = {
2477 .name = "radeonfb",
2478 .id_table = radeonfb_pci_table,
2479 .probe = radeonfb_pci_register,
2480 .remove = __devexit_p(radeonfb_pci_unregister),
2481 #ifdef CONFIG_PM
2482 .suspend = radeonfb_pci_suspend,
2483 .resume = radeonfb_pci_resume,
2484 #endif /* CONFIG_PM */
2485 };
2486
2487 #ifndef MODULE
2488 static int __init radeonfb_setup (char *options)
2489 {
2490 char *this_opt;
2491
2492 if (!options || !*options)
2493 return 0;
2494
2495 while ((this_opt = strsep (&options, ",")) != NULL) {
2496 if (!*this_opt)
2497 continue;
2498
2499 if (!strncmp(this_opt, "noaccel", 7)) {
2500 noaccel = 1;
2501 } else if (!strncmp(this_opt, "mirror", 6)) {
2502 mirror = 1;
2503 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2504 force_dfp = 1;
2505 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2506 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2507 } else if (!strncmp(this_opt, "backlight:", 10)) {
2508 backlight = simple_strtoul(this_opt+10, NULL, 0);
2509 #ifdef CONFIG_MTRR
2510 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2511 nomtrr = 1;
2512 #endif
2513 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2514 nomodeset = 1;
2515 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2516 force_measure_pll = 1;
2517 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2518 ignore_edid = 1;
2519 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2520 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2521 force_sleep = 1;
2522 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2523 ignore_devlist = 1;
2524 #endif
2525 } else if (!strncmp(this_opt, "accel_cexp", 12)) {
2526 accel_cexp = 1;
2527 } else
2528 mode_option = this_opt;
2529 }
2530 return 0;
2531 }
2532 #endif /* MODULE */
2533
2534 static int __init radeonfb_init (void)
2535 {
2536 #ifndef MODULE
2537 char *option = NULL;
2538
2539 if (fb_get_options("radeonfb", &option))
2540 return -ENODEV;
2541 radeonfb_setup(option);
2542 #endif
2543 return pci_register_driver (&radeonfb_driver);
2544 }
2545
2546
2547 static void __exit radeonfb_exit (void)
2548 {
2549 pci_unregister_driver (&radeonfb_driver);
2550 }
2551
2552 module_init(radeonfb_init);
2553 module_exit(radeonfb_exit);
2554
2555 MODULE_AUTHOR("Ani Joshi");
2556 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2557 MODULE_LICENSE("GPL");
2558 module_param(noaccel, bool, 0);
2559 module_param(default_dynclk, int, 0);
2560 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2561 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2562 module_param(nomodeset, bool, 0);
2563 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2564 module_param(mirror, bool, 0);
2565 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2566 module_param(force_dfp, bool, 0);
2567 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2568 module_param(ignore_edid, bool, 0);
2569 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2570 module_param(monitor_layout, charp, 0);
2571 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2572 module_param(force_measure_pll, bool, 0);
2573 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2574 module_param(accel_cexp, bool, 0);
2575 MODULE_PARM_DESC(accel_cexp, "Use acceleration engine for color expansion");
2576 #ifdef CONFIG_MTRR
2577 module_param(nomtrr, bool, 0);
2578 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2579 #endif
2580 module_param(panel_yres, int, 0);
2581 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2582 module_param(mode_option, charp, 0);
2583 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2584 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2585 module_param(force_sleep, bool, 0);
2586 MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2587 module_param(ignore_devlist, bool, 0);
2588 MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2589 #endif
Stable & featurefull patchset based on Linus's git branch