arch/sh/mm/tlb-sh4.c

   1 /*
   2  * arch/sh/mm/tlb-sh4.c
   3  *
   4  * SH-4 specific TLB operations
   5  *
   6  * Copyright (C) 1999  Niibe Yutaka
   7  * Copyright (C) 2002  Paul Mundt
   8  *
   9  * Released under the terms of the GNU GPL v2.0.
  10  */
  11 #include <linux/signal.h>
  12 #include <linux/sched.h>
  13 #include <linux/kernel.h>
  14 #include <linux/errno.h>
  15 #include <linux/string.h>
  16 #include <linux/types.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/mman.h>
  19 #include <linux/mm.h>
  20 #include <linux/smp.h>
  21 #include <linux/smp_lock.h>
  22 #include <linux/interrupt.h>
  23
  24 #include <asm/system.h>
  25 #include <asm/io.h>
  26 #include <asm/uaccess.h>
  27 #include <asm/pgalloc.h>
  28 #include <asm/mmu_context.h>
  29 #include <asm/cacheflush.h>
  30
  31 void update_mmu_cache(struct vm_area_struct * vma,
  32                       unsigned long address, pte_t pte)
  33 {
  34         unsigned long flags;
  35         unsigned long pteval;
  36         unsigned long vpn;
  37
  38         /* Ptrace may call this routine. */
  39         if (vma && current->active_mm != vma->vm_mm)
  40                 return;
  41
  42 #ifndef CONFIG_CACHE_OFF
  43         {
  44                 unsigned long pfn = pte_pfn(pte);
  45
  46                 if (pfn_valid(pfn)) {
  47                         struct page *page = pfn_to_page(pfn);
  48
  49                         if (!test_bit(PG_mapped, &page->flags)) {
  50                                 unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
  51                                 __flush_wback_region((void *)P1SEGADDR(phys),
  52                                                      PAGE_SIZE);
  53                                 __set_bit(PG_mapped, &page->flags);
  54                         }
  55                 }
  56         }
  57 #endif
  58
  59         local_irq_save(flags);
  60
  61         /* Set PTEH register */
  62         vpn = (address & MMU_VPN_MASK) | get_asid();
  63         ctrl_outl(vpn, MMU_PTEH);
  64
  65         pteval = pte_val(pte);
  66
  67         /* Set PTEA register */
  68         if (cpu_data->flags & CPU_HAS_PTEA)
  69                 /* TODO: make this look less hacky */
  70                 ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA);
  71
  72         /* Set PTEL register */
  73         pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
  74 #ifdef CONFIG_CACHE_WRITETHROUGH
  75         pteval |= _PAGE_WT;
  76 #endif
  77         /* conveniently, we want all the software flags to be 0 anyway */
  78         ctrl_outl(pteval, MMU_PTEL);
  79
  80         /* Load the TLB */
  81         asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
  82         local_irq_restore(flags);
  83 }
  84
  85 void local_flush_tlb_one(unsigned long asid, unsigned long page)
  86 {
  87         unsigned long addr, data;
  88
  89         /*
  90          * NOTE: PTEH.ASID should be set to this MM
  91          *       _AND_ we need to write ASID to the array.
  92          *
  93          * It would be simple if we didn't need to set PTEH.ASID...
  94          */
  95         addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
  96         data = page | asid; /* VALID bit is off */
  97         jump_to_P2();
  98         ctrl_outl(data, addr);
  99         back_to_P1();
 100 }
 101