2 * sata_nv.c - NVIDIA nForce SATA
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
34 #include <linux/config.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
46 #define DRV_NAME "sata_nv"
47 #define DRV_VERSION "0.9"
54 NV_PORT0_SCR_REG_OFFSET
= 0x00,
55 NV_PORT1_SCR_REG_OFFSET
= 0x40,
58 NV_INT_STATUS_CK804
= 0x440,
59 NV_INT_STATUS_PDEV_INT
= 0x01,
60 NV_INT_STATUS_PDEV_PM
= 0x02,
61 NV_INT_STATUS_PDEV_ADDED
= 0x04,
62 NV_INT_STATUS_PDEV_REMOVED
= 0x08,
63 NV_INT_STATUS_SDEV_INT
= 0x10,
64 NV_INT_STATUS_SDEV_PM
= 0x20,
65 NV_INT_STATUS_SDEV_ADDED
= 0x40,
66 NV_INT_STATUS_SDEV_REMOVED
= 0x80,
69 NV_INT_ENABLE_CK804
= 0x441,
70 NV_INT_ENABLE_PDEV_MASK
= 0x01,
71 NV_INT_ENABLE_PDEV_PM
= 0x02,
72 NV_INT_ENABLE_PDEV_ADDED
= 0x04,
73 NV_INT_ENABLE_PDEV_REMOVED
= 0x08,
74 NV_INT_ENABLE_SDEV_MASK
= 0x10,
75 NV_INT_ENABLE_SDEV_PM
= 0x20,
76 NV_INT_ENABLE_SDEV_ADDED
= 0x40,
77 NV_INT_ENABLE_SDEV_REMOVED
= 0x80,
80 NV_INT_CONFIG_METHD
= 0x01, // 0 = INT, 1 = SMI
82 // For PCI config register 20
83 NV_MCP_SATA_CFG_20
= 0x50,
84 NV_MCP_SATA_CFG_20_SATA_SPACE_EN
= 0x04,
87 static int nv_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
88 static irqreturn_t
nv_interrupt (int irq
, void *dev_instance
,
89 struct pt_regs
*regs
);
90 static u32
nv_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
91 static void nv_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
101 static const struct pci_device_id nv_pci_tbl
[] = {
102 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA
,
103 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, NFORCE2
},
104 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA
,
105 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, NFORCE3
},
106 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2
,
107 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, NFORCE3
},
108 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA
,
109 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CK804
},
110 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2
,
111 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CK804
},
112 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA
,
113 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CK804
},
114 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2
,
115 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CK804
},
116 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA
,
117 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, GENERIC
},
118 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2
,
119 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, GENERIC
},
120 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA
,
121 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, GENERIC
},
122 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2
,
123 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, GENERIC
},
124 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA
,
125 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, GENERIC
},
126 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2
,
127 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, GENERIC
},
128 { PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3
,
129 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, GENERIC
},
130 { PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
131 PCI_ANY_ID
, PCI_ANY_ID
,
132 PCI_CLASS_STORAGE_IDE
<<8, 0xffff00, GENERIC
},
133 { PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
134 PCI_ANY_ID
, PCI_ANY_ID
,
135 PCI_CLASS_STORAGE_RAID
<<8, 0xffff00, GENERIC
},
136 { 0, } /* terminate list */
139 static struct pci_driver nv_pci_driver
= {
141 .id_table
= nv_pci_tbl
,
142 .probe
= nv_init_one
,
143 .remove
= ata_pci_remove_one
,
146 static struct scsi_host_template nv_sht
= {
147 .module
= THIS_MODULE
,
149 .ioctl
= ata_scsi_ioctl
,
150 .queuecommand
= ata_scsi_queuecmd
,
151 .can_queue
= ATA_DEF_QUEUE
,
152 .this_id
= ATA_SHT_THIS_ID
,
153 .sg_tablesize
= LIBATA_MAX_PRD
,
154 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
155 .emulated
= ATA_SHT_EMULATED
,
156 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
157 .proc_name
= DRV_NAME
,
158 .dma_boundary
= ATA_DMA_BOUNDARY
,
159 .slave_configure
= ata_scsi_slave_config
,
160 .slave_destroy
= ata_scsi_slave_destroy
,
161 .bios_param
= ata_std_bios_param
,
164 static const struct ata_port_operations nv_ops
= {
165 .port_disable
= ata_port_disable
,
166 .tf_load
= ata_tf_load
,
167 .tf_read
= ata_tf_read
,
168 .exec_command
= ata_exec_command
,
169 .check_status
= ata_check_status
,
170 .dev_select
= ata_std_dev_select
,
171 .phy_reset
= sata_phy_reset
,
172 .bmdma_setup
= ata_bmdma_setup
,
173 .bmdma_start
= ata_bmdma_start
,
174 .bmdma_stop
= ata_bmdma_stop
,
175 .bmdma_status
= ata_bmdma_status
,
176 .qc_prep
= ata_qc_prep
,
177 .qc_issue
= ata_qc_issue_prot
,
178 .eng_timeout
= ata_eng_timeout
,
179 .data_xfer
= ata_pio_data_xfer
,
180 .irq_handler
= nv_interrupt
,
181 .irq_clear
= ata_bmdma_irq_clear
,
182 .scr_read
= nv_scr_read
,
183 .scr_write
= nv_scr_write
,
184 .port_start
= ata_port_start
,
185 .port_stop
= ata_port_stop
,
186 .host_stop
= ata_pci_host_stop
,
189 /* FIXME: The hardware provides the necessary SATA PHY controls
190 * to support ATA_FLAG_SATA_RESET. However, it is currently
191 * necessary to disable that flag, to solve misdetection problems.
192 * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
194 * This problem really needs to be investigated further. But in the
195 * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
197 static struct ata_port_info nv_port_info
= {
199 .host_flags
= ATA_FLAG_SATA
|
200 /* ATA_FLAG_SATA_RESET | */
203 .pio_mask
= NV_PIO_MASK
,
204 .mwdma_mask
= NV_MWDMA_MASK
,
205 .udma_mask
= NV_UDMA_MASK
,
209 MODULE_AUTHOR("NVIDIA");
210 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
211 MODULE_LICENSE("GPL");
212 MODULE_DEVICE_TABLE(pci
, nv_pci_tbl
);
213 MODULE_VERSION(DRV_VERSION
);
215 static irqreturn_t
nv_interrupt (int irq
, void *dev_instance
,
216 struct pt_regs
*regs
)
218 struct ata_host_set
*host_set
= dev_instance
;
220 unsigned int handled
= 0;
223 spin_lock_irqsave(&host_set
->lock
, flags
);
225 for (i
= 0; i
< host_set
->n_ports
; i
++) {
228 ap
= host_set
->ports
[i
];
230 !(ap
->flags
& ATA_FLAG_DISABLED
)) {
231 struct ata_queued_cmd
*qc
;
233 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
234 if (qc
&& (!(qc
->tf
.flags
& ATA_TFLAG_POLLING
)))
235 handled
+= ata_host_intr(ap
, qc
);
237 // No request pending? Clear interrupt status
238 // anyway, in case there's one pending.
239 ap
->ops
->check_status(ap
);
244 spin_unlock_irqrestore(&host_set
->lock
, flags
);
246 return IRQ_RETVAL(handled
);
249 static u32
nv_scr_read (struct ata_port
*ap
, unsigned int sc_reg
)
251 if (sc_reg
> SCR_CONTROL
)
254 return ioread32((void __iomem
*)ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
257 static void nv_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
)
259 if (sc_reg
> SCR_CONTROL
)
262 iowrite32(val
, (void __iomem
*)ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
265 static int nv_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
267 static int printed_version
= 0;
268 struct ata_port_info
*ppi
;
269 struct ata_probe_ent
*probe_ent
;
270 int pci_dev_busy
= 0;
275 // Make sure this is a SATA controller by counting the number of bars
276 // (NVIDIA SATA controllers will always have six bars). Otherwise,
277 // it's an IDE controller and we ignore it.
278 for (bar
=0; bar
<6; bar
++)
279 if (pci_resource_start(pdev
, bar
) == 0)
282 if (!printed_version
++)
283 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
285 rc
= pci_enable_device(pdev
);
289 rc
= pci_request_regions(pdev
, DRV_NAME
);
292 goto err_out_disable
;
295 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
297 goto err_out_regions
;
298 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
300 goto err_out_regions
;
305 probe_ent
= ata_pci_init_native_mode(pdev
, &ppi
, ATA_PORT_PRIMARY
| ATA_PORT_SECONDARY
);
307 goto err_out_regions
;
309 probe_ent
->mmio_base
= pci_iomap(pdev
, 5, 0);
310 if (!probe_ent
->mmio_base
) {
312 goto err_out_free_ent
;
315 base
= (unsigned long)probe_ent
->mmio_base
;
317 probe_ent
->port
[0].scr_addr
= base
+ NV_PORT0_SCR_REG_OFFSET
;
318 probe_ent
->port
[1].scr_addr
= base
+ NV_PORT1_SCR_REG_OFFSET
;
320 pci_set_master(pdev
);
322 rc
= ata_device_add(probe_ent
);
324 goto err_out_iounmap
;
331 pci_iounmap(pdev
, probe_ent
->mmio_base
);
335 pci_release_regions(pdev
);
338 pci_disable_device(pdev
);
343 static int __init
nv_init(void)
345 return pci_module_init(&nv_pci_driver
);
348 static void __exit
nv_exit(void)
350 pci_unregister_driver(&nv_pci_driver
);
353 module_init(nv_init
);
354 module_exit(nv_exit
);