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IB/mlx4: Fix up SRQ limit_watermark endianness
[linux-2.6/zen-sources.git] / drivers / net / amd8111e.c
bloba61b2f89fc336c3f7bc75a9f2dece28c37124586
1
2 /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
3 * Copyright (C) 2004 Advanced Micro Devices
4 *
5 *
6 * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
7 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
8 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
9 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
10 * Copyright 1993 United States Government as represented by the
11 * Director, National Security Agency.[ pcnet32.c ]
12 * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
13 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
14 *
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
29 * USA
30
31 Module Name:
32
33 amd8111e.c
34
35 Abstract:
36
37 AMD8111 based 10/100 Ethernet Controller Driver.
38
39 Environment:
40
41 Kernel Mode
42
43 Revision History:
44 3.0.0
45 Initial Revision.
46 3.0.1
47 1. Dynamic interrupt coalescing.
48 2. Removed prev_stats.
49 3. MII support.
50 4. Dynamic IPG support
51 3.0.2 05/29/2003
52 1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
53 2. Bug fix: Fixed VLAN support failure.
54 3. Bug fix: Fixed receive interrupt coalescing bug.
55 4. Dynamic IPG support is disabled by default.
56 3.0.3 06/05/2003
57 1. Bug fix: Fixed failure to close the interface if SMP is enabled.
58 3.0.4 12/09/2003
59 1. Added set_mac_address routine for bonding driver support.
60 2. Tested the driver for bonding support
61 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
62 indicated to the h/w.
63 4. Modified amd8111e_rx() routine to receive all the received packets
64 in the first interrupt.
65 5. Bug fix: Corrected rx_errors reported in get_stats() function.
66 3.0.5 03/22/2004
67 1. Added NAPI support
68
69 */
70
71
72 #include <linux/module.h>
73 #include <linux/kernel.h>
74 #include <linux/types.h>
75 #include <linux/compiler.h>
76 #include <linux/slab.h>
77 #include <linux/delay.h>
78 #include <linux/init.h>
79 #include <linux/ioport.h>
80 #include <linux/pci.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/skbuff.h>
84 #include <linux/ethtool.h>
85 #include <linux/mii.h>
86 #include <linux/if_vlan.h>
87 #include <linux/ctype.h>
88 #include <linux/crc32.h>
89 #include <linux/dma-mapping.h>
90
91 #include <asm/system.h>
92 #include <asm/io.h>
93 #include <asm/byteorder.h>
94 #include <asm/uaccess.h>
95
96 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
97 #define AMD8111E_VLAN_TAG_USED 1
98 #else
99 #define AMD8111E_VLAN_TAG_USED 0
100 #endif
101
102 #include "amd8111e.h"
103 #define MODULE_NAME "amd8111e"
104 #define MODULE_VERS "3.0.6"
105 MODULE_AUTHOR("Advanced Micro Devices, Inc.");
106 MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version 3.0.6");
107 MODULE_LICENSE("GPL");
108 MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
109 module_param_array(speed_duplex, int, NULL, 0);
110 MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
111 module_param_array(coalesce, bool, NULL, 0);
112 MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
113 module_param_array(dynamic_ipg, bool, NULL, 0);
114 MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
115
116 static struct pci_device_id amd8111e_pci_tbl[] = {
117
118 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
120 { 0, }
121
122 };
123 /*
124 This function will read the PHY registers.
125 */
126 static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
127 {
128 void __iomem *mmio = lp->mmio;
129 unsigned int reg_val;
130 unsigned int repeat= REPEAT_CNT;
131
132 reg_val = readl(mmio + PHY_ACCESS);
133 while (reg_val & PHY_CMD_ACTIVE)
134 reg_val = readl( mmio + PHY_ACCESS );
135
136 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
137 ((reg & 0x1f) << 16), mmio +PHY_ACCESS);
138 do{
139 reg_val = readl(mmio + PHY_ACCESS);
140 udelay(30); /* It takes 30 us to read/write data */
141 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
142 if(reg_val & PHY_RD_ERR)
143 goto err_phy_read;
144
145 *val = reg_val & 0xffff;
146 return 0;
147 err_phy_read:
148 *val = 0;
149 return -EINVAL;
150
151 }
152
153 /*
154 This function will write into PHY registers.
155 */
156 static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
157 {
158 unsigned int repeat = REPEAT_CNT;
159 void __iomem *mmio = lp->mmio;
160 unsigned int reg_val;
161
162 reg_val = readl(mmio + PHY_ACCESS);
163 while (reg_val & PHY_CMD_ACTIVE)
164 reg_val = readl( mmio + PHY_ACCESS );
165
166 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
167 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
168
169 do{
170 reg_val = readl(mmio + PHY_ACCESS);
171 udelay(30); /* It takes 30 us to read/write the data */
172 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
173
174 if(reg_val & PHY_RD_ERR)
175 goto err_phy_write;
176
177 return 0;
178
179 err_phy_write:
180 return -EINVAL;
181
182 }
183 /*
184 This is the mii register read function provided to the mii interface.
185 */
186 static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
187 {
188 struct amd8111e_priv* lp = netdev_priv(dev);
189 unsigned int reg_val;
190
191 amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
192 return reg_val;
193
194 }
195
196 /*
197 This is the mii register write function provided to the mii interface.
198 */
199 static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
200 {
201 struct amd8111e_priv* lp = netdev_priv(dev);
202
203 amd8111e_write_phy(lp, phy_id, reg_num, val);
204 }
205
206 /*
207 This function will set PHY speed. During initialization sets the original speed to 100 full.
208 */
209 static void amd8111e_set_ext_phy(struct net_device *dev)
210 {
211 struct amd8111e_priv *lp = netdev_priv(dev);
212 u32 bmcr,advert,tmp;
213
214 /* Determine mii register values to set the speed */
215 advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
216 tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
217 switch (lp->ext_phy_option){
218
219 default:
220 case SPEED_AUTONEG: /* advertise all values */
221 tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
222 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
223 break;
224 case SPEED10_HALF:
225 tmp |= ADVERTISE_10HALF;
226 break;
227 case SPEED10_FULL:
228 tmp |= ADVERTISE_10FULL;
229 break;
230 case SPEED100_HALF:
231 tmp |= ADVERTISE_100HALF;
232 break;
233 case SPEED100_FULL:
234 tmp |= ADVERTISE_100FULL;
235 break;
236 }
237
238 if(advert != tmp)
239 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
240 /* Restart auto negotiation */
241 bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
242 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
243 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
244
245 }
246
247 /*
248 This function will unmap skb->data space and will free
249 all transmit and receive skbuffs.
250 */
251 static int amd8111e_free_skbs(struct net_device *dev)
252 {
253 struct amd8111e_priv *lp = netdev_priv(dev);
254 struct sk_buff* rx_skbuff;
255 int i;
256
257 /* Freeing transmit skbs */
258 for(i = 0; i < NUM_TX_BUFFERS; i++){
259 if(lp->tx_skbuff[i]){
260 pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
261 dev_kfree_skb (lp->tx_skbuff[i]);
262 lp->tx_skbuff[i] = NULL;
263 lp->tx_dma_addr[i] = 0;
264 }
265 }
266 /* Freeing previously allocated receive buffers */
267 for (i = 0; i < NUM_RX_BUFFERS; i++){
268 rx_skbuff = lp->rx_skbuff[i];
269 if(rx_skbuff != NULL){
270 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
271 lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
272 dev_kfree_skb(lp->rx_skbuff[i]);
273 lp->rx_skbuff[i] = NULL;
274 lp->rx_dma_addr[i] = 0;
275 }
276 }
277
278 return 0;
279 }
280
281 /*
282 This will set the receive buffer length corresponding to the mtu size of networkinterface.
283 */
284 static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
285 {
286 struct amd8111e_priv* lp = netdev_priv(dev);
287 unsigned int mtu = dev->mtu;
288
289 if (mtu > ETH_DATA_LEN){
290 /* MTU + ethernet header + FCS
291 + optional VLAN tag + skb reserve space 2 */
292
293 lp->rx_buff_len = mtu + ETH_HLEN + 10;
294 lp->options |= OPTION_JUMBO_ENABLE;
295 } else{
296 lp->rx_buff_len = PKT_BUFF_SZ;
297 lp->options &= ~OPTION_JUMBO_ENABLE;
298 }
299 }
300
301 /*
302 This function will free all the previously allocated buffers, determine new receive buffer length and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
303 */
304 static int amd8111e_init_ring(struct net_device *dev)
305 {
306 struct amd8111e_priv *lp = netdev_priv(dev);
307 int i;
308
309 lp->rx_idx = lp->tx_idx = 0;
310 lp->tx_complete_idx = 0;
311 lp->tx_ring_idx = 0;
312
313
314 if(lp->opened)
315 /* Free previously allocated transmit and receive skbs */
316 amd8111e_free_skbs(dev);
317
318 else{
319 /* allocate the tx and rx descriptors */
320 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
321 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
322 &lp->tx_ring_dma_addr)) == NULL)
323
324 goto err_no_mem;
325
326 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
327 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
328 &lp->rx_ring_dma_addr)) == NULL)
329
330 goto err_free_tx_ring;
331
332 }
333 /* Set new receive buff size */
334 amd8111e_set_rx_buff_len(dev);
335
336 /* Allocating receive skbs */
337 for (i = 0; i < NUM_RX_BUFFERS; i++) {
338
339 if (!(lp->rx_skbuff[i] = dev_alloc_skb(lp->rx_buff_len))) {
340 /* Release previos allocated skbs */
341 for(--i; i >= 0 ;i--)
342 dev_kfree_skb(lp->rx_skbuff[i]);
343 goto err_free_rx_ring;
344 }
345 skb_reserve(lp->rx_skbuff[i],2);
346 }
347 /* Initilaizing receive descriptors */
348 for (i = 0; i < NUM_RX_BUFFERS; i++) {
349 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
350 lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
351
352 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
353 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
354 wmb();
355 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
356 }
357
358 /* Initializing transmit descriptors */
359 for (i = 0; i < NUM_TX_RING_DR; i++) {
360 lp->tx_ring[i].buff_phy_addr = 0;
361 lp->tx_ring[i].tx_flags = 0;
362 lp->tx_ring[i].buff_count = 0;
363 }
364
365 return 0;
366
367 err_free_rx_ring:
368
369 pci_free_consistent(lp->pci_dev,
370 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
371 lp->rx_ring_dma_addr);
372
373 err_free_tx_ring:
374
375 pci_free_consistent(lp->pci_dev,
376 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
377 lp->tx_ring_dma_addr);
378
379 err_no_mem:
380 return -ENOMEM;
381 }
382 /* This function will set the interrupt coalescing according to the input arguments */
383 static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
384 {
385 unsigned int timeout;
386 unsigned int event_count;
387
388 struct amd8111e_priv *lp = netdev_priv(dev);
389 void __iomem *mmio = lp->mmio;
390 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
391
392
393 switch(cmod)
394 {
395 case RX_INTR_COAL :
396 timeout = coal_conf->rx_timeout;
397 event_count = coal_conf->rx_event_count;
398 if( timeout > MAX_TIMEOUT ||
399 event_count > MAX_EVENT_COUNT )
400 return -EINVAL;
401
402 timeout = timeout * DELAY_TIMER_CONV;
403 writel(VAL0|STINTEN, mmio+INTEN0);
404 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
405 mmio+DLY_INT_A);
406 break;
407
408 case TX_INTR_COAL :
409 timeout = coal_conf->tx_timeout;
410 event_count = coal_conf->tx_event_count;
411 if( timeout > MAX_TIMEOUT ||
412 event_count > MAX_EVENT_COUNT )
413 return -EINVAL;
414
415
416 timeout = timeout * DELAY_TIMER_CONV;
417 writel(VAL0|STINTEN,mmio+INTEN0);
418 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
419 mmio+DLY_INT_B);
420 break;
421
422 case DISABLE_COAL:
423 writel(0,mmio+STVAL);
424 writel(STINTEN, mmio+INTEN0);
425 writel(0, mmio +DLY_INT_B);
426 writel(0, mmio+DLY_INT_A);
427 break;
428 case ENABLE_COAL:
429 /* Start the timer */
430 writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */
431 writel(VAL0|STINTEN, mmio+INTEN0);
432 break;
433 default:
434 break;
435
436 }
437 return 0;
438
439 }
440
441 /*
442 This function initializes the device registers and starts the device.
443 */
444 static int amd8111e_restart(struct net_device *dev)
445 {
446 struct amd8111e_priv *lp = netdev_priv(dev);
447 void __iomem *mmio = lp->mmio;
448 int i,reg_val;
449
450 /* stop the chip */
451 writel(RUN, mmio + CMD0);
452
453 if(amd8111e_init_ring(dev))
454 return -ENOMEM;
455
456 /* enable the port manager and set auto negotiation always */
457 writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
458 writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
459
460 amd8111e_set_ext_phy(dev);
461
462 /* set control registers */
463 reg_val = readl(mmio + CTRL1);
464 reg_val &= ~XMTSP_MASK;
465 writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
466
467 /* enable interrupt */
468 writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
469 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
470 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
471
472 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
473
474 /* initialize tx and rx ring base addresses */
475 writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
476 writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
477
478 writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
479 writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
480
481 /* set default IPG to 96 */
482 writew((u32)DEFAULT_IPG,mmio+IPG);
483 writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
484
485 if(lp->options & OPTION_JUMBO_ENABLE){
486 writel((u32)VAL2|JUMBO, mmio + CMD3);
487 /* Reset REX_UFLO */
488 writel( REX_UFLO, mmio + CMD2);
489 /* Should not set REX_UFLO for jumbo frames */
490 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
491 }else{
492 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
493 writel((u32)JUMBO, mmio + CMD3);
494 }
495
496 #if AMD8111E_VLAN_TAG_USED
497 writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
498 #endif
499 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
500
501 /* Setting the MAC address to the device */
502 for(i = 0; i < ETH_ADDR_LEN; i++)
503 writeb( dev->dev_addr[i], mmio + PADR + i );
504
505 /* Enable interrupt coalesce */
506 if(lp->options & OPTION_INTR_COAL_ENABLE){
507 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
508 dev->name);
509 amd8111e_set_coalesce(dev,ENABLE_COAL);
510 }
511
512 /* set RUN bit to start the chip */
513 writel(VAL2 | RDMD0, mmio + CMD0);
514 writel(VAL0 | INTREN | RUN, mmio + CMD0);
515
516 /* To avoid PCI posting bug */
517 readl(mmio+CMD0);
518 return 0;
519 }
520 /*
521 This function clears necessary the device registers.
522 */
523 static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
524 {
525 unsigned int reg_val;
526 unsigned int logic_filter[2] ={0,};
527 void __iomem *mmio = lp->mmio;
528
529
530 /* stop the chip */
531 writel(RUN, mmio + CMD0);
532
533 /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
534 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
535
536 /* Clear RCV_RING_BASE_ADDR */
537 writel(0, mmio + RCV_RING_BASE_ADDR0);
538
539 /* Clear XMT_RING_BASE_ADDR */
540 writel(0, mmio + XMT_RING_BASE_ADDR0);
541 writel(0, mmio + XMT_RING_BASE_ADDR1);
542 writel(0, mmio + XMT_RING_BASE_ADDR2);
543 writel(0, mmio + XMT_RING_BASE_ADDR3);
544
545 /* Clear CMD0 */
546 writel(CMD0_CLEAR,mmio + CMD0);
547
548 /* Clear CMD2 */
549 writel(CMD2_CLEAR, mmio +CMD2);
550
551 /* Clear CMD7 */
552 writel(CMD7_CLEAR , mmio + CMD7);
553
554 /* Clear DLY_INT_A and DLY_INT_B */
555 writel(0x0, mmio + DLY_INT_A);
556 writel(0x0, mmio + DLY_INT_B);
557
558 /* Clear FLOW_CONTROL */
559 writel(0x0, mmio + FLOW_CONTROL);
560
561 /* Clear INT0 write 1 to clear register */
562 reg_val = readl(mmio + INT0);
563 writel(reg_val, mmio + INT0);
564
565 /* Clear STVAL */
566 writel(0x0, mmio + STVAL);
567
568 /* Clear INTEN0 */
569 writel( INTEN0_CLEAR, mmio + INTEN0);
570
571 /* Clear LADRF */
572 writel(0x0 , mmio + LADRF);
573
574 /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
575 writel( 0x80010,mmio + SRAM_SIZE);
576
577 /* Clear RCV_RING0_LEN */
578 writel(0x0, mmio + RCV_RING_LEN0);
579
580 /* Clear XMT_RING0/1/2/3_LEN */
581 writel(0x0, mmio + XMT_RING_LEN0);
582 writel(0x0, mmio + XMT_RING_LEN1);
583 writel(0x0, mmio + XMT_RING_LEN2);
584 writel(0x0, mmio + XMT_RING_LEN3);
585
586 /* Clear XMT_RING_LIMIT */
587 writel(0x0, mmio + XMT_RING_LIMIT);
588
589 /* Clear MIB */
590 writew(MIB_CLEAR, mmio + MIB_ADDR);
591
592 /* Clear LARF */
593 amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
594
595 /* SRAM_SIZE register */
596 reg_val = readl(mmio + SRAM_SIZE);
597
598 if(lp->options & OPTION_JUMBO_ENABLE)
599 writel( VAL2|JUMBO, mmio + CMD3);
600 #if AMD8111E_VLAN_TAG_USED
601 writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
602 #endif
603 /* Set default value to CTRL1 Register */
604 writel(CTRL1_DEFAULT, mmio + CTRL1);
605
606 /* To avoid PCI posting bug */
607 readl(mmio + CMD2);
608
609 }
610
611 /*
612 This function disables the interrupt and clears all the pending
613 interrupts in INT0
614 */
615 static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
616 {
617 u32 intr0;
618
619 /* Disable interrupt */
620 writel(INTREN, lp->mmio + CMD0);
621
622 /* Clear INT0 */
623 intr0 = readl(lp->mmio + INT0);
624 writel(intr0, lp->mmio + INT0);
625
626 /* To avoid PCI posting bug */
627 readl(lp->mmio + INT0);
628
629 }
630
631 /*
632 This function stops the chip.
633 */
634 static void amd8111e_stop_chip(struct amd8111e_priv* lp)
635 {
636 writel(RUN, lp->mmio + CMD0);
637
638 /* To avoid PCI posting bug */
639 readl(lp->mmio + CMD0);
640 }
641
642 /*
643 This function frees the transmiter and receiver descriptor rings.
644 */
645 static void amd8111e_free_ring(struct amd8111e_priv* lp)
646 {
647
648 /* Free transmit and receive skbs */
649 amd8111e_free_skbs(lp->amd8111e_net_dev);
650
651 /* Free transmit and receive descriptor rings */
652 if(lp->rx_ring){
653 pci_free_consistent(lp->pci_dev,
654 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
655 lp->rx_ring, lp->rx_ring_dma_addr);
656 lp->rx_ring = NULL;
657 }
658
659 if(lp->tx_ring){
660 pci_free_consistent(lp->pci_dev,
661 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
662 lp->tx_ring, lp->tx_ring_dma_addr);
663
664 lp->tx_ring = NULL;
665 }
666
667 }
668 #if AMD8111E_VLAN_TAG_USED
669 /*
670 This is the receive indication function for packets with vlan tag.
671 */
672 static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag)
673 {
674 #ifdef CONFIG_AMD8111E_NAPI
675 return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag);
676 #else
677 return vlan_hwaccel_rx(skb, lp->vlgrp, vlan_tag);
678 #endif /* CONFIG_AMD8111E_NAPI */
679 }
680 #endif
681
682 /*
683 This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb.
684 */
685 static int amd8111e_tx(struct net_device *dev)
686 {
687 struct amd8111e_priv* lp = netdev_priv(dev);
688 int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
689 int status;
690 /* Complete all the transmit packet */
691 while (lp->tx_complete_idx != lp->tx_idx){
692 tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
693 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
694
695 if(status & OWN_BIT)
696 break; /* It still hasn't been Txed */
697
698 lp->tx_ring[tx_index].buff_phy_addr = 0;
699
700 /* We must free the original skb */
701 if (lp->tx_skbuff[tx_index]) {
702 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
703 lp->tx_skbuff[tx_index]->len,
704 PCI_DMA_TODEVICE);
705 dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
706 lp->tx_skbuff[tx_index] = NULL;
707 lp->tx_dma_addr[tx_index] = 0;
708 }
709 lp->tx_complete_idx++;
710 /*COAL update tx coalescing parameters */
711 lp->coal_conf.tx_packets++;
712 lp->coal_conf.tx_bytes += lp->tx_ring[tx_index].buff_count;
713
714 if (netif_queue_stopped(dev) &&
715 lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
716 /* The ring is no longer full, clear tbusy. */
717 /* lp->tx_full = 0; */
718 netif_wake_queue (dev);
719 }
720 }
721 return 0;
722 }
723
724 #ifdef CONFIG_AMD8111E_NAPI
725 /* This function handles the driver receive operation in polling mode */
726 static int amd8111e_rx_poll(struct net_device *dev, int * budget)
727 {
728 struct amd8111e_priv *lp = netdev_priv(dev);
729 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
730 void __iomem *mmio = lp->mmio;
731 struct sk_buff *skb,*new_skb;
732 int min_pkt_len, status;
733 unsigned int intr0;
734 int num_rx_pkt = 0;
735 /*int max_rx_pkt = NUM_RX_BUFFERS;*/
736 short pkt_len;
737 #if AMD8111E_VLAN_TAG_USED
738 short vtag;
739 #endif
740 int rx_pkt_limit = dev->quota;
741 unsigned long flags;
742
743 do{
744 /* process receive packets until we use the quota*/
745 /* If we own the next entry, it's a new packet. Send it up. */
746 while(1) {
747 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
748 if (status & OWN_BIT)
749 break;
750
751 /*
752 * There is a tricky error noted by John Murphy,
753 * <murf@perftech.com> to Russ Nelson: Even with
754 * full-sized * buffers it's possible for a
755 * jabber packet to use two buffers, with only
756 * the last correctly noting the error.
757 */
758
759 if(status & ERR_BIT) {
760 /* reseting flags */
761 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
762 goto err_next_pkt;
763 }
764 /* check for STP and ENP */
765 if(!((status & STP_BIT) && (status & ENP_BIT))){
766 /* reseting flags */
767 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
768 goto err_next_pkt;
769 }
770 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
771
772 #if AMD8111E_VLAN_TAG_USED
773 vtag = status & TT_MASK;
774 /*MAC will strip vlan tag*/
775 if(lp->vlgrp != NULL && vtag !=0)
776 min_pkt_len =MIN_PKT_LEN - 4;
777 else
778 #endif
779 min_pkt_len =MIN_PKT_LEN;
780
781 if (pkt_len < min_pkt_len) {
782 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
783 lp->drv_rx_errors++;
784 goto err_next_pkt;
785 }
786 if(--rx_pkt_limit < 0)
787 goto rx_not_empty;
788 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
789 /* if allocation fail,
790 ignore that pkt and go to next one */
791 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
792 lp->drv_rx_errors++;
793 goto err_next_pkt;
794 }
795
796 skb_reserve(new_skb, 2);
797 skb = lp->rx_skbuff[rx_index];
798 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
799 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
800 skb_put(skb, pkt_len);
801 lp->rx_skbuff[rx_index] = new_skb;
802 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
803 new_skb->data,
804 lp->rx_buff_len-2,
805 PCI_DMA_FROMDEVICE);
806
807 skb->protocol = eth_type_trans(skb, dev);
808
809 #if AMD8111E_VLAN_TAG_USED
810 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
811 amd8111e_vlan_rx(lp, skb,
812 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
813 } else
814 #endif
815 netif_receive_skb(skb);
816 /*COAL update rx coalescing parameters*/
817 lp->coal_conf.rx_packets++;
818 lp->coal_conf.rx_bytes += pkt_len;
819 num_rx_pkt++;
820 dev->last_rx = jiffies;
821
822 err_next_pkt:
823 lp->rx_ring[rx_index].buff_phy_addr
824 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
825 lp->rx_ring[rx_index].buff_count =
826 cpu_to_le16(lp->rx_buff_len-2);
827 wmb();
828 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
829 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
830 }
831 /* Check the interrupt status register for more packets in the
832 mean time. Process them since we have not used up our quota.*/
833
834 intr0 = readl(mmio + INT0);
835 /*Ack receive packets */
836 writel(intr0 & RINT0,mmio + INT0);
837
838 } while(intr0 & RINT0);
839
840 /* Receive descriptor is empty now */
841 dev->quota -= num_rx_pkt;
842 *budget -= num_rx_pkt;
843
844 spin_lock_irqsave(&lp->lock, flags);
845 netif_rx_complete(dev);
846 writel(VAL0|RINTEN0, mmio + INTEN0);
847 writel(VAL2 | RDMD0, mmio + CMD0);
848 spin_unlock_irqrestore(&lp->lock, flags);
849 return 0;
850
851 rx_not_empty:
852 /* Do not call a netif_rx_complete */
853 dev->quota -= num_rx_pkt;
854 *budget -= num_rx_pkt;
855 return 1;
856 }
857
858 #else
859 /*
860 This function will check the ownership of receive buffers and descriptors. It will indicate to kernel up to half the number of maximum receive buffers in the descriptor ring, in a single receive interrupt. It will also replenish the descriptors with new skbs.
861 */
862 static int amd8111e_rx(struct net_device *dev)
863 {
864 struct amd8111e_priv *lp = netdev_priv(dev);
865 struct sk_buff *skb,*new_skb;
866 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
867 int min_pkt_len, status;
868 int num_rx_pkt = 0;
869 int max_rx_pkt = NUM_RX_BUFFERS;
870 short pkt_len;
871 #if AMD8111E_VLAN_TAG_USED
872 short vtag;
873 #endif
874
875 /* If we own the next entry, it's a new packet. Send it up. */
876 while(++num_rx_pkt <= max_rx_pkt){
877 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
878 if(status & OWN_BIT)
879 return 0;
880
881 /* check if err summary bit is set */
882 if(status & ERR_BIT){
883 /*
884 * There is a tricky error noted by John Murphy,
885 * <murf@perftech.com> to Russ Nelson: Even with full-sized
886 * buffers it's possible for a jabber packet to use two
887 * buffers, with only the last correctly noting the error. */
888 /* reseting flags */
889 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
890 goto err_next_pkt;
891 }
892 /* check for STP and ENP */
893 if(!((status & STP_BIT) && (status & ENP_BIT))){
894 /* reseting flags */
895 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
896 goto err_next_pkt;
897 }
898 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
899
900 #if AMD8111E_VLAN_TAG_USED
901 vtag = status & TT_MASK;
902 /*MAC will strip vlan tag*/
903 if(lp->vlgrp != NULL && vtag !=0)
904 min_pkt_len =MIN_PKT_LEN - 4;
905 else
906 #endif
907 min_pkt_len =MIN_PKT_LEN;
908
909 if (pkt_len < min_pkt_len) {
910 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
911 lp->drv_rx_errors++;
912 goto err_next_pkt;
913 }
914 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
915 /* if allocation fail,
916 ignore that pkt and go to next one */
917 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
918 lp->drv_rx_errors++;
919 goto err_next_pkt;
920 }
921
922 skb_reserve(new_skb, 2);
923 skb = lp->rx_skbuff[rx_index];
924 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
925 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
926 skb_put(skb, pkt_len);
927 lp->rx_skbuff[rx_index] = new_skb;
928 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
929 new_skb->data, lp->rx_buff_len-2,PCI_DMA_FROMDEVICE);
930
931 skb->protocol = eth_type_trans(skb, dev);
932
933 #if AMD8111E_VLAN_TAG_USED
934 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
935 amd8111e_vlan_rx(lp, skb,
936 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
937 } else
938 #endif
939
940 netif_rx (skb);
941 /*COAL update rx coalescing parameters*/
942 lp->coal_conf.rx_packets++;
943 lp->coal_conf.rx_bytes += pkt_len;
944
945 dev->last_rx = jiffies;
946
947 err_next_pkt:
948 lp->rx_ring[rx_index].buff_phy_addr
949 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
950 lp->rx_ring[rx_index].buff_count =
951 cpu_to_le16(lp->rx_buff_len-2);
952 wmb();
953 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
954 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
955 }
956
957 return 0;
958 }
959 #endif /* CONFIG_AMD8111E_NAPI */
960 /*
961 This function will indicate the link status to the kernel.
962 */
963 static int amd8111e_link_change(struct net_device* dev)
964 {
965 struct amd8111e_priv *lp = netdev_priv(dev);
966 int status0,speed;
967
968 /* read the link change */
969 status0 = readl(lp->mmio + STAT0);
970
971 if(status0 & LINK_STATS){
972 if(status0 & AUTONEG_COMPLETE)
973 lp->link_config.autoneg = AUTONEG_ENABLE;
974 else
975 lp->link_config.autoneg = AUTONEG_DISABLE;
976
977 if(status0 & FULL_DPLX)
978 lp->link_config.duplex = DUPLEX_FULL;
979 else
980 lp->link_config.duplex = DUPLEX_HALF;
981 speed = (status0 & SPEED_MASK) >> 7;
982 if(speed == PHY_SPEED_10)
983 lp->link_config.speed = SPEED_10;
984 else if(speed == PHY_SPEED_100)
985 lp->link_config.speed = SPEED_100;
986
987 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n", dev->name,
988 (lp->link_config.speed == SPEED_100) ? "100": "10",
989 (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half");
990 netif_carrier_on(dev);
991 }
992 else{
993 lp->link_config.speed = SPEED_INVALID;
994 lp->link_config.duplex = DUPLEX_INVALID;
995 lp->link_config.autoneg = AUTONEG_INVALID;
996 printk(KERN_INFO "%s: Link is Down.\n",dev->name);
997 netif_carrier_off(dev);
998 }
999
1000 return 0;
1001 }
1002 /*
1003 This function reads the mib counters.
1004 */
1005 static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
1006 {
1007 unsigned int status;
1008 unsigned int data;
1009 unsigned int repeat = REPEAT_CNT;
1010
1011 writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
1012 do {
1013 status = readw(mmio + MIB_ADDR);
1014 udelay(2); /* controller takes MAX 2 us to get mib data */
1015 }
1016 while (--repeat && (status & MIB_CMD_ACTIVE));
1017
1018 data = readl(mmio + MIB_DATA);
1019 return data;
1020 }
1021
1022 /*
1023 This function reads the mib registers and returns the hardware statistics. It updates previous internal driver statistics with new values.
1024 */
1025 static struct net_device_stats *amd8111e_get_stats(struct net_device * dev)
1026 {
1027 struct amd8111e_priv *lp = netdev_priv(dev);
1028 void __iomem *mmio = lp->mmio;
1029 unsigned long flags;
1030 /* struct net_device_stats *prev_stats = &lp->prev_stats; */
1031 struct net_device_stats* new_stats = &lp->stats;
1032
1033 if(!lp->opened)
1034 return &lp->stats;
1035 spin_lock_irqsave (&lp->lock, flags);
1036
1037 /* stats.rx_packets */
1038 new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
1039 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
1040 amd8111e_read_mib(mmio, rcv_unicast_pkts);
1041
1042 /* stats.tx_packets */
1043 new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
1044
1045 /*stats.rx_bytes */
1046 new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
1047
1048 /* stats.tx_bytes */
1049 new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
1050
1051 /* stats.rx_errors */
1052 /* hw errors + errors driver reported */
1053 new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1054 amd8111e_read_mib(mmio, rcv_fragments)+
1055 amd8111e_read_mib(mmio, rcv_jabbers)+
1056 amd8111e_read_mib(mmio, rcv_alignment_errors)+
1057 amd8111e_read_mib(mmio, rcv_fcs_errors)+
1058 amd8111e_read_mib(mmio, rcv_miss_pkts)+
1059 lp->drv_rx_errors;
1060
1061 /* stats.tx_errors */
1062 new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1063
1064 /* stats.rx_dropped*/
1065 new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
1066
1067 /* stats.tx_dropped*/
1068 new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1069
1070 /* stats.multicast*/
1071 new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
1072
1073 /* stats.collisions*/
1074 new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
1075
1076 /* stats.rx_length_errors*/
1077 new_stats->rx_length_errors =
1078 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1079 amd8111e_read_mib(mmio, rcv_oversize_pkts);
1080
1081 /* stats.rx_over_errors*/
1082 new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1083
1084 /* stats.rx_crc_errors*/
1085 new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
1086
1087 /* stats.rx_frame_errors*/
1088 new_stats->rx_frame_errors =
1089 amd8111e_read_mib(mmio, rcv_alignment_errors);
1090
1091 /* stats.rx_fifo_errors */
1092 new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1093
1094 /* stats.rx_missed_errors */
1095 new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1096
1097 /* stats.tx_aborted_errors*/
1098 new_stats->tx_aborted_errors =
1099 amd8111e_read_mib(mmio, xmt_excessive_collision);
1100
1101 /* stats.tx_carrier_errors*/
1102 new_stats->tx_carrier_errors =
1103 amd8111e_read_mib(mmio, xmt_loss_carrier);
1104
1105 /* stats.tx_fifo_errors*/
1106 new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1107
1108 /* stats.tx_window_errors*/
1109 new_stats->tx_window_errors =
1110 amd8111e_read_mib(mmio, xmt_late_collision);
1111
1112 /* Reset the mibs for collecting new statistics */
1113 /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
1114
1115 spin_unlock_irqrestore (&lp->lock, flags);
1116
1117 return new_stats;
1118 }
1119 /* This function recalculate the interupt coalescing mode on every interrupt
1120 according to the datarate and the packet rate.
1121 */
1122 static int amd8111e_calc_coalesce(struct net_device *dev)
1123 {
1124 struct amd8111e_priv *lp = netdev_priv(dev);
1125 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
1126 int tx_pkt_rate;
1127 int rx_pkt_rate;
1128 int tx_data_rate;
1129 int rx_data_rate;
1130 int rx_pkt_size;
1131 int tx_pkt_size;
1132
1133 tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
1134 coal_conf->tx_prev_packets = coal_conf->tx_packets;
1135
1136 tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
1137 coal_conf->tx_prev_bytes = coal_conf->tx_bytes;
1138
1139 rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
1140 coal_conf->rx_prev_packets = coal_conf->rx_packets;
1141
1142 rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
1143 coal_conf->rx_prev_bytes = coal_conf->rx_bytes;
1144
1145 if(rx_pkt_rate < 800){
1146 if(coal_conf->rx_coal_type != NO_COALESCE){
1147
1148 coal_conf->rx_timeout = 0x0;
1149 coal_conf->rx_event_count = 0;
1150 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1151 coal_conf->rx_coal_type = NO_COALESCE;
1152 }
1153 }
1154 else{
1155
1156 rx_pkt_size = rx_data_rate/rx_pkt_rate;
1157 if (rx_pkt_size < 128){
1158 if(coal_conf->rx_coal_type != NO_COALESCE){
1159
1160 coal_conf->rx_timeout = 0;
1161 coal_conf->rx_event_count = 0;
1162 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1163 coal_conf->rx_coal_type = NO_COALESCE;
1164 }
1165
1166 }
1167 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
1168
1169 if(coal_conf->rx_coal_type != LOW_COALESCE){
1170 coal_conf->rx_timeout = 1;
1171 coal_conf->rx_event_count = 4;
1172 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1173 coal_conf->rx_coal_type = LOW_COALESCE;
1174 }
1175 }
1176 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
1177
1178 if(coal_conf->rx_coal_type != MEDIUM_COALESCE){
1179 coal_conf->rx_timeout = 1;
1180 coal_conf->rx_event_count = 4;
1181 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1182 coal_conf->rx_coal_type = MEDIUM_COALESCE;
1183 }
1184
1185 }
1186 else if(rx_pkt_size >= 1024){
1187 if(coal_conf->rx_coal_type != HIGH_COALESCE){
1188 coal_conf->rx_timeout = 2;
1189 coal_conf->rx_event_count = 3;
1190 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1191 coal_conf->rx_coal_type = HIGH_COALESCE;
1192 }
1193 }
1194 }
1195 /* NOW FOR TX INTR COALESC */
1196 if(tx_pkt_rate < 800){
1197 if(coal_conf->tx_coal_type != NO_COALESCE){
1198
1199 coal_conf->tx_timeout = 0x0;
1200 coal_conf->tx_event_count = 0;
1201 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1202 coal_conf->tx_coal_type = NO_COALESCE;
1203 }
1204 }
1205 else{
1206
1207 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1208 if (tx_pkt_size < 128){
1209
1210 if(coal_conf->tx_coal_type != NO_COALESCE){
1211
1212 coal_conf->tx_timeout = 0;
1213 coal_conf->tx_event_count = 0;
1214 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1215 coal_conf->tx_coal_type = NO_COALESCE;
1216 }
1217
1218 }
1219 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
1220
1221 if(coal_conf->tx_coal_type != LOW_COALESCE){
1222 coal_conf->tx_timeout = 1;
1223 coal_conf->tx_event_count = 2;
1224 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1225 coal_conf->tx_coal_type = LOW_COALESCE;
1226
1227 }
1228 }
1229 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
1230
1231 if(coal_conf->tx_coal_type != MEDIUM_COALESCE){
1232 coal_conf->tx_timeout = 2;
1233 coal_conf->tx_event_count = 5;
1234 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1235 coal_conf->tx_coal_type = MEDIUM_COALESCE;
1236 }
1237
1238 }
1239 else if(tx_pkt_size >= 1024){
1240 if (tx_pkt_size >= 1024){
1241 if(coal_conf->tx_coal_type != HIGH_COALESCE){
1242 coal_conf->tx_timeout = 4;
1243 coal_conf->tx_event_count = 8;
1244 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1245 coal_conf->tx_coal_type = HIGH_COALESCE;
1246 }
1247 }
1248 }
1249 }
1250 return 0;
1251
1252 }
1253 /*
1254 This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
1255 */
1256 static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1257 {
1258
1259 struct net_device * dev = (struct net_device *) dev_id;
1260 struct amd8111e_priv *lp = netdev_priv(dev);
1261 void __iomem *mmio = lp->mmio;
1262 unsigned int intr0, intren0;
1263 unsigned int handled = 1;
1264
1265 if(unlikely(dev == NULL))
1266 return IRQ_NONE;
1267
1268 spin_lock(&lp->lock);
1269
1270 /* disabling interrupt */
1271 writel(INTREN, mmio + CMD0);
1272
1273 /* Read interrupt status */
1274 intr0 = readl(mmio + INT0);
1275 intren0 = readl(mmio + INTEN0);
1276
1277 /* Process all the INT event until INTR bit is clear. */
1278
1279 if (!(intr0 & INTR)){
1280 handled = 0;
1281 goto err_no_interrupt;
1282 }
1283
1284 /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1285 writel(intr0, mmio + INT0);
1286
1287 /* Check if Receive Interrupt has occurred. */
1288 #ifdef CONFIG_AMD8111E_NAPI
1289 if(intr0 & RINT0){
1290 if(netif_rx_schedule_prep(dev)){
1291 /* Disable receive interupts */
1292 writel(RINTEN0, mmio + INTEN0);
1293 /* Schedule a polling routine */
1294 __netif_rx_schedule(dev);
1295 }
1296 else if (intren0 & RINTEN0) {
1297 printk("************Driver bug! \
1298 interrupt while in poll\n");
1299 /* Fix by disable receive interrupts */
1300 writel(RINTEN0, mmio + INTEN0);
1301 }
1302 }
1303 #else
1304 if(intr0 & RINT0){
1305 amd8111e_rx(dev);
1306 writel(VAL2 | RDMD0, mmio + CMD0);
1307 }
1308 #endif /* CONFIG_AMD8111E_NAPI */
1309 /* Check if Transmit Interrupt has occurred. */
1310 if(intr0 & TINT0)
1311 amd8111e_tx(dev);
1312
1313 /* Check if Link Change Interrupt has occurred. */
1314 if (intr0 & LCINT)
1315 amd8111e_link_change(dev);
1316
1317 /* Check if Hardware Timer Interrupt has occurred. */
1318 if (intr0 & STINT)
1319 amd8111e_calc_coalesce(dev);
1320
1321 err_no_interrupt:
1322 writel( VAL0 | INTREN,mmio + CMD0);
1323
1324 spin_unlock(&lp->lock);
1325
1326 return IRQ_RETVAL(handled);
1327 }
1328
1329 #ifdef CONFIG_NET_POLL_CONTROLLER
1330 static void amd8111e_poll(struct net_device *dev)
1331 {
1332 unsigned long flags;
1333 local_irq_save(flags);
1334 amd8111e_interrupt(0, dev);
1335 local_irq_restore(flags);
1336 }
1337 #endif
1338
1339
1340 /*
1341 This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
1342 */
1343 static int amd8111e_close(struct net_device * dev)
1344 {
1345 struct amd8111e_priv *lp = netdev_priv(dev);
1346 netif_stop_queue(dev);
1347
1348 spin_lock_irq(&lp->lock);
1349
1350 amd8111e_disable_interrupt(lp);
1351 amd8111e_stop_chip(lp);
1352 amd8111e_free_ring(lp);
1353
1354 netif_carrier_off(lp->amd8111e_net_dev);
1355
1356 /* Delete ipg timer */
1357 if(lp->options & OPTION_DYN_IPG_ENABLE)
1358 del_timer_sync(&lp->ipg_data.ipg_timer);
1359
1360 spin_unlock_irq(&lp->lock);
1361 free_irq(dev->irq, dev);
1362
1363 /* Update the statistics before closing */
1364 amd8111e_get_stats(dev);
1365 lp->opened = 0;
1366 return 0;
1367 }
1368 /* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device.
1369 */
1370 static int amd8111e_open(struct net_device * dev )
1371 {
1372 struct amd8111e_priv *lp = netdev_priv(dev);
1373
1374 if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED,
1375 dev->name, dev))
1376 return -EAGAIN;
1377
1378 spin_lock_irq(&lp->lock);
1379
1380 amd8111e_init_hw_default(lp);
1381
1382 if(amd8111e_restart(dev)){
1383 spin_unlock_irq(&lp->lock);
1384 if (dev->irq)
1385 free_irq(dev->irq, dev);
1386 return -ENOMEM;
1387 }
1388 /* Start ipg timer */
1389 if(lp->options & OPTION_DYN_IPG_ENABLE){
1390 add_timer(&lp->ipg_data.ipg_timer);
1391 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
1392 }
1393
1394 lp->opened = 1;
1395
1396 spin_unlock_irq(&lp->lock);
1397
1398 netif_start_queue(dev);
1399
1400 return 0;
1401 }
1402 /*
1403 This function checks if there is any transmit descriptors available to queue more packet.
1404 */
1405 static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp )
1406 {
1407 int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1408 if(lp->tx_skbuff[tx_index] != 0)
1409 return -1;
1410 else
1411 return 0;
1412
1413 }
1414 /*
1415 This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
1416 */
1417
1418 static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
1419 {
1420 struct amd8111e_priv *lp = netdev_priv(dev);
1421 int tx_index;
1422 unsigned long flags;
1423
1424 spin_lock_irqsave(&lp->lock, flags);
1425
1426 tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1427
1428 lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1429
1430 lp->tx_skbuff[tx_index] = skb;
1431 lp->tx_ring[tx_index].tx_flags = 0;
1432
1433 #if AMD8111E_VLAN_TAG_USED
1434 if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
1435 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1436 cpu_to_le16(TCC_VLAN_INSERT);
1437 lp->tx_ring[tx_index].tag_ctrl_info =
1438 cpu_to_le16(vlan_tx_tag_get(skb));
1439
1440 }
1441 #endif
1442 lp->tx_dma_addr[tx_index] =
1443 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1444 lp->tx_ring[tx_index].buff_phy_addr =
1445 (u32) cpu_to_le32(lp->tx_dma_addr[tx_index]);
1446
1447 /* Set FCS and LTINT bits */
1448 wmb();
1449 lp->tx_ring[tx_index].tx_flags |=
1450 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1451
1452 lp->tx_idx++;
1453
1454 /* Trigger an immediate send poll. */
1455 writel( VAL1 | TDMD0, lp->mmio + CMD0);
1456 writel( VAL2 | RDMD0,lp->mmio + CMD0);
1457
1458 dev->trans_start = jiffies;
1459
1460 if(amd8111e_tx_queue_avail(lp) < 0){
1461 netif_stop_queue(dev);
1462 }
1463 spin_unlock_irqrestore(&lp->lock, flags);
1464 return 0;
1465 }
1466 /*
1467 This function returns all the memory mapped registers of the device.
1468 */
1469 static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1470 {
1471 void __iomem *mmio = lp->mmio;
1472 /* Read only necessary registers */
1473 buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1474 buf[1] = readl(mmio + XMT_RING_LEN0);
1475 buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1476 buf[3] = readl(mmio + RCV_RING_LEN0);
1477 buf[4] = readl(mmio + CMD0);
1478 buf[5] = readl(mmio + CMD2);
1479 buf[6] = readl(mmio + CMD3);
1480 buf[7] = readl(mmio + CMD7);
1481 buf[8] = readl(mmio + INT0);
1482 buf[9] = readl(mmio + INTEN0);
1483 buf[10] = readl(mmio + LADRF);
1484 buf[11] = readl(mmio + LADRF+4);
1485 buf[12] = readl(mmio + STAT0);
1486 }
1487
1488
1489 /*
1490 This function sets promiscuos mode, all-multi mode or the multicast address
1491 list to the device.
1492 */
1493 static void amd8111e_set_multicast_list(struct net_device *dev)
1494 {
1495 struct dev_mc_list* mc_ptr;
1496 struct amd8111e_priv *lp = netdev_priv(dev);
1497 u32 mc_filter[2] ;
1498 int i,bit_num;
1499 if(dev->flags & IFF_PROMISC){
1500 writel( VAL2 | PROM, lp->mmio + CMD2);
1501 return;
1502 }
1503 else
1504 writel( PROM, lp->mmio + CMD2);
1505 if(dev->flags & IFF_ALLMULTI || dev->mc_count > MAX_FILTER_SIZE){
1506 /* get all multicast packet */
1507 mc_filter[1] = mc_filter[0] = 0xffffffff;
1508 lp->mc_list = dev->mc_list;
1509 lp->options |= OPTION_MULTICAST_ENABLE;
1510 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1511 return;
1512 }
1513 if( dev->mc_count == 0 ){
1514 /* get only own packets */
1515 mc_filter[1] = mc_filter[0] = 0;
1516 lp->mc_list = NULL;
1517 lp->options &= ~OPTION_MULTICAST_ENABLE;
1518 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1519 /* disable promiscous mode */
1520 writel(PROM, lp->mmio + CMD2);
1521 return;
1522 }
1523 /* load all the multicast addresses in the logic filter */
1524 lp->options |= OPTION_MULTICAST_ENABLE;
1525 lp->mc_list = dev->mc_list;
1526 mc_filter[1] = mc_filter[0] = 0;
1527 for (i = 0, mc_ptr = dev->mc_list; mc_ptr && i < dev->mc_count;
1528 i++, mc_ptr = mc_ptr->next) {
1529 bit_num = (ether_crc_le(ETH_ALEN, mc_ptr->dmi_addr) >> 26) & 0x3f;
1530 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1531 }
1532 amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
1533
1534 /* To eliminate PCI posting bug */
1535 readl(lp->mmio + CMD2);
1536
1537 }
1538
1539 static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info)
1540 {
1541 struct amd8111e_priv *lp = netdev_priv(dev);
1542 struct pci_dev *pci_dev = lp->pci_dev;
1543 strcpy (info->driver, MODULE_NAME);
1544 strcpy (info->version, MODULE_VERS);
1545 sprintf(info->fw_version,"%u",chip_version);
1546 strcpy (info->bus_info, pci_name(pci_dev));
1547 }
1548
1549 static int amd8111e_get_regs_len(struct net_device *dev)
1550 {
1551 return AMD8111E_REG_DUMP_LEN;
1552 }
1553
1554 static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1555 {
1556 struct amd8111e_priv *lp = netdev_priv(dev);
1557 regs->version = 0;
1558 amd8111e_read_regs(lp, buf);
1559 }
1560
1561 static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1562 {
1563 struct amd8111e_priv *lp = netdev_priv(dev);
1564 spin_lock_irq(&lp->lock);
1565 mii_ethtool_gset(&lp->mii_if, ecmd);
1566 spin_unlock_irq(&lp->lock);
1567 return 0;
1568 }
1569
1570 static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1571 {
1572 struct amd8111e_priv *lp = netdev_priv(dev);
1573 int res;
1574 spin_lock_irq(&lp->lock);
1575 res = mii_ethtool_sset(&lp->mii_if, ecmd);
1576 spin_unlock_irq(&lp->lock);
1577 return res;
1578 }
1579
1580 static int amd8111e_nway_reset(struct net_device *dev)
1581 {
1582 struct amd8111e_priv *lp = netdev_priv(dev);
1583 return mii_nway_restart(&lp->mii_if);
1584 }
1585
1586 static u32 amd8111e_get_link(struct net_device *dev)
1587 {
1588 struct amd8111e_priv *lp = netdev_priv(dev);
1589 return mii_link_ok(&lp->mii_if);
1590 }
1591
1592 static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1593 {
1594 struct amd8111e_priv *lp = netdev_priv(dev);
1595 wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1596 if (lp->options & OPTION_WOL_ENABLE)
1597 wol_info->wolopts = WAKE_MAGIC;
1598 }
1599
1600 static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1601 {
1602 struct amd8111e_priv *lp = netdev_priv(dev);
1603 if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1604 return -EINVAL;
1605 spin_lock_irq(&lp->lock);
1606 if (wol_info->wolopts & WAKE_MAGIC)
1607 lp->options |=
1608 (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1609 else if(wol_info->wolopts & WAKE_PHY)
1610 lp->options |=
1611 (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1612 else
1613 lp->options &= ~OPTION_WOL_ENABLE;
1614 spin_unlock_irq(&lp->lock);
1615 return 0;
1616 }
1617
1618 static const struct ethtool_ops ops = {
1619 .get_drvinfo = amd8111e_get_drvinfo,
1620 .get_regs_len = amd8111e_get_regs_len,
1621 .get_regs = amd8111e_get_regs,
1622 .get_settings = amd8111e_get_settings,
1623 .set_settings = amd8111e_set_settings,
1624 .nway_reset = amd8111e_nway_reset,
1625 .get_link = amd8111e_get_link,
1626 .get_wol = amd8111e_get_wol,
1627 .set_wol = amd8111e_set_wol,
1628 };
1629
1630 /*
1631 This function handles all the ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
1632 */
1633
1634 static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
1635 {
1636 struct mii_ioctl_data *data = if_mii(ifr);
1637 struct amd8111e_priv *lp = netdev_priv(dev);
1638 int err;
1639 u32 mii_regval;
1640
1641 if (!capable(CAP_NET_ADMIN))
1642 return -EPERM;
1643
1644 switch(cmd) {
1645 case SIOCGMIIPHY:
1646 data->phy_id = lp->ext_phy_addr;
1647
1648 /* fallthru */
1649 case SIOCGMIIREG:
1650
1651 spin_lock_irq(&lp->lock);
1652 err = amd8111e_read_phy(lp, data->phy_id,
1653 data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1654 spin_unlock_irq(&lp->lock);
1655
1656 data->val_out = mii_regval;
1657 return err;
1658
1659 case SIOCSMIIREG:
1660
1661 spin_lock_irq(&lp->lock);
1662 err = amd8111e_write_phy(lp, data->phy_id,
1663 data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1664 spin_unlock_irq(&lp->lock);
1665
1666 return err;
1667
1668 default:
1669 /* do nothing */
1670 break;
1671 }
1672 return -EOPNOTSUPP;
1673 }
1674 static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1675 {
1676 struct amd8111e_priv *lp = netdev_priv(dev);
1677 int i;
1678 struct sockaddr *addr = p;
1679
1680 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1681 spin_lock_irq(&lp->lock);
1682 /* Setting the MAC address to the device */
1683 for(i = 0; i < ETH_ADDR_LEN; i++)
1684 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1685
1686 spin_unlock_irq(&lp->lock);
1687
1688 return 0;
1689 }
1690
1691 /*
1692 This function changes the mtu of the device. It restarts the device to initialize the descriptor with new receive buffers.
1693 */
1694 static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1695 {
1696 struct amd8111e_priv *lp = netdev_priv(dev);
1697 int err;
1698
1699 if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU))
1700 return -EINVAL;
1701
1702 if (!netif_running(dev)) {
1703 /* new_mtu will be used
1704 when device starts netxt time */
1705 dev->mtu = new_mtu;
1706 return 0;
1707 }
1708
1709 spin_lock_irq(&lp->lock);
1710
1711 /* stop the chip */
1712 writel(RUN, lp->mmio + CMD0);
1713
1714 dev->mtu = new_mtu;
1715
1716 err = amd8111e_restart(dev);
1717 spin_unlock_irq(&lp->lock);
1718 if(!err)
1719 netif_start_queue(dev);
1720 return err;
1721 }
1722
1723 #if AMD8111E_VLAN_TAG_USED
1724 static void amd8111e_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1725 {
1726 struct amd8111e_priv *lp = netdev_priv(dev);
1727 spin_lock_irq(&lp->lock);
1728 lp->vlgrp = grp;
1729 spin_unlock_irq(&lp->lock);
1730 }
1731 #endif
1732
1733 static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
1734 {
1735 writel( VAL1|MPPLBA, lp->mmio + CMD3);
1736 writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1737
1738 /* To eliminate PCI posting bug */
1739 readl(lp->mmio + CMD7);
1740 return 0;
1741 }
1742
1743 static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
1744 {
1745
1746 /* Adapter is already stoped/suspended/interrupt-disabled */
1747 writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
1748
1749 /* To eliminate PCI posting bug */
1750 readl(lp->mmio + CMD7);
1751 return 0;
1752 }
1753 /* This function is called when a packet transmission fails to complete within a resonable period, on the assumption that an interrupts have been failed or the interface is locked up. This function will reinitialize the hardware */
1754
1755 static void amd8111e_tx_timeout(struct net_device *dev)
1756 {
1757 struct amd8111e_priv* lp = netdev_priv(dev);
1758 int err;
1759
1760 printk(KERN_ERR "%s: transmit timed out, resetting\n",
1761 dev->name);
1762 spin_lock_irq(&lp->lock);
1763 err = amd8111e_restart(dev);
1764 spin_unlock_irq(&lp->lock);
1765 if(!err)
1766 netif_wake_queue(dev);
1767 }
1768 static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
1769 {
1770 struct net_device *dev = pci_get_drvdata(pci_dev);
1771 struct amd8111e_priv *lp = netdev_priv(dev);
1772
1773 if (!netif_running(dev))
1774 return 0;
1775
1776 /* disable the interrupt */
1777 spin_lock_irq(&lp->lock);
1778 amd8111e_disable_interrupt(lp);
1779 spin_unlock_irq(&lp->lock);
1780
1781 netif_device_detach(dev);
1782
1783 /* stop chip */
1784 spin_lock_irq(&lp->lock);
1785 if(lp->options & OPTION_DYN_IPG_ENABLE)
1786 del_timer_sync(&lp->ipg_data.ipg_timer);
1787 amd8111e_stop_chip(lp);
1788 spin_unlock_irq(&lp->lock);
1789
1790 if(lp->options & OPTION_WOL_ENABLE){
1791 /* enable wol */
1792 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
1793 amd8111e_enable_magicpkt(lp);
1794 if(lp->options & OPTION_WAKE_PHY_ENABLE)
1795 amd8111e_enable_link_change(lp);
1796
1797 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1798 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1799
1800 }
1801 else{
1802 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1803 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1804 }
1805
1806 pci_save_state(pci_dev);
1807 pci_set_power_state(pci_dev, PCI_D3hot);
1808
1809 return 0;
1810 }
1811 static int amd8111e_resume(struct pci_dev *pci_dev)
1812 {
1813 struct net_device *dev = pci_get_drvdata(pci_dev);
1814 struct amd8111e_priv *lp = netdev_priv(dev);
1815
1816 if (!netif_running(dev))
1817 return 0;
1818
1819 pci_set_power_state(pci_dev, PCI_D0);
1820 pci_restore_state(pci_dev);
1821
1822 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1823 pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1824
1825 netif_device_attach(dev);
1826
1827 spin_lock_irq(&lp->lock);
1828 amd8111e_restart(dev);
1829 /* Restart ipg timer */
1830 if(lp->options & OPTION_DYN_IPG_ENABLE)
1831 mod_timer(&lp->ipg_data.ipg_timer,
1832 jiffies + IPG_CONVERGE_JIFFIES);
1833 spin_unlock_irq(&lp->lock);
1834
1835 return 0;
1836 }
1837
1838
1839 static void __devexit amd8111e_remove_one(struct pci_dev *pdev)
1840 {
1841 struct net_device *dev = pci_get_drvdata(pdev);
1842 if (dev) {
1843 unregister_netdev(dev);
1844 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio);
1845 free_netdev(dev);
1846 pci_release_regions(pdev);
1847 pci_disable_device(pdev);
1848 pci_set_drvdata(pdev, NULL);
1849 }
1850 }
1851 static void amd8111e_config_ipg(struct net_device* dev)
1852 {
1853 struct amd8111e_priv *lp = netdev_priv(dev);
1854 struct ipg_info* ipg_data = &lp->ipg_data;
1855 void __iomem *mmio = lp->mmio;
1856 unsigned int prev_col_cnt = ipg_data->col_cnt;
1857 unsigned int total_col_cnt;
1858 unsigned int tmp_ipg;
1859
1860 if(lp->link_config.duplex == DUPLEX_FULL){
1861 ipg_data->ipg = DEFAULT_IPG;
1862 return;
1863 }
1864
1865 if(ipg_data->ipg_state == SSTATE){
1866
1867 if(ipg_data->timer_tick == IPG_STABLE_TIME){
1868
1869 ipg_data->timer_tick = 0;
1870 ipg_data->ipg = MIN_IPG - IPG_STEP;
1871 ipg_data->current_ipg = MIN_IPG;
1872 ipg_data->diff_col_cnt = 0xFFFFFFFF;
1873 ipg_data->ipg_state = CSTATE;
1874 }
1875 else
1876 ipg_data->timer_tick++;
1877 }
1878
1879 if(ipg_data->ipg_state == CSTATE){
1880
1881 /* Get the current collision count */
1882
1883 total_col_cnt = ipg_data->col_cnt =
1884 amd8111e_read_mib(mmio, xmt_collisions);
1885
1886 if ((total_col_cnt - prev_col_cnt) <
1887 (ipg_data->diff_col_cnt)){
1888
1889 ipg_data->diff_col_cnt =
1890 total_col_cnt - prev_col_cnt ;
1891
1892 ipg_data->ipg = ipg_data->current_ipg;
1893 }
1894
1895 ipg_data->current_ipg += IPG_STEP;
1896
1897 if (ipg_data->current_ipg <= MAX_IPG)
1898 tmp_ipg = ipg_data->current_ipg;
1899 else{
1900 tmp_ipg = ipg_data->ipg;
1901 ipg_data->ipg_state = SSTATE;
1902 }
1903 writew((u32)tmp_ipg, mmio + IPG);
1904 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1905 }
1906 mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1907 return;
1908
1909 }
1910
1911 static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
1912 {
1913 struct amd8111e_priv *lp = netdev_priv(dev);
1914 int i;
1915
1916 for (i = 0x1e; i >= 0; i--) {
1917 u32 id1, id2;
1918
1919 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1920 continue;
1921 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1922 continue;
1923 lp->ext_phy_id = (id1 << 16) | id2;
1924 lp->ext_phy_addr = i;
1925 return;
1926 }
1927 lp->ext_phy_id = 0;
1928 lp->ext_phy_addr = 1;
1929 }
1930
1931 static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
1932 const struct pci_device_id *ent)
1933 {
1934 int err,i,pm_cap;
1935 unsigned long reg_addr,reg_len;
1936 struct amd8111e_priv* lp;
1937 struct net_device* dev;
1938
1939 err = pci_enable_device(pdev);
1940 if(err){
1941 printk(KERN_ERR "amd8111e: Cannot enable new PCI device,"
1942 "exiting.\n");
1943 return err;
1944 }
1945
1946 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
1947 printk(KERN_ERR "amd8111e: Cannot find PCI base address"
1948 "exiting.\n");
1949 err = -ENODEV;
1950 goto err_disable_pdev;
1951 }
1952
1953 err = pci_request_regions(pdev, MODULE_NAME);
1954 if(err){
1955 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, "
1956 "exiting.\n");
1957 goto err_disable_pdev;
1958 }
1959
1960 pci_set_master(pdev);
1961
1962 /* Find power-management capability. */
1963 if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){
1964 printk(KERN_ERR "amd8111e: No Power Management capability, "
1965 "exiting.\n");
1966 goto err_free_reg;
1967 }
1968
1969 /* Initialize DMA */
1970 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) < 0) {
1971 printk(KERN_ERR "amd8111e: DMA not supported,"
1972 "exiting.\n");
1973 goto err_free_reg;
1974 }
1975
1976 reg_addr = pci_resource_start(pdev, 0);
1977 reg_len = pci_resource_len(pdev, 0);
1978
1979 dev = alloc_etherdev(sizeof(struct amd8111e_priv));
1980 if (!dev) {
1981 printk(KERN_ERR "amd8111e: Etherdev alloc failed, exiting.\n");
1982 err = -ENOMEM;
1983 goto err_free_reg;
1984 }
1985
1986 SET_MODULE_OWNER(dev);
1987 SET_NETDEV_DEV(dev, &pdev->dev);
1988
1989 #if AMD8111E_VLAN_TAG_USED
1990 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ;
1991 dev->vlan_rx_register =amd8111e_vlan_rx_register;
1992 #endif
1993
1994 lp = netdev_priv(dev);
1995 lp->pci_dev = pdev;
1996 lp->amd8111e_net_dev = dev;
1997 lp->pm_cap = pm_cap;
1998
1999 spin_lock_init(&lp->lock);
2000
2001 lp->mmio = ioremap(reg_addr, reg_len);
2002 if (lp->mmio == 0) {
2003 printk(KERN_ERR "amd8111e: Cannot map device registers, "
2004 "exiting\n");
2005 err = -ENOMEM;
2006 goto err_free_dev;
2007 }
2008
2009 /* Initializing MAC address */
2010 for(i = 0; i < ETH_ADDR_LEN; i++)
2011 dev->dev_addr[i] =readb(lp->mmio + PADR + i);
2012
2013 /* Setting user defined parametrs */
2014 lp->ext_phy_option = speed_duplex[card_idx];
2015 if(coalesce[card_idx])
2016 lp->options |= OPTION_INTR_COAL_ENABLE;
2017 if(dynamic_ipg[card_idx++])
2018 lp->options |= OPTION_DYN_IPG_ENABLE;
2019
2020 /* Initialize driver entry points */
2021 dev->open = amd8111e_open;
2022 dev->hard_start_xmit = amd8111e_start_xmit;
2023 dev->stop = amd8111e_close;
2024 dev->get_stats = amd8111e_get_stats;
2025 dev->set_multicast_list = amd8111e_set_multicast_list;
2026 dev->set_mac_address = amd8111e_set_mac_address;
2027 dev->do_ioctl = amd8111e_ioctl;
2028 dev->change_mtu = amd8111e_change_mtu;
2029 SET_ETHTOOL_OPS(dev, &ops);
2030 dev->irq =pdev->irq;
2031 dev->tx_timeout = amd8111e_tx_timeout;
2032 dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
2033 #ifdef CONFIG_AMD8111E_NAPI
2034 dev->poll = amd8111e_rx_poll;
2035 dev->weight = 32;
2036 #endif
2037 #ifdef CONFIG_NET_POLL_CONTROLLER
2038 dev->poll_controller = amd8111e_poll;
2039 #endif
2040
2041 #if AMD8111E_VLAN_TAG_USED
2042 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2043 dev->vlan_rx_register =amd8111e_vlan_rx_register;
2044 #endif
2045 /* Probe the external PHY */
2046 amd8111e_probe_ext_phy(dev);
2047
2048 /* setting mii default values */
2049 lp->mii_if.dev = dev;
2050 lp->mii_if.mdio_read = amd8111e_mdio_read;
2051 lp->mii_if.mdio_write = amd8111e_mdio_write;
2052 lp->mii_if.phy_id = lp->ext_phy_addr;
2053
2054 /* Set receive buffer length and set jumbo option*/
2055 amd8111e_set_rx_buff_len(dev);
2056
2057
2058 err = register_netdev(dev);
2059 if (err) {
2060 printk(KERN_ERR "amd8111e: Cannot register net device, "
2061 "exiting.\n");
2062 goto err_iounmap;
2063 }
2064
2065 pci_set_drvdata(pdev, dev);
2066
2067 /* Initialize software ipg timer */
2068 if(lp->options & OPTION_DYN_IPG_ENABLE){
2069 init_timer(&lp->ipg_data.ipg_timer);
2070 lp->ipg_data.ipg_timer.data = (unsigned long) dev;
2071 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
2072 lp->ipg_data.ipg_timer.expires = jiffies +
2073 IPG_CONVERGE_JIFFIES;
2074 lp->ipg_data.ipg = DEFAULT_IPG;
2075 lp->ipg_data.ipg_state = CSTATE;
2076 };
2077
2078 /* display driver and device information */
2079
2080 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
2081 printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n", dev->name,MODULE_VERS);
2082 printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet ", dev->name, chip_version);
2083 for (i = 0; i < 6; i++)
2084 printk("%2.2x%c",dev->dev_addr[i],i == 5 ? ' ' : ':');
2085 printk( "\n");
2086 if (lp->ext_phy_id)
2087 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
2088 dev->name, lp->ext_phy_id, lp->ext_phy_addr);
2089 else
2090 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
2091 dev->name);
2092 return 0;
2093 err_iounmap:
2094 iounmap(lp->mmio);
2095
2096 err_free_dev:
2097 free_netdev(dev);
2098
2099 err_free_reg:
2100 pci_release_regions(pdev);
2101
2102 err_disable_pdev:
2103 pci_disable_device(pdev);
2104 pci_set_drvdata(pdev, NULL);
2105 return err;
2106
2107 }
2108
2109 static struct pci_driver amd8111e_driver = {
2110 .name = MODULE_NAME,
2111 .id_table = amd8111e_pci_tbl,
2112 .probe = amd8111e_probe_one,
2113 .remove = __devexit_p(amd8111e_remove_one),
2114 .suspend = amd8111e_suspend,
2115 .resume = amd8111e_resume
2116 };
2117
2118 static int __init amd8111e_init(void)
2119 {
2120 return pci_register_driver(&amd8111e_driver);
2121 }
2122
2123 static void __exit amd8111e_cleanup(void)
2124 {
2125 pci_unregister_driver(&amd8111e_driver);
2126 }
2127
2128 module_init(amd8111e_init);
2129 module_exit(amd8111e_cleanup);
Stable & featurefull patchset based on Linus's git branch