2 * AMD CS5535/CS5536 GPIO driver.
3 * Allows a user space process to play with the GPIO pins.
5 * Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the smems of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/cdev.h>
18 #include <linux/ioport.h>
19 #include <linux/pci.h>
20 #include <asm/uaccess.h>
24 #define NAME "cs5535_gpio"
26 MODULE_AUTHOR("Ben Gardner <bgardner@wabtec.com>");
27 MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO Pin Driver");
28 MODULE_LICENSE("GPL");
31 module_param(major
, int, 0);
32 MODULE_PARM_DESC(major
, "Major device number");
35 module_param(mask
, ulong
, 0);
36 MODULE_PARM_DESC(mask
, "GPIO channel mask");
38 #define MSR_LBAR_GPIO 0x5140000C
42 static struct pci_device_id divil_pci
[] = {
43 { PCI_DEVICE(PCI_VENDOR_ID_NS
, PCI_DEVICE_ID_NS_CS5535_ISA
) },
44 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_CS5536_ISA
) },
47 MODULE_DEVICE_TABLE(pci
, divil_pci
);
49 static struct cdev cs5535_gpio_cdev
;
51 /* reserve 32 entries even though some aren't usable */
52 #define CS5535_GPIO_COUNT 32
55 #define CS5535_GPIO_SIZE 256
63 static struct gpio_regmap rm
[] =
65 { 0x30, 0x00, '1', '0' }, /* GPIOx_READ_BACK / GPIOx_OUT_VAL */
66 { 0x20, 0x20, 'I', 'i' }, /* GPIOx_IN_EN */
67 { 0x04, 0x04, 'O', 'o' }, /* GPIOx_OUT_EN */
68 { 0x08, 0x08, 't', 'T' }, /* GPIOx_OUT_OD_EN */
69 { 0x18, 0x18, 'P', 'p' }, /* GPIOx_OUT_PU_EN */
70 { 0x1c, 0x1c, 'D', 'd' }, /* GPIOx_OUT_PD_EN */
75 * Gets the register offset for the GPIO bank.
76 * Low (0-15) starts at 0x00, high (16-31) starts at 0x80
78 static inline u32
cs5535_lowhigh_base(int reg
)
80 return (reg
& 0x10) << 3;
83 static ssize_t
cs5535_gpio_write(struct file
*file
, const char __user
*data
,
84 size_t len
, loff_t
*ppos
)
86 u32 m
= iminor(file
->f_path
.dentry
->d_inode
);
88 u32 base
= gpio_base
+ cs5535_lowhigh_base(m
);
93 * Creates the mask for atomic bit programming.
94 * The high 16 bits and the low 16 bits are used to set the mask.
95 * For example, GPIO 15 maps to 31,15: 0,1 => On; 1,0=> Off
100 for (i
= 0; i
< len
; ++i
) {
101 if (get_user(c
, data
+i
))
104 for (j
= 0; j
< ARRAY_SIZE(rm
); j
++) {
106 outl(m1
, base
+ rm
[j
].wr_offset
);
107 /* If enabling output, turn off AUX 1 and AUX 2 */
109 outl(m0
, base
+ 0x10);
110 outl(m0
, base
+ 0x14);
113 } else if (c
== rm
[j
].off
) {
114 outl(m0
, base
+ rm
[j
].wr_offset
);
123 static ssize_t
cs5535_gpio_read(struct file
*file
, char __user
*buf
,
124 size_t len
, loff_t
*ppos
)
126 u32 m
= iminor(file
->f_path
.dentry
->d_inode
);
127 u32 base
= gpio_base
+ cs5535_lowhigh_base(m
);
128 int rd_bit
= 1 << (m
& 0x0f);
133 if (*ppos
>= ARRAY_SIZE(rm
))
136 for (i
= *ppos
; (i
< (*ppos
+ len
)) && (i
< ARRAY_SIZE(rm
)); i
++) {
137 ch
= (inl(base
+ rm
[i
].rd_offset
) & rd_bit
) ?
138 rm
[i
].on
: rm
[i
].off
;
140 if (put_user(ch
, buf
+count
))
146 /* add a line-feed if there is room */
147 if ((i
== ARRAY_SIZE(rm
)) && (count
< len
)) {
148 put_user('\n', buf
+ count
);
156 /* No BKL needed here - "mask" is the only global resource used
157 here and it's a boot-time parameter */
158 static int cs5535_gpio_open(struct inode
*inode
, struct file
*file
)
160 u32 m
= iminor(inode
);
162 /* the mask says which pins are usable by this driver */
163 if ((mask
& (1 << m
)) == 0)
166 return nonseekable_open(inode
, file
);
169 static const struct file_operations cs5535_gpio_fops
= {
170 .owner
= THIS_MODULE
,
171 .write
= cs5535_gpio_write
,
172 .read
= cs5535_gpio_read
,
173 .open
= cs5535_gpio_open
176 static int __init
cs5535_gpio_init(void)
182 if (pci_dev_present(divil_pci
) == 0) {
183 printk(KERN_WARNING NAME
": DIVIL not found\n");
187 /* Grab the GPIO I/O range */
188 rdmsr(MSR_LBAR_GPIO
, low
, hi
);
190 /* Check the mask and whether GPIO is enabled (sanity check) */
191 if (hi
!= 0x0000f001) {
192 printk(KERN_WARNING NAME
": GPIO not enabled\n");
196 /* Mask off the IO base address */
197 gpio_base
= low
& 0x0000ff00;
201 * 31-29,23 : reserved (always mask out)
212 * If a mask was not specified, be conservative and only allow:
213 * 1,2,5,6,10-13,24,25,27
220 if (!request_region(gpio_base
, CS5535_GPIO_SIZE
, NAME
)) {
221 printk(KERN_ERR NAME
": can't allocate I/O for GPIO\n");
226 dev_id
= MKDEV(major
, 0);
227 retval
= register_chrdev_region(dev_id
, CS5535_GPIO_COUNT
,
230 retval
= alloc_chrdev_region(&dev_id
, 0, CS5535_GPIO_COUNT
,
232 major
= MAJOR(dev_id
);
236 release_region(gpio_base
, CS5535_GPIO_SIZE
);
240 printk(KERN_DEBUG NAME
": base=%#x mask=%#lx major=%d\n",
241 gpio_base
, mask
, major
);
243 cdev_init(&cs5535_gpio_cdev
, &cs5535_gpio_fops
);
244 cdev_add(&cs5535_gpio_cdev
, dev_id
, CS5535_GPIO_COUNT
);
249 static void __exit
cs5535_gpio_cleanup(void)
251 dev_t dev_id
= MKDEV(major
, 0);
253 cdev_del(&cs5535_gpio_cdev
);
254 unregister_chrdev_region(dev_id
, CS5535_GPIO_COUNT
);
255 release_region(gpio_base
, CS5535_GPIO_SIZE
);
258 module_init(cs5535_gpio_init
);
259 module_exit(cs5535_gpio_cleanup
);